JPH0574805A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To inhibit the generation of a corner defect by slightly displacing the amorphous formation of a shallow section and a deep section in the lateral direction and forming stages as amorphous layers formed at two stages. CONSTITUTION:A gate oxide film 2 and a polysilicon gate electrode 3 are formed onto a P-type semiconductor substrate 1. A first amorphous layer 5 is formed by implanting ions 4. A sidewall oxide film 7 is shaped, ions 8 are implanted, and a second amorphous layer 9 is formed at a position slightly displaced in the lateral direction from the first amorphous layer 5. The depth of the first amorphous layer 5 is set in depth shallower than that of the second amorphous layer 9 at that time. Electrically inactive ions are used as the ions 4, 8 to be implanted. Accordingly, generation of corner defects can be inhibited.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ion implantation method for suppressing the generation of defects in a super high density semiconductor device.

[0002]

2. Description of the Related Art In a conventional semiconductor device, since the density of elements is increased, stress is increased and defects are apt to grow. LDD shown in FIG.
(Lightly Doped Drain) type MOS
The occurrence of defects in a conventional semiconductor device will be described by taking a transistor as an example. In the figure, 1 indicates a semiconductor substrate. Reference numeral 2 indicates a gate oxide film of the MOS transistor. Three
Indicates the gate electrode of the transistor. Reference numeral 7 indicates a sidewall oxide film for forming an LDD structure. Reference numeral 8 denotes an arsenic ion beam for forming source / drain regions. This ion beam forms an amorphous layer 5 in the silicon substrate 1 due to implantation damage. When the amorphous region 5 is crystal-grown by heat treatment, as shown in the figure, crystal growth from the lower side of the substrate is upward, and crystal growth from two kinds of perpendicular directions that grow laterally occurs. For this reason, when the shape is an inversely tapered amorphous shape 12 due to a vertical shape, a crystal discontinuity, which is a corner defect 13, is present at a portion where the both ends collide and hit, and a nucleus for defect generation is formed. It When some stress is applied to the defect area, the growth of defects occurs from the void 13. Regarding the formation of voids in this section, Tamura et al. Have described Nuclear Instruments and Methods.
and Method) B37 / 38 (1989)
p. 329.

As an example of this solution, the inventor of the present application has proposed a method of changing the amorphous shape by forming a large angle with respect to the gate to suppress the generation of voids (Japanese Patent Application No. 2- 140951). This method will be described with reference to FIG. Usually 7 after forming the sidewall oxide film 7 ^. Source / drain implantation at 1 implantation angle
4 to 20 ^. After the above implantation, the amorphous layer 5 is formed at a gentle angle 15 toward the silicon surface. For this reason, the influence of the plane orientation becomes small at the time of recovery by heat treatment, and the formation of voids disappears or becomes small. However, this method requires a device that can handle a large implantation angle, and cannot handle any device. In particular, it was difficult to perform this large tilt angle implantation with a large current ion implantation apparatus.

[0004]

As described above, in the structure of the conventional example shown in FIG. 4, since the corner defect 13 is formed, the corner of the large crystal defect is inevitably generated, and the pn junction portion of the precise device is inevitable. The leakage current increases because the pn region, which is very sensitive to defects, crosses the pn region. As a result, sufficient characteristics cannot be expected, and the yield of non-defective products is significantly reduced. This problem is not limited to the implantation for forming the source / drain, but becomes a problem when the amorphous layer is locally formed by performing high-concentration implantation using a mask. As a result, in today's world where ultra-high density has progressed, the mechanical stress generated in the process increases and the frequency of leakage current increases, making it impossible to manufacture non-defective products.

In view of the above problems, it is an object of the present invention to provide a process method for suppressing corner defects by a simple method without special ion implantation of an amorphous layer formed by ion implantation. ..

[0006]

In order to solve the above-mentioned problems, in the manufacturing method of the present invention, the amorphous formation of the shallow portion and the deep portion is formed in two steps in such a manner that the amorphous portions are laterally divided. By providing a step as a crystalline layer, the state of crystal recovery is changed to change the state of solid phase growth to suppress the occurrence of corner defects.

[0007]

According to the present invention, by changing the shape of the amorphous state by the above-mentioned constitution, the formation of voids during recrystallization changes, the recovery process changes, and the formation of corner defects disappears or does not disappear. Also becomes smaller. As a result, the frequency of growth of defects caused by stress disappears.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device manufacturing method according to an embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a sectional view showing steps in an embodiment of the present invention. In FIG. 1, 1 is a p-type semiconductor substrate, 2 is a gate oxide film with a thickness of 10 nm, and 3 is 250 nm.
A thick polysilicon gate electrode is shown. Numeral 4 is a fluorinated germanium ion beam, which is injected with a dose amount of 1 × 10 ¹⁴ cm −2 at an acceleration energy of 50 keV. Phosphorus ion is also 50 ke
An n-type layer 6 was formed by implanting a dose amount of 1 × 10 ¹³ cm −2 with V acceleration energy. In FIG. 1b, 7 forms a side wall oxide film and implants high concentration arsenic 8. At this time, when p-type boron ions or the like that cannot form an amorphous layer are implanted, a germanium fluoride ion or the like is also implanted to form the amorphous layer. Here, it is an important point that the thickness of the amorphous layer 5 formed in step a is set to be shallower than the depth of the amorphous layer 9 formed in step b. Further, in the step a, in the case of n-type, it is usual to implant phosphorus ions. This phosphorus implantation may of course be formed with a large angle after forming the sidewalls.

As described above, according to this embodiment, an amorphous layer is once formed in a shallow place, and a deep amorphous layer is formed next to it, so that only a deep amorphous layer is formed as in the conventional case. It will be different from when it is done. As a result, the shape of the amorphous layer can be made a shape in which corner defects are unlikely to occur.

FIG. 2 shows a comparison of the effect between a conventional example and a schematic diagram after crystal growth. The shape of the amorphous layer of the present invention and the corner after recovery are shown. According to the present invention, corner defects can be almost eliminated. Also, regarding the electrical characteristics, the probability of an abnormal increase in the leakage current decreases, and it almost never occurs. Further, in the embodiment, the forming ion of the amorphous layer is fluorinated germanium, but other ions may be silicon or silicon fluoride, or argon or xenon inert in germanium or silicon. Further, in the embodiment used here, the MOS transistor is used, but it can be used in any case in the high concentration implantation accompanied by the amorphous formation. FIG. 3 shows the change in the yield when the test transistor group having a scale equivalent to 1 MORAM is formed depending on the presence or absence of the first implantation as the dependence of the dose amount of the first germanium fluoride ion. The source and drain were applied with 5 V and 100 nA or less were shown as non-defective products.

[0012]

As described above, according to the present invention, by forming the amorphous layer at the same time as the LDD implantation, it is possible to suppress the formation of the corner defect which becomes the nucleus of the generation of the large defect.

[Brief description of drawings]

FIG. 1 is a process sectional view in a first embodiment of the present invention.

FIG. 2 is a schematic diagram for explaining the operation in the same embodiment.

FIG. 3 is a diagram showing a yield in a test device.

FIG. 4 is a cross-sectional view showing crystal growth when no conventional measures are taken.

FIG. 5 is a cross-sectional view showing improvements in high incidence angle injection.

[Explanation of symbols]

 1 silicon substrate 2 gate oxide film 3 gate electrode 4 germanium fluoride ion beam 5 first amorphous layer 9 second amorphous layer

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location 8617-4M H01L 21/265 L

Claims (5)

[Claims] 1. A step of implanting ions for forming a first amorphous layer on a surface of a semiconductor substrate having a step, and depositing a deposited thin film and anisotropically etching the deposited film only on the stepped portion. A method of manufacturing a semiconductor device, comprising at least a step of leaving and a step of implanting ions under a condition that a second amorphous layer can be formed at a position deeper than the first amorphous layer. 2. A method for manufacturing a semiconductor device, wherein the ions for forming the first and second amorphous layers are electrically inactive ions. 3. The method for manufacturing a semiconductor device according to claim 1, wherein the ions for forming the first amorphous layer are germanium, silicon, or molecular ions containing this element. 4. A method of manufacturing a semiconductor device, wherein ions for ion implantation for forming the second amorphous layer are ions containing arsenic or phosphorus. 5. A method of manufacturing a semiconductor device, wherein the step structure according to claim 1 is a gate electrode of a MOS transistor.