JPH0574676A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH0574676A
JPH0574676A JP3040177A JP4017791A JPH0574676A JP H0574676 A JPH0574676 A JP H0574676A JP 3040177 A JP3040177 A JP 3040177A JP 4017791 A JP4017791 A JP 4017791A JP H0574676 A JPH0574676 A JP H0574676A
Authority
JP
Japan
Prior art keywords
layer
electron beam
resist
exposed
photoresist
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3040177A
Other languages
Japanese (ja)
Inventor
Yasumasa Misawa
康巨 三澤
Kazuhiko Hirokawa
一彦 廣川
Hitoshi Kojima
均 小島
Akihiro Yokoyama
明弘 横山
Yasushi Sakata
靖 坂田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujifilm Business Innovation Corp
Original Assignee
Fuji Xerox Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Xerox Co Ltd filed Critical Fuji Xerox Co Ltd
Priority to JP3040177A priority Critical patent/JPH0574676A/en
Publication of JPH0574676A publication Critical patent/JPH0574676A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70Microphotolithographic exposure; Apparatus therefor
    • G03F7/70425Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
    • G03F7/7045Hybrid exposures, i.e. multiple exposures of the same area using different types of exposure apparatus, e.g. combining projection, proximity, direct write, interferometric, UV, x-ray or particle beam

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)

Abstract

PURPOSE:To form a resist pattern which can be realized through a simple process and has an excellent resisting property at the time of working a base layer by forming an electron-beam resist layer on a photoresist layer and exposing and developing the photoresist layer after the electron beam resist layer is exposed to and developed by an electron beam after plotting the pattern. CONSTITUTION:After a photoresist layer 5 which reacts to light is formed on a base layer 1 to be worked, an electron-beam resist layer 6 which is sensitive to an electron beam and blocks light to which the layer 5 is sensitive is formed on the layer 5. Then a pattern corresponding to an electronic beam is plotted on the layer 6 and the layer is exposed to and developed by the electron beam. After developing the layer 6, the photoresist layer 5 is exposed and developed by using the developed resist layer 6A as a mask. In the succeeding process, for example, after the base layer 1 is etched by an RIE method by using the resist patterns 6A and 5A as masks, the patterns are transferred to the layer 1.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半導体装置の製造方法に
関し、特に半導体装置中のパタ−ンを形成するためのリ
ソグラフィに関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to lithography for forming a pattern in a semiconductor device.

【0002】[0002]

【従来の技術】電子線リソグラフィに使用される電子線
レジストは未だ充分な感度のものが得られていない。そ
のため、通常のホトリソグラフィと同様の単純な1層の
レジストを使用した場合、パタ−ン描画の時間が長くな
ってしまうという問題がある。レジストを薄くすれば描
画時間は短くなるが、その後のエッチングに耐えるため
には、レジスト層はある程度の厚さが必要である。特に
下層に凹凸のある半導体装置の製造に使用されるレジス
ト層は1〜2μmの厚さが必要とされている。
2. Description of the Related Art Electron beam resists used in electron beam lithography have not yet been obtained with sufficient sensitivity. Therefore, when a simple one-layer resist similar to that used in normal photolithography is used, there is a problem that the pattern drawing time becomes long. The thinner the resist, the shorter the drawing time, but the resist layer must have a certain thickness to withstand the subsequent etching. In particular, the resist layer used for manufacturing a semiconductor device having an uneven lower layer is required to have a thickness of 1 to 2 μm.

【0003】上記の問題を解決する1つの方法として、
3層レジストが使用されることがある。図2は3層レジ
ストを使用した従来の半導体装置の製造工程図である。
As one method for solving the above problems,
A three layer resist may be used. FIG. 2 is a manufacturing process diagram of a conventional semiconductor device using a three-layer resist.

【0004】先ず、工程(a) において、加工対象の金属
層、絶縁膜層、あるいはシリコン基板等よりなる下地層
1上に、通常の光に対して感光を有しない下層レジスト
層2を形成し、次の工程(b) において、半導体酸化膜よ
りなる中間層3を形成し、引続く工程(c) において、電
子線レジスト層4を形成する。そして工程(d) におい
て、電子線レジスト層上に電子線描画、現像した後、工
程(e) ,(f) において、上層をマスクとしてエッチング
条件を変えて下層を順次エッチングすることにより、工
程(f) に示すようにレジストパタ−ンが形成される。工
程(f) 以後は、下層レジスト層2をマスクとして、下地
層1をエッチングしたり、イオン注入したりする。
First, in step (a), a lower resist layer 2 which is not sensitive to ordinary light is formed on a base layer 1 made of a metal layer, an insulating film layer, a silicon substrate or the like to be processed. In the next step (b), the intermediate layer 3 made of a semiconductor oxide film is formed, and in the subsequent step (c), the electron beam resist layer 4 is formed. Then, in step (d), after electron beam drawing and development on the electron beam resist layer, in steps (e) and (f), the lower layer is sequentially etched by changing the etching conditions using the upper layer as a mask. A resist pattern is formed as shown in f). After the step (f), the underlying layer 1 is etched or ions are implanted using the lower resist layer 2 as a mask.

【0005】[0005]

【発明が解決しようとする課題】しかしながら上記の製
造工程によると、電子線レジスト層を薄くすることによ
り描画時間を短くできるが、1層レジストに比べて大幅
に工程が複雑になるという問題点がある。
However, according to the above manufacturing process, the drawing time can be shortened by making the electron beam resist layer thin, but there is a problem that the process is considerably complicated as compared with the one-layer resist. is there.

【0006】本発明の目的は、簡単な工程で実現でき且
つ下地層の加工の際の耐性が良好なレジストパタ−ンが
形成されるようにした半導体装置の製造方法を提供する
ことにある。
An object of the present invention is to provide a method of manufacturing a semiconductor device in which a resist pattern which can be realized by a simple process and which has good resistance when processing an underlayer is formed.

【0007】[0007]

【課題を解決するための手段】本発明は前記問題点を解
決するために、光に反応するホトレジスト層を加工対象
の下地層上に形成する工程と、電子線に対して感光し且
つ前記ホトレジスト層が感光可能な光を阻止する電子線
レジスト層を前記ホトレジスト層上に形成する工程と、
前記電子線レジスト層上に電子線に対応の描画をして電
子線により該電子線レジスト層に露光・現像する工程
と、前記現像後の電子線レジスト層をマスクとして前記
ホトレジスト層に露光・現像する工程とを含む半導体装
置の製造方法とした。
In order to solve the above-mentioned problems, the present invention comprises a step of forming a photoresist layer which reacts with light on an underlayer to be processed, and a step of exposing the photoresist to an electron beam. A step of forming an electron beam resist layer on the photoresist layer, the layer blocking light that is sensitive to light;
A step of drawing a pattern corresponding to an electron beam on the electron beam resist layer to expose / develop the electron beam resist layer with an electron beam; and a step of exposing / developing the photoresist layer with the developed electron beam resist layer as a mask The method for manufacturing a semiconductor device includes the steps of:

【0008】[0008]

【作用】本発明によれば、加工対象の下地層上に、光に
反応するホトレジスト層が形成され、その上に、電子線
に対して感光し且つホトレジスト層が感光可能にしてい
る光を阻止する電子線レジスト層が形成される。そして
電子線レジスト層上に描画して電子線により露光する
と、電子線レジスト層には該描画によるレジストパタ−
ンが現像され、ホトレジスト層はそのままになってい
る。次にその上からホトレジスト層に感光可能な光によ
り露光・現像するとホトレジスト層は先に描画されて現
像された電子線レジスト層によってマスクされて、該描
画によるレジストパタ−ンが形成される。
According to the present invention, a photoresist layer which reacts with light is formed on the underlayer to be processed, and the photoresist layer which is exposed to an electron beam and blocks the photoresist layer to be exposed to light is blocked. An electron beam resist layer is formed. When an electron beam resist layer is drawn and exposed by an electron beam, the electron beam resist layer is exposed to the resist pattern by the drawing.
The photoresist layer has been developed, leaving the photoresist layer intact. Next, when the photoresist layer is exposed to light and developed from above, the photoresist layer is masked by the electron beam resist layer which has been previously drawn and developed to form a resist pattern by the drawing.

【0009】[0009]

【実施例】図1は本発明の一実施例を示す半導体装置の
製造工程図である。
FIG. 1 is a manufacturing process diagram of a semiconductor device showing an embodiment of the present invention.

【0010】同図において、1は図2におけると同様な
加工対象の下地層であり、この場合、例えばアルミニウ
ム膜よりなる。
In the figure, reference numeral 1 designates an underlayer to be processed as in FIG. 2, and in this case, it is made of, for example, an aluminum film.

【0011】5は特定な光(後記するg線)に感光する
いわゆるホトレジスト層で、工程(a) により、下地層1
上に、例えば東京応化工業製のTSMR8700を塗布し、12
0℃で40秒間ベ−キングして約1.4μm厚に形成さ
れる。
Numeral 5 is a so-called photoresist layer which is exposed to a specific light (g-line which will be described later).
For example, apply TSMR8700 manufactured by Tokyo Ohka Kogyo Co., Ltd.
It is baked at 0 ° C. for 40 seconds to have a thickness of about 1.4 μm.

【0012】6は電子線レジスト層で、水銀ランプのg
線(波長436nm)に対して不透明になるように、例
えばチバガイギ−社のチヌビン等の色素が混入されてい
る。該電子線レジスト層は、工程(b) により、ホトレジ
スト層5上に塗布され、90℃で5分間ベ−キングされ
て約0.6μm厚さに形成される。
Reference numeral 6 is an electron beam resist layer, which is g of a mercury lamp.
A dye such as Tinubin manufactured by Ciba-Geigy Co. is mixed so as to be opaque to the line (wavelength 436 nm). The electron beam resist layer is applied on the photoresist layer 5 in step (b) and baked at 90 ° C. for 5 minutes to have a thickness of about 0.6 μm.

【0013】そして工程(c) において、電子線に対応の
描画をして、30KV、4μC/cm2 の電子線により電
子線レジスト層6に露光されてアルカリ現像液で100
秒間現像される。その結果、工程(c) に示すように該描
画によるレジストパタ−ン6Aが形成される。このとき
ホトレジスト層5は感光しない。
Then, in the step (c), the electron beam resist layer 6 is exposed by an electron beam of 30 KV and 4 μC / cm 2 by drawing an image corresponding to the electron beam, and then exposed to 100 with an alkaline developer.
It is developed for 2 seconds. As a result, a resist pattern 6A is formed by the drawing as shown in step (c). At this time, the photoresist layer 5 is not exposed to light.

【0014】引続く工程(d) ,(e) において、水銀ラン
プのg線を用いて、その上から0.2秒間にわたって露
光され、ホトレジスト用のアルカリ現像液で現像され
る。その結果、先のレジストパタ−ン6Aをマスクとし
たレジストパタ−ン5Aが形成される。
In the subsequent steps (d) and (e), exposure is carried out for 0.2 seconds from above using the g-line of a mercury lamp and development is carried out with an alkali developing solution for photoresist. As a result, a resist pattern 5A is formed using the resist pattern 6A as a mask.

【0015】その後の工程においては、レジストパタ−
ン6A,5Aをマスクとして、下地層1が例えばRIE
法によりエッチングされて、下地層1に該パタ−ンが転
写される。
In the subsequent steps, the resist pattern
The underlying layer 1 is, for example, RIE
Then, the pattern is transferred to the underlayer 1.

【0016】本実施例は2層レジストでパタ−ンが形成
されるために、従来の3層レジストによる場合に比べ
て、工程が簡略化される。
In this embodiment, since the pattern is formed by the two-layer resist, the process is simplified as compared with the conventional three-layer resist.

【0017】また、従来の3層レジストに必要としてい
た中間層のエッチング及び下層レジストのエッチングが
不要であり、光照射及び現像は従来の光リソグラフィの
装置を用いて従来の製造条件でできるため、追加の装置
や工程を必要としない。
Further, the etching of the intermediate layer and the etching of the lower layer resist, which are required for the conventional three-layer resist, are unnecessary, and light irradiation and development can be performed under the conventional manufacturing conditions using the conventional photolithography apparatus. No additional equipment or steps required.

【0018】さらに、形成されたホトレジスト層5は通
常の光リソグラフィのレジストであるため、その後のエ
ッチングの条件も旧来の1層レジストの場合と同様にし
て行うことができ、3層レジストの場合のように、エッ
チングマスクとなるレジスト材質が従来のフォトレジス
トと異なることによるエッチング条件の変更も必要な
い。
Further, since the formed photoresist layer 5 is a resist for ordinary photolithography, the subsequent etching conditions can be the same as in the case of the conventional one-layer resist, and in the case of the three-layer resist. As described above, it is not necessary to change the etching conditions due to the fact that the resist material used as the etching mask is different from that of the conventional photoresist.

【0019】なお、図1の工程(e) では、フォトレジス
ト5の現像後に電子線レジスト層6が残存するとした
が、両レジストの材質、現像法によっては電子線レジス
ト層6の全部または一部が除去されるが、本発明の趣旨
にいささかも反するものではない。
In step (e) of FIG. 1, the electron beam resist layer 6 remains after the development of the photoresist 5. However, the electron beam resist layer 6 may be wholly or partially exposed depending on the material of both resists and the developing method. Is removed, but it does not in any way go against the spirit of the present invention.

【0020】[0020]

【発明の効果】以上説明したように本発明によれば、加
工対象の下地層上に、ホトレジスト層と、該ホトレジス
ト層への露光を阻止するようにした電子線レジスト層と
を順次形成し、電子線レジスト層上に描画して、電子線
によって露光・現像し、これをマスクとしてホトレジス
ト層に露光して現像するようにしたので、共通の描画に
より電子線レジスト層とホトレジスト層とによる2重の
レジストパタ−ンが形成されて、これらが以後の下地層
のエッチング等のために強靭なマスクとして機能する。
そして2層レジストによってレジストパタ−ンを形成し
たので、従来の3層によるものに比べて簡単な工程で実
現できる。
As described above, according to the present invention, a photoresist layer and an electron beam resist layer for preventing exposure to the photoresist layer are sequentially formed on the underlying layer to be processed, Since the pattern is drawn on the electron beam resist layer, exposed and developed by the electron beam, and the photoresist layer is exposed and developed using this as a mask, the double drawing by the electron beam resist layer and the photoresist layer is performed by common drawing. Resist pattern is formed, and these functions as a tough mask for subsequent etching of the underlying layer.
Since the resist pattern is formed by the two-layer resist, it can be realized by a simple process as compared with the conventional three-layer resist.

【図面の簡単な説明】[Brief description of drawings]

【図1】 本発明の実施例を示す半導体装置の製造工程
FIG. 1 is a manufacturing process diagram of a semiconductor device showing an embodiment of the present invention.

【図2】 従来例を示す半導体装置の製造工程図FIG. 2 is a manufacturing process diagram of a semiconductor device showing a conventional example.

【符号の説明】[Explanation of symbols]

1…下地層、5…ホトレジスト層、6…電子線レジスト
層、5A,6A…レジストパタ−ン。
1 ... Underlayer, 5 ... Photoresist layer, 6 ... Electron beam resist layer, 5A, 6A ... Resist pattern.

フロントページの続き (72)発明者 横山 明弘 神奈川県海老名市本郷2274番地 富士ゼロ ツクス株式会社海老名事業所内 (72)発明者 坂田 靖 神奈川県海老名市本郷2274番地 富士ゼロ ツクス株式会社海老名事業所内Front page continued (72) Inventor Akihiro Yokoyama 2274 Hongo, Ebina City, Kanagawa Prefecture Fuji Zero Tsukus Co., Ltd.Ebina Business Office (72) Inventor Yasushi Sakata 2274 Hongo, Ebina City, Kanagawa Prefecture Ebina Business Office Fuji Zero Tsuxu Co., Ltd.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 光に反応するホトレジスト層を加工対象
の下地層上に形成する工程と、 電子線に対して感光し且つ前記ホトレジスト層が感光可
能な光を阻止する電子線レジスト層を前記ホトレジスト
層上に形成する工程と、 前記電子線レジスト層上に電子線に対応の描画をして電
子線により該電子線レジスト層に露光・現像する工程
と、 前記現像後の電子線レジスト層をマスクとして前記ホト
レジスト層に露光・現像する工程とを含む、 ことを特徴とする半導体装置の製造方法。
1. A step of forming a photoresist layer which is sensitive to light on an underlayer to be processed, and an electron beam resist layer which is exposed to an electron beam and blocks light which can be exposed to the photoresist layer. Forming on the electron beam resist layer, drawing on the electron beam resist layer corresponding to an electron beam, exposing and developing the electron beam resist layer with the electron beam, and masking the electron beam resist layer after development. And a step of exposing and developing the photoresist layer as described above.
JP3040177A 1991-03-06 1991-03-06 Manufacture of semiconductor device Pending JPH0574676A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3040177A JPH0574676A (en) 1991-03-06 1991-03-06 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3040177A JPH0574676A (en) 1991-03-06 1991-03-06 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH0574676A true JPH0574676A (en) 1993-03-26

Family

ID=12573496

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3040177A Pending JPH0574676A (en) 1991-03-06 1991-03-06 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH0574676A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008258562A (en) * 2007-02-08 2008-10-23 Matsushita Electric Ind Co Ltd Pattern formation method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008258562A (en) * 2007-02-08 2008-10-23 Matsushita Electric Ind Co Ltd Pattern formation method

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