JPH0574192A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To evaluate a circuit when a malfunction is caused by a method wherein a test pad is added to a chip and a word-line control circuit is controlled. CONSTITUTION:The logical sum of a signal from a test pad 9 with reference to an input pulse signal 8 which has been synchronized with an address signal is taken by means of an OR circuit 14, and an output signal 10 is obtained. When a high level or a low level is applied to the test pad 9, a word line 17 is selected by the signal of the test pad 9 or the input pulse signal with reference to a block control signal 11 and decoding signals 13. Consequently, the control operation or the noncontrol operation of the word line can be changed over by means of a pulse which has been synchronized with the address signal. Thereby, when a malfunction is caused, the word line is changed over arbitrarily, and it is possible to judge whether the malfunction has been caused by a pulse width or whether a memory cell itself is problematic.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device,
Particularly, it relates to a word line selection circuit controlled by a pulse generated in synchronization with an address signal.

[0002]

2. Description of the Related Art FIG. 3 is a circuit diagram showing a conventional example of this type of semiconductor memory device.

In FIG. 3, an input signal 1 is a convex pulse signal which is generated in synchronization with an address signal, and the AND circuit 5 takes a logic with a block control signal 2 which divides a memory cell array into blocks. 4 is output.

At this time, the block control signal 2 is low (LO
If it is at the (W) level, the output signal 4 is always at the LOW level. When the input signal 1 is at the high level, the output signal 4 outputs the high level only when the input signal 1 is at the high level. The word line selection circuit selects the word line by ANDing the decode signal 3 from the address and the output signal 4 with the AND circuit 6. At this time, the word line is selected only when the output signal 4 is at the HIGH level.

That is, in the conventional circuit, the selection period is controlled by the pulse signal 1 generated in synchronization with the word line 7, and the writing and reading operations of the information to the memory cell are completed within this word line selection period. It is a circuit that does.

[0006]

In the conventional semiconductor memory device described above, since the word line selection period is controlled by the pulse generated in synchronization with the address, the write and read operations are performed within the word line selection period. If it cannot be completed and malfunction occurs, it is very difficult to clarify whether the malfunction is caused by the memory cell itself or the write / read operation, and it takes a lot of time for circuit evaluation. It has the disadvantage of spending.

It is an object of the present invention to provide a semiconductor memory device which solves the above-mentioned drawbacks and enables quick circuit evaluation.

[0008]

The semiconductor memory device of the present invention has a structure having a word line selection circuit which is synchronized with an input address signal and is controlled by a pulse output having a preset pulse width. In addition, by adding a test pad other than a normal pad on the chip, the word line selection circuit can be controlled or non-controlled by the pulse.

[0009]

1 is a circuit diagram showing a semiconductor memory device according to an embodiment of the present invention.

In FIG. 1, in this embodiment, an OR circuit 14 which receives a signal from a test pad 9 and a pulse signal as input.
And the output signal 10 of the OR circuit 14 and the block control signal 1
AND circuit (block selection circuit) 15 which receives 1 and
And the output signal 12 and the decode signal 13 of the AND circuit 15
An AND circuit (word line selection circuit) 16 having inputs and is provided, and a word line 17 is provided as an output.

The input signal 8 which is a convex pulse signal generated in synchronization with the address signal and the signal from the test pad 9 are logically output by the OR circuit 14 to output the signal 10.

At this time, if the HIGH level is applied to the test pad 9 other than the normal pad, the output signal 10 becomes the HIGH level. In this case, the block control signal 1
If 1 and the decode signal 13 are HIGH level, the word line 17 is selected regardless of the pulse signal 8.

When the LOW level is applied to the test pad 9, the output signal 10 becomes the HIGH level only when the pulse signal 8 is at the HIGH level.

That is, similar to the conventional example, the pulse signal 8
Thus, the word line 17 is selected or deselected.

As described above, the semiconductor memory device of this embodiment is
It includes a test pad capable of switching between two operations of controlling and non-controlling the word line by a pulse generated in synchronization with the address signal.

FIG. 2 is a circuit diagram showing a semiconductor memory device according to another embodiment of the present invention.

In FIG. 2, the power source voltage 19 is used in this embodiment.
Transfer circuit 34 connected to the pulse signal 1
A transfer circuit 35 connected to the input terminal 8;
The test pad 20, an inverter circuit 29, an AND circuit 36 that receives the input signal 25 and the block control signal 26, and an AND circuit 37 that receives the output signal 27 of the AND circuit 36 and the decode signal 28 are provided. ing.

Here, the output of the AND circuit 37 becomes a word line. The transfer circuit 34 includes an N-channel transistor 30 and a P-channel transistor 31.
The transfer circuit 35 includes the P-channel transistor 3
2 and an N-channel transistor 33.

The test pad 20 turns on or off the transfer circuits 34 and 35 by applying an arbitrary voltage, and the input signal 18 which is a convex pulse signal generated in synchronization with the address or the power supply. Any of the HIGH level signals supplied from the voltage 19 is transmitted to the input signal 25 on the drain side of the transfer circuit.

At this time, when a HIGH level is applied to the test pad 20, the N-channel transistor 30 turns ON.
Then, the P-channel transistor 32 is turned off. Further, since the signal 21 is output to the signal circuit 22 by the inverter circuit 29 at the LOW level, the P-channel transistor 31 is turned off.
N, and the N-channel transistor 33 is turned off.

That is, the transfer circuit 34 is turned on, and the HIGH level supplied from the power supply voltage 19 is set to the drain side of the transfer circuit, that is, the signal 23.
Communicate to.

On the contrary, the transfer circuit 35 is turned off, the pulse signal 18 is not transmitted to the drain side of the transfer circuit, and the signal 24 is in a high impedance state.

Therefore, the signal 25 becomes HIGH level, and the block control signal 26 and the decode signal 28 become HIGH.
If it is at H level, the word line 38 is selected regardless of the pulse signal 18.

When a LOW level is applied to the test pad 20, the pulse signal 18 is transmitted to the signals 24 and 25 on the drain side of the transfer circuit, contrary to the above case, and the pulse signal 18 is transmitted as in the conventional example. Thus, selection and deselection of word lines are performed.

As described above, by operating the test pads 9 and 20 from the outside, the method of selecting the word line can be arbitrarily switched.

[0026]

As described above, according to the present invention, the semiconductor memory device is made to write or read data based on the pulse output of the preset pulse width, and when the operation occurs, the chip By applying a HIGH or LOW level to a test pad other than the normal pad provided above, the selection method of the word line can be arbitrarily switched between the pulse signal and the selection method. Therefore, it is possible to easily determine whether the malfunction has occurred in relation to the pulse width of the pulse output or whether there is a problem in the memory cell itself.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a semiconductor memory device according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing another embodiment of the present invention.

FIG. 3 is a circuit diagram showing a conventional word line selection circuit.

[Explanation of symbols]

 1,8,18 pulse signal 2,11,26 block control signal 3,13,28 decode signal 4,12,27 AND circuit output signal 5,15,36 AND circuit (block selection circuit) 6,16,37 AND Circuit (word line selection circuit) 7,17,38 Word line 9,20 Test pad 10 Output signal of OR circuit 14 OR circuit 19 Power supply voltage 21 Signal from test pad 22 Output signal of inverter circuit 23,24 Drain of transfer circuit Side signal 25 Input signal of AND circuit 29 Inverter circuit 30, 33 N channel transistor 31, 32 P channel transistor 34, 35 Transfer circuit

Claims (2)

[Claims] 1. In a semiconductor memory device having a word line selection circuit which is synchronized with an input address signal and is controlled by a pulse output having a preset pulse width, a test pad other than a normal pad is added on a chip. By so doing, the semiconductor memory device is characterized in that the word line selection circuit can be controlled or not controlled by the pulse. 2. The semiconductor memory device according to claim 1, wherein a block selection circuit is interposed between the test pad and the word line selection circuit.