JPH0573414A - Cache memory control system - Google Patents

Abstract

PURPOSE:To decrease the utilization quantity of a system bus. CONSTITUTION:In a computer system, bus masters 10, 20 having a cache memory and a bus master 30 having no cache memory are mixed in a state that they share a main storage device 24 and the system executes write-back control. A control line 31 discriminates whether the bus master for making an access of the main storage device 24 is the bus masters 10, 20 having a cache memory or the bus master 30 having no cache memory. At the time of read from the bus master 30 having no cache memory, the state of the cache memory in which the read block is stored in a state that the occupancy is unchanged is maintained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cache memory control system, and more particularly to a cache memory control system for a computer system in which a bus master having a cache memory and a bus master not having a cache memory coexist.

[0002]

2. Description of the Related Art FIG. 5 is a block diagram showing an example of a conventional computer system. In the figure, 10 and 20 are processors that are bus masters, and the cache memory 1
1 and 21 and monitor control circuits 12 and 22, respectively, and are connected to the system bus 23. A main storage device (MS) 24 is connected to the system bus 23.

The supervisory control circuits 12 and 22 respectively monitor read and write access to the system bus 23, and perform read / write control and state control of the cache memories 11 and 21.

First, the write-back method will be described. At the time of reading, the processors 10 and 20 read data from the cache memories 11 and 21 if there is a corresponding block on the cache memories 11 and 12 (hit). If there is no corresponding block (miss hit), the corresponding block is cached from the main memory 24 to the cache memory 1
The data is read onto the processors 1 and 21 as well as the processors 10 and 20.

At this time, if there is no empty block on the cache memories 11 and 21, for example, a known LRU is used.
A block to be swapped out is determined according to some rule such as a (least recently used) algorithm, and if the content of the block does not match the content of the main memory 24, the content is written to the main memory 24. (This operation is called write-back) is read to the block, but if the contents of the block match the contents of the main storage device, the contents of the block are discarded, The contents of the main memory 24 are overwritten.

At the time of writing, the cache memories 11 and 2
If there is a corresponding block in 1 (hit), write there. If there is no corresponding block (miss hit), the corresponding block is retrieved from the main memory 24 in the cache memory 11,
Read on 21 and write there.

At this time, when there is no empty block in the cache memories 11 and 21, a block to be swapped out is determined according to a rule such as the LRU algorithm, and the contents of the block do not match the contents of the main memory 24. In this case, the contents are written in the main memory device 24 and then read to the block.
If it matches the contents of 4, the contents of the block are discarded and the contents of the main memory 24 are overwritten on the block.

The write-back method is often used in a multiprocessor system because the common bus is used in a small amount.

However, when the write-back method is adopted in the multiprocessor system, it is necessary to perform control for eliminating the contradiction between a plurality of cache memories.

In general, in order to prevent the above-mentioned contradiction, the state information for the input inhibition state is added to each memory block for control, but the most primitive method will be described here.

To describe the types of states, P (Private clean): the private unmodified cache memories 11 and 12 have the same contents as the main memory 24 without the copy of the same block (there is only one).

D (Private Dirty): The contents are different from those of the main memory device 24 because there is no copy of the same block in the exclusive-use changed cache memories 11 and 12 (only exists).

S (Shared clean): Both the shared unmodified cache memories 11 and 12 have a copy of the same block, and have the same contents as the main memory 24.

I (Invalid): Invalid Invalid block with no contents.

Next, the operation in each state will be described.

P (Private clean): Unchanged occupancy read: Read from the cache memories 11 and 12. The state is unchanged.

Write: Write to the cache memories 11 and 12. The state becomes D.

Read from another bus master: The state becomes S.

Write from another bus master: The state becomes I.

D (Private Dirty): Occupancy changed Read: Read from the cache memories 11 and 12. The state is unchanged.

Write: Write only to the cache memories 11 and 12. The state is unchanged.

Read from another bus master: The corresponding block is written back and the state becomes S (or I).

Write from another bus master: Writes back the corresponding block and the state becomes I.

S (Shared clean): Shared unmodified Read: Read from the cache memories 11 and 12. The state is unchanged.

Write: Write to the cache memories 11 and 12 as well as to the main memory 24. The state becomes P.

Read from other master: State is unchanged.

Write from another master: The state becomes I.

I (Invalid): Invalid Read: Main memory 24 to cache memory 11, 1
2 and the processors 10, 20. The state becomes S.

Write: Read from the main memory 24 to the cache memories 11 and 21, and then the cache memory 1
Write to 1, 21. The state becomes D.

[0030]

In the conventional system, as shown in FIG. 3A, for example, P of the cache memory 11 is used.
When the processor 20 reads the main storage device 24 using the system bus 23 for the block in the state, since the cache memory 11 is a read from another bus master, the block in the cache memory 11 is changed from the P state to the S state. Thereafter, when the processor 11 writes this block, the state changes from the S state to the P state and the system bus 2
3 is used to write to the main memory 24. Further, when the processor 11 writes this block, the P state changes to the D state, and even if the processor 11 subsequently writes this block, the D state is maintained.

Here, a bus master having no cache such as a DMAC (Direct Memory Access Controller) is connected to the system, and the cache memory 11
When the DMAC reads the main memory 24 for a block in the P state, the block in the cache memory 11 changes from the P state to the S state, and when the processor 10 next writes this block, the block changes from the S state to the P state. The main memory 24 is written using the system bus 23.

However, since the DMAC does not have a cache, it is not necessary to change the state of the block of the cache memory 11 even when the DMAC reads the main memory device 24. It is not necessary in the conventional method, but the P state is changed to the S state. For this reason, when the processor 11 next writes this block, the main memory 24 is written and the amount of use of the system bus 23 increases.

The present invention has been made in view of the above points,
An object of the present invention is to provide a cache memory control method in which the usage of the system bus is reduced.

[0034]

According to the cache memory control system of the present invention, a bus master having a cache memory and a bus master not having a cache memory are mixed by sharing a main storage device and a write-back control is performed in a computer system. In the cache memory control method, the bus master that accesses the main memory has a control line that distinguishes between a bus master having a cache memory and a bus master having no cache memory, and is read when a bus master having no cache memory is read. Maintains the state of the cache memory that stores the block in the occupied unmodified state.

Further, at the time of writing from a bus master having no cache memory, the write data is fetched into the cache memory which stores the written block in an unaltered state which is occupied or shared and maintains the state of the cache memory.

[0036]

According to the present invention, when the bus master having no cache memory is read, the state of the block in the unoccupied state of the cache memory is maintained so that the system bus is not used at the next write access to this block. When a bus master without a cache memory is writing, if the block is in the unoccupied or shared state of the cache memory, the write data is fetched and the state is maintained so that the system bus is not used during the next read access of this block. In addition, the usage of the system bus can be reduced.

[0037]

1 is a block diagram of an embodiment of a computer system according to the present invention. 5, those parts which are the same as those corresponding parts in FIG. 5 are designated by the same reference numerals, and a description thereof will be omitted.

In FIG. 1, the system bus 23 is connected to the processors 10 and 20 having a cache memory and the DMAC 30 having no cache memory.
The DMAC 30 is a bus master that can occupy the system bus 23 like the processors 10 and 20. Also DMAC
A control line 31 is provided between 30 and the monitoring control circuits 12 and 22, and the control line 31 notifies the monitoring control circuits 12 and 22 whether or not the DMAC 30 is accessing the main memory device 24.

The supervisory control circuits 12 and 22 are cache memories 1 from the processors 10 and 20 with which they are associated.
When there is a read / write access of 1, 21, P,
The same state control as in the prior art is performed in each of the D, S, and I states, but when there is a read / write access from another bus master, the state control processing shown in FIG. 2 is performed according to the state of the control line 31.

In FIG. 2, in step 40, it is determined whether the access from another bus master is a read or a write. If read, whether the block accessed in each of steps 41, 42 and 43 is the P state or the D state. , S state is determined. If it is in the P state, it is determined in step 44 whether the DMAC 30 is accessed, the state is changed to S in step 45 only when a bus master having a cache memory other than the DMAC 30 is accessed, and P is set when the DMAC 30 having no cache memory is accessed. Stay in the state. If it is in the D state, the block is written back in step 46 and the state is set to S (or I).

The states are maintained in the S state and the I state.

If the access from another bus master is a write, it is determined in steps 51, 52 and 53 whether the accessed block is in the P state, the D state or the S state. If it is in the P state, it is determined in step 54 whether the DMAC 30 is accessed, and only when the bus master having a cache memory other than the DMAC 30 is accessed, the step 5 is executed.
Change the state to S in 5 and do not have a cache memory D
When the MAC 30 is accessed, the data from the system bus 23 is taken into the cache and the P state is maintained. If it is in the D state, the corresponding block is written back in step 56 and the state is set to I.

If it is in the S state, DMAC3 is executed in step 57.
It is determined whether the access is 0, the state is changed to I in step 58 only when the bus master having the cache memory is accessed, and the DMAC 30 having no cache memory is accessed.
At the time of access, the data from the system bus 23 is taken into the cache and the S state is maintained. In the I state, that state is maintained.

When the DMAC 30 reads the main memory device 24 for a block in the P state of the cache memory 11, the block in the cache memory 11 maintains the P state as shown in FIG. When 11 writes this block, it changes from the P state to the D state. During this period, the main memory 2
Do not write to 4. Therefore, the system bus 23
The usage of is reduced. Further, in the conventional method, when another bus master writes the main storage device 24 to a block in the P state of the cache memory 11, the block of the cache memory 11 changes from the P state to the I state as shown in FIG. Next, when the processor 10 reads this block, the main memory 2 is accessed via the system bus 23.
4 is read by the cache memory 11 and the processor 10 to change from the I state to the S state.

However, in the system of the present invention, for the block in the P state of the cache memory 11, the bus master having no cache memory such as the DMAC 30 is the main storage device 2.
When 4 is written, the block of the cache memory 11 maintains the P state as shown in FIG. 4B, and when the processor 10 next reads this block, the cache memory 11 is read and maintains the P state. , It is not necessary to use the system bus 23. Therefore, the usage of the system bus 23 is reduced.

The control line 31 may be built in the system bus 23.

[0047]

As described above, according to the cache memory control system of the present invention, the usage of the system bus can be reduced, which is extremely useful in practice.

[Brief description of drawings]

FIG. 1 is a block configuration diagram of a system according to the present invention.

FIG. 2 is a flowchart of a state control process.

FIG. 3 is a diagram showing a state change.

FIG. 4 is a diagram showing a state change.

FIG. 5 is a block configuration diagram of a conventional system.

[Explanation of symbols]

 10, 20 processor 11, 21 cache memory 12, 21 supervisory control circuit 23 system bus 24 main memory device 30 DMAC 31 control line

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yasutoshi Sakurai 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (72) Inventor Tatsuya Yamaguchi, 1015, Kamikodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited

Claims (2)

[Claims] 1. A bus master (1) having a cache memory
0, 20) and a bus master (30) having no cache memory are shared by sharing the main memory device (24), and in the cache memory control method of the computer system for performing write-back control, access to the main memory device is performed. A bus master (30) having a control line for distinguishing a bus master (10, 20) having the cache memory or a bus master (30) having no cache memory from the bus master (30) having no cache memory At times, a cache memory control method is characterized in that the state of a cache memory that stores a read block in an unmodified state is maintained. 2. The cache memory control method according to claim 1, wherein when writing from a bus master (30) that does not have the cache memory, the written block is stored in an unaltered state of being occupied or shared. A cache memory control method characterized by fetching write data to and maintaining the state of the cache memory.