JPH0573400A - Memory control system - Google Patents

Abstract

PURPOSE:To shorten the time required to specify a track and to obtain high throughput by writing or retrieving chain information or searching a free track at the time of data input by a control part without the intervention of a CPU. CONSTITUTION:The control part 17 searches for the free track in the document control area in a memory 16 and writes it in a next track address register(TAR) 3. An address counter 2 receives the chain information from the TAR 3 and outputs a next track address request signal to the control part 17. At the same time, data begin to be transferred from a data bus 100 to the memory 16. The control part 17 informs the host CPU 13 of the track number only when the track is the head track of a page. The control part 17 receives the next track address request signal and searches for a free track again. Once the free track is found, its track number is written in the TAR 3 and after free track information and control information are written in the control area, chain processing is performed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory control system, and more particularly to a memory control system with a built-in document management function for time-divisionally accessing different data strings input / output through a plurality of data paths to a memory managed by itself.

[0002]

2. Description of the Related Art Conventionally, this type of memory control system has a structure as shown in FIG. Here, four data paths 100-400 are installed,
Of course, it does not matter if it increases or decreases. Further, although all the data paths in the figure are bidirectional, the case where the data path 100 is an input and the data path 200 is an output will be described here. The data input from the data path 100 is written in the memory 16 via the FIFO 1 and the data selector 14. At this time, it is written by the input of the memory write signal MWR output from the control unit 17.

The memory 16 is managed in track units, and is composed of, for example, 8 [KB / track]. The memory 16 enters a data write state when a memory write signal MWR is input from the control unit 17, and enters a data read state when a memory read signal MRD is input. Further, the data is sent and received to and from each FIFO via the selector 14, and the address is supplied from each address counter via the selector 15.

The memory area for storing input data is
It is designated by writing an address from the host CPU 13 to the next track address register 3. here,
Since empty tracks are scattered in the memory 16, the host C
The PU 13 needs to search for an empty track by itself. The address counter 2 fetches the next track address designated by the host CPU 13 from the next track address register 3, and the memory write signal MWR1 from the controller 17 is obtained.
The address in the track is incremented in synchronization with (the same signal as the above MWR).

The output of the address counter 2 is passed through the address selector 15 as a memory address to the memory 1
6 is input. When a truck is filled with data,
The address counter has the values shown in FIG. At the same time, the address counter 2 issues an interrupt signal INT1 to the host CPU 13, fetches the next track NO from the next track address register 3, and clears the in-track address.

When the host CPU 13 detects the interrupt signal INT1, it writes the next track NO in the next track address register 3. Therefore, if the next track is not designated by the host CPU 13 before the current track is filled, the input of data from the data path 100 is temporarily stopped.

Next, the operation of outputting data from the data path 200 will be described. First, the memory track NO to be output from the host CPU 13 is written in the next track address register 6. The address counter 5 fetches the next track NO from the next track address register 6, and the memory read signal MRD2 (the above-mentioned MR
The address in the track is incremented in synchronization with the same signal as D).

The output of the address counter 5 is the selector 15
Is input to the memory 16 as a memory address via. The memory 16 outputs corresponding data according to the given address and the memory read signal MRD, and the data is output to the data path 200 via the selector 14 and the FIFO 4.

The address counter 5 takes in the next track NO from the next track address register 6 and, at the same time, outputs an interrupt signal INT2 to the host CPU 13. When detecting the interrupt signal INT2, the host CPU 13 writes the next track NO in the next track address register 6. Therefore, if the next track NO is not specified from the host CPU 13 before the reading of the current track is completed, the output of data to the data path 200 is temporarily stopped.

Although the data paths 100 and 200 have been described above, the same applies to the operations of the data paths 300 and 400.

As described above, the memory 16 is accessed from a plurality of data paths.
Since the connection to 6 is performed in a time-sharing manner, by appropriately setting the capacity of each FIFO, it becomes possible to transfer data continuously without waiting for each data path.

As described above, in the conventional memory control system, when writing data to the memory, it is necessary to search for an empty track and store the next track NO (chain information). Further, when reading data from the memory, it is necessary to search the corresponding track according to the chain information stored in advance. Conventionally, the host CPU 13 performed all of these tasks. That is, it is a so-called program I / O control method.

However, if the designation of the next track NO after the search of the empty track or the search of the chain information is delayed, the data transfer between the tracks to the data path is temporarily stopped, resulting in the data transfer. There is a drawback that the throughput cannot be high.

[0014]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional drawbacks, and an object of the present invention is to provide a memory control system capable of increasing the throughput of data transfer.

[0015]

A memory control system according to the present invention has an area for storing empty track information indicating whether or not all the data tracks in its own memory are empty tracks and data to be stored in the tracks. A memory having an area for storing chain information indicating a track in which the following data is stored; and means for accessing the memory in track units based on the empty track information and the chain information. To do.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the memory control system according to the present invention.
The same parts as are indicated by the same reference numerals. The memory control system of this embodiment is based on a so-called DMA control system in which the control unit 17 performs a search, unlike the system of FIG. 2 in which the host CPU searches for an empty track.

In the present system, first, as a premise, a part of the memory for accumulating data is secured as a document management area. That is, as shown in FIG. 4, the memory 13 has a document management area for managing the storage area in addition to the original data storage area.

As shown in FIG. 5, the document management area is composed of a management area for each track from NO0000 track to the last track in the storage area. 16-bit information is stored in the management area for each track, and bits D0 to D12 indicate the track number (chain information) in which the next data following the data to be stored in that track is stored.
Bit D15 is empty track information indicating whether the track is empty or has been accumulated.

Bits D13 and D14 are control information indicating the position of the accumulation track in a page (for example, transmission / reception data of a facsimile machine) composed of one or more tracks. Here, bits D13 and D14
Is 0, it indicates that the track is a track in the middle of the page. Bit D13 is "1", bit D
When 14 is "0", it indicates that the track is the top track of the page, and bit D13 is "0" and bit D14.
"1" indicates that the track is the last track of the page. When the bits D13 and D14 are both "1", it indicates that the track is the first and last tracks of the page, that is, 1 track / 1 page.

Returning to FIG. 1, the operation of this system will be specifically described. It is assumed that the data path 100 is an input setting and the data path 200 is an output setting.

Based on the input setting instruction of the data path 100 from the host CPU 13, the control unit 17 searches the document management area in the memory 16 for an empty track. Specifically, the track of bit D15 = 0 in the management area is found. When a free track is found as a result of the search, the control unit 17 writes the corresponding track NO in the next track address register 3 and writes free track information and control information in its management area. Specifically, "1" (meaning accumulated) is written in the bit D15, "0" is written in the bit D14, and "1" (meaning the first track) is written in the bit D13.

The address counter 2 fetches the chain information (next track NO) from the next track address register 3 and sends the next track address request signal R to the control unit 17.
Outputs EQ1. At the same time, the data is taken from the data path 100 and the transfer to the memory 16 is started. Further, only when the track is the top track of the page, the control unit 17 notifies the host CPU 13 of the track number.

The control section 17 receives the next track address request signal REQ1 and again searches for an empty track.

When the empty track is found, the control section 17 writes the corresponding track number in the next track address register and writes the empty track information and the control information in the management area. Further, the management area of the previous track is accessed, and the corresponding track No. is used as chain information for bits D0 to D12
Write to.

The above operation is sequentially repeated to form a track NO connection (data chain state) within one page.

On the other hand, when outputting data, the following operation is performed. First, the control unit 17 writes the corresponding track number into the next track address register 6 based on the output setting designation of the data path 200 from the host CPU 13 and the instruction of the top track number of the page.

Then, the address counter 5 causes the next track address register 6 to transfer the accumulated track NO.
To output the next track address request signal REQ2 to the control unit 17. At the same time, the data of the corresponding track is sequentially read from the memory 16 and the data path
To start the transfer.

The control unit 17 receives the request signal REQ2,
The chain information is retrieved from the management area of the previous track, and the corresponding track number is written in the next track address register again. The above operation is repeated, the chain information is searched, and the track No. is connected to transfer and output the data of one page.

It is obvious that this system can be used not only for data transfer in a facsimile machine but also for memory control of various information processors.

[0031]

As described above, according to the present invention, the control unit executes the search for an empty track and the writing of the chain information without inputting the CPU during the data input, and the search of the chain information during the data output. Since it is executed without the CPU, the time required for specifying the track is short, and as a result, the data transfer is not interrupted in track units, and high throughput can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a memory control system according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a conventional memory control system.

FIG. 3 is a conceptual diagram showing the contents of an address counter.

FIG. 4 is a conceptual diagram showing internal storage information of a memory in FIG.

5 is a conceptual diagram showing the contents of a document management area in FIG.

[Explanation of symbols]

 1, 4, 7, 10 FIFO 2, 5, 8, 11 Address counter 3, 6, 9, 12 Secondary track address register 14, 15 Selector 16 Memory 17 Control unit

Claims (1)

[Claims] 1. An area for storing empty track information indicating whether the track is an empty track for all data tracks in its own memory, and the next data following the data to be stored in the track are stored. A memory control system comprising: a memory having an area for storing chain information indicating an existing track; and means for accessing the memory in track units based on the empty track information and the chain information.