JPH0573163A - Voltage generation circuit - Google Patents

Voltage generation circuit

Info

Publication number
JPH0573163A
JPH0573163A JP3235262A JP23526291A JPH0573163A JP H0573163 A JPH0573163 A JP H0573163A JP 3235262 A JP3235262 A JP 3235262A JP 23526291 A JP23526291 A JP 23526291A JP H0573163 A JPH0573163 A JP H0573163A
Authority
JP
Japan
Prior art keywords
power supply
transistors
intermediate potential
voltage
voltage generating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3235262A
Other languages
Japanese (ja)
Inventor
Yoshihiko Mizukami
義彦 水上
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC IC Microcomputer Systems Co Ltd
Original Assignee
NEC IC Microcomputer Systems Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC IC Microcomputer Systems Co Ltd filed Critical NEC IC Microcomputer Systems Co Ltd
Priority to JP3235262A priority Critical patent/JPH0573163A/en
Publication of JPH0573163A publication Critical patent/JPH0573163A/en
Pending legal-status Critical Current

Links

Landscapes

  • Control Of Electrical Variables (AREA)
  • Amplifiers (AREA)

Abstract

PURPOSE:To generate the voltage source capable of obtaining an arbitrary intermediate potential, canceling the temperature characteristic and performing the absorption and distortion with low power consumption and with few fluctuation due to the condition of load. CONSTITUTION:The circuit is composed of a means for generating the intermediate potential consisting of a constant voltage generating the intermediate potential from a pair of power supply terminals 1 and 2 and resistance 4 and a buffer circuit consisting of transistors 9 and 10 connecting a pair of complementary emitters to be supplied from this intermediate potential as the intermediate power supply of the other circuit by resistance 17 and 18. Between the bases of a pair of transistors 9 and 10, as many as diodes 11 and 12 are connected in the forward direction of the base emitter of a pair of transistors 9 and 10.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は電圧発生回路に関し、特
に吸い込み掃き出し可能な中間電位の電圧発生回路に関
する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a voltage generating circuit, and more particularly to an intermediate potential voltage generating circuit capable of sucking and sweeping.

【0002】[0002]

【従来の技術】従来のこの種の電圧発生回路の一例を、
図3に示す。例えば、電子交換機の加入者回路等におい
ては、電源電圧が標準で48Vと非常に大きなものとな
っている。従って、加入者回路等を構成する演算増幅器
5,6は、回路耐圧を保つ為に、又電源電圧が大きいこ
とによる消費電力低減の為に、演算増幅器5,6の電源
ラインを、図3の様に、縦積み接続する事が多い。
2. Description of the Related Art An example of a conventional voltage generating circuit of this type is
As shown in FIG. For example, in a subscriber circuit of an electronic exchange, the power supply voltage is 48 V as a standard, which is very large. Therefore, the operational amplifiers 5 and 6 constituting the subscriber circuit are connected to the power supply lines of the operational amplifiers 5 and 6 in FIG. 3 in order to maintain the circuit withstand voltage and to reduce the power consumption due to the large power supply voltage. Similarly, it is often connected vertically.

【0003】即ち、従来の一例においては端子1,2間
に接続された電源は、ツェナーダイオードやダイオード
等の組み合せによる定電圧発生回路3と抵抗4とによっ
て中間電位を発生させ、演算増幅器5の高電源側は電源
端子1に、低電源側は中間電位に接続し、又演算増幅器
6の高電源側は中間電位に、低電源側は電源端子2に接
続する事によって実現していた。
That is, in a conventional example, a power source connected between terminals 1 and 2 generates an intermediate potential by a constant voltage generating circuit 3 and a resistor 4 which are a combination of Zener diodes, diodes, etc. The high power supply side is connected to the power supply terminal 1, the low power supply side is connected to the intermediate potential, the high power supply side of the operational amplifier 6 is connected to the intermediate potential, and the low power supply side is connected to the power supply terminal 2.

【0004】次に、従来のこの種の電圧発生回路の別の
例を図4に示す。端子1,2間に接続された電源は、定
電圧発生回路3と抵抗4とによって中間電位を発生し、
さらに抵抗7,8によって任意の電位に分圧設定した
後、トランジスタ9,10によってバッファリングさ
れ、演算増幅器5,6の縦積み接続部の電源となってい
た。
Next, another example of the conventional voltage generating circuit of this type is shown in FIG. The power supply connected between the terminals 1 and 2 generates an intermediate potential by the constant voltage generating circuit 3 and the resistor 4,
Further, after dividing the voltage to an arbitrary potential by the resistors 7 and 8, the voltage was buffered by the transistors 9 and 10 and served as a power source for the vertical connection of the operational amplifiers 5 and 6.

【0005】[0005]

【発明が解決しようとする課題】前述した従来の電圧発
生回路の一例においては、縦積み接続部の電位は定電圧
発生回路3によって決定される為、任意の中間電位を得
る為にはツェナーダイオードとダイオードとの組み合せ
が複雑となり、又温度特性のキャンセルも難かしくな
り、あまり現実的で無いという欠点が有った。
In one example of the above-mentioned conventional voltage generating circuit, the potential of the vertically-stacked connection portion is determined by the constant voltage generating circuit 3. Therefore, in order to obtain an arbitrary intermediate potential, a Zener diode is required. However, the combination of the diode and the diode becomes complicated, and it is difficult to cancel the temperature characteristic, which is not practical.

【0006】例えば、電源端子2から見て10Vの中間
電位を発生させる為には、ツェナーダイオードの降伏電
圧7V,ダイオードの順方向電圧0.65Vとすると、
ツェナーダイオード1個とダイオード5個との組み合せ
で10.25Vとなり、又温度特性もダイオード4個分
の約−8mV/℃と悪い。
For example, in order to generate an intermediate potential of 10V when viewed from the power supply terminal 2, assuming that the breakdown voltage of the Zener diode is 7V and the forward voltage of the diode is 0.65V,
A combination of one Zener diode and five diodes has a voltage of 10.25 V, and the temperature characteristic is poor at about -8 mV / ° C for four diodes.

【0007】又、演算増幅器5,6の状態によっては、
縦積み接続部の電源は吸い込み・掃き出しの両方の場合
が考えられる為、定電圧発生回路3と抵抗4とには十分
なアイドリング電流が必要となり、消費電力増大につな
がるという欠点も有った。
Further, depending on the states of the operational amplifiers 5 and 6,
Since the power source for the vertically stacked connection portion may be for both suction and sweeping out, a sufficient idling current is required for the constant voltage generation circuit 3 and the resistor 4, which also has the drawback of increasing power consumption.

【0008】例えば、演算増幅器5はパワーダウンモー
ドとなり、演算増幅器6のみがアクティブモードで高電
源側から1mAの吸い込みが有る場合を想定すれば、抵
抗4から1mA供給できる為には、常時1.5mA程度
のアイドリング電流が必要となり、端子1,2間に48
V印加されているとすると、常時72mWの消費電力が
発生する事となり、特に回路数の多い加入者回路におい
ては好ましくない。
For example, assuming that the operational amplifier 5 is in the power-down mode and only the operational amplifier 6 is in the active mode and 1 mA is sucked from the high power source side, in order to be able to supply 1 mA from the resistor 4, it is always 1. An idling current of about 5 mA is required, and 48 between terminals 1 and 2
If V is applied, a power consumption of 72 mW is always generated, which is not preferable especially in a subscriber circuit having a large number of circuits.

【0009】次に、従来の電圧発生回路の別の例におい
ては、前述した従来の一例の欠点にかんがみ、任意の電
位が得られる抵抗7,8とアイドリング電流が一例に比
べて1/10程度少なくて済むバッファトランジスタ
9,10が具備されているが、演算増幅器5,6の状態
によって変化する縦積み接続部の吸い込み・掃き出しに
よって、その電圧が変化するという欠点が有る。
Next, in another example of the conventional voltage generating circuit, in view of the drawbacks of the conventional example described above, the resistors 7 and 8 and the idling current for obtaining an arbitrary potential are about 1/10 of the example. Although the number of buffer transistors 9 and 10 required is small, there is a drawback in that the voltage changes due to the suction / sweeping of the vertically stacked connection portion which changes depending on the states of the operational amplifiers 5 and 6.

【0010】即ち、吸い込み時はトランジスタ9はしゃ
断(OFF)し、トランジスタ10が導通(ON)する
為、抵抗7,8によって決定された電位より0.65V
上昇し、又掃き出し時はトランジスタ9がONし、トラ
ンジスタ10はOFFする為、抵抗7,8によって決定
された電位より0.65V下降する。
That is, during suction, the transistor 9 is cut off (OFF) and the transistor 10 is turned on (ON). Therefore, the potential determined by the resistors 7 and 8 is 0.65V.
The voltage rises, and the transistor 9 is turned on and the transistor 10 is turned off at the time of sweeping, so that the potential drops by 0.65 V from the potential determined by the resistors 7 and 8.

【0011】従って、スイッチングにより計1.3Vの
電圧の変化が発生する事になり、好まくない。さらに、
これが定常的に繰り返されると、演算増幅器の電源雑音
除去比の性能にもよるが、出力に雑音として発生すると
いう欠点も合わせ持っていた。
Accordingly, switching causes a total voltage change of 1.3V, which is not preferable. further,
If this is steadily repeated, it also has a drawback that noise is generated in the output, depending on the performance of the power supply noise rejection ratio of the operational amplifier.

【0012】本発明の目的は、前記諸欠点を解決し、温
度特性を良好にし、消費電力を減少させ、雑音特性も良
好にした電圧発生回路を提供することにある。
An object of the present invention is to provide a voltage generating circuit which solves the above-mentioned drawbacks, improves temperature characteristics, reduces power consumption and noise characteristics.

【0013】[0013]

【課題を解決するための手段】本発明の電圧発生回路の
構成は、第1,第2の電源端子間に第1,第2の増幅器
が縦積み接続され、前記第1,第2の増幅器の共通電源
接続点と定電圧発生回路の出力との間にバッファを介在
させ、前記バッファ内に含まれるトランジスタのベース
には、特性変動を小さくするようにダイオードが接続さ
れていることを特徴とする。
According to the structure of a voltage generating circuit of the present invention, first and second amplifiers are vertically connected between first and second power supply terminals, and the first and second amplifiers are connected. A buffer is interposed between the common power source connection point of the above and the output of the constant voltage generating circuit, and a diode is connected to the base of the transistor included in the buffer so as to reduce the characteristic variation. To do.

【0014】[0014]

【実施例】図1は本発明の一実施例の電圧発生回路を示
す回路図である。
1 is a circuit diagram showing a voltage generating circuit according to an embodiment of the present invention.

【0015】図1において、本実施例は、ダイオード1
1,12,抵抗7,8,17,18,npnトランジス
タ9,pnpトランジスタ10を有し、その他は図3と
同様である。
In FIG. 1, a diode 1 is used in this embodiment.
1, 12, resistors 7, 8, 17, 18, npn transistor 9, pnp transistor 10, and others are the same as in FIG.

【0016】図1において、本発明の一実施例の電圧発
生回路では、電源端子1,2に印加された電圧は定電圧
発生回路3と抵抗4とによって中間電位を発生させ、さ
らには抵抗7,8,ダイオード11,12によって任意
の電圧に分圧し、トランジスタ9,10のベースに供給
している。
In FIG. 1, in the voltage generating circuit according to one embodiment of the present invention, the voltage applied to the power supply terminals 1 and 2 causes an intermediate potential to be generated by the constant voltage generating circuit 3 and the resistor 4, and further the resistor 7 is used. , 8 and diodes 11, 12 divide the voltage to an arbitrary voltage and supply it to the bases of the transistors 9, 10.

【0017】ここで、トランジスタ9,10のベース間
にダイオード11,12が接続されている為、トランジ
スタ9,10は完全にしゃ断(OFF)する事は無い。
Since the diodes 11 and 12 are connected between the bases of the transistors 9 and 10, the transistors 9 and 10 are not completely cut off (OFF).

【0018】即ち、吸い込み・掃き出しによる電圧変動
はほとんど発生しない。例えば、アイドリング電流設定
用の抵抗17,18をそれぞれ50Ωとし、吸い込み・
掃き出しの電流をそれぞれ1mAと想定すれば、0.1
V程度の変動のみとなり、大幅に改善される。
That is, almost no voltage fluctuation occurs due to suction / sweeping. For example, the resistors 17 and 18 for setting the idling current are set to 50Ω, respectively,
Assuming that each sweep current is 1 mA, 0.1
Only a fluctuation of about V, which is a great improvement.

【0019】図2は本発明の他の実施例の電圧発生回路
を示す回路図である。
FIG. 2 is a circuit diagram showing a voltage generating circuit according to another embodiment of the present invention.

【0020】図2において、本実施例は、ダイオード1
1,12,13,14,抵抗17,18,npnトラン
ジスタ9,15,pnpトランジスタ10,16を有
し、その他は図4と同様である。
In FIG. 2, a diode 1 is used in this embodiment.
1, 12, 13, 14, resistances 17, 18, npn transistors 9, 15, and pnp transistors 10, 16 are provided, and the others are the same as in FIG.

【0021】図2において、演算増幅器5,6が例えば
高帯域が必要で有るとすれば、必然的に演算増幅器5,
6の電源電流も増大する。
In FIG. 2, if the operational amplifiers 5 and 6 require a high band, for example, the operational amplifiers 5 and 6 are inevitably used.
The power supply current of 6 also increases.

【0022】即ち、吸い込み・掃き出しの電流も増大す
る為、トランジスタ1個ではベース電流も無視できなく
なり、抵抗7,8等によって発生させた任意の電圧に誤
差が生じてくる事になる。
That is, since the sinking / sweeping current also increases, the base current cannot be ignored with one transistor, and an error will occur in an arbitrary voltage generated by the resistors 7 and 8.

【0023】この対策として、図2のごとく、トランジ
スタ15,16を追加しトランジスタ9,10とダーリ
ントン接続する事で、ベース電流の影響を無視する事が
できる。
As a countermeasure against this, as shown in FIG. 2, by adding transistors 15 and 16 and connecting the transistors 9 and 10 to Darlington, the influence of the base current can be ignored.

【0024】[0024]

【発明の効果】以上説明したように、本発明は、特に一
対の相補型のトランジスタのベース間に、前記トランジ
スタのベースエミッタの順方向と同じ方向に同じ数だけ
ダイオードを接続した事により、任意の電圧が発生で
き、消費電力も少なく、負荷の状態による電圧変動も少
なく、さらに温度特性のキャンセルも可能な中間電位の
電源発生回路が容易に実現できるという効果が有る。
As described above, according to the present invention, in particular, the same number of diodes are connected between the bases of a pair of complementary transistors in the same direction as the forward direction of the base-emitters of the transistors. Is generated, the power consumption is low, the voltage fluctuation due to the load condition is small, and the power supply generation circuit of the intermediate potential capable of canceling the temperature characteristic can be easily realized.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例の電圧発生回路を示す回路図
である。
FIG. 1 is a circuit diagram showing a voltage generating circuit according to an embodiment of the present invention.

【図2】本発明の他の実施例の電圧発生回路を示す回路
図である。
FIG. 2 is a circuit diagram showing a voltage generating circuit according to another embodiment of the present invention.

【図3】従来の一例の電圧発生回路を示す回路図であ
る。
FIG. 3 is a circuit diagram showing a conventional voltage generation circuit.

【図4】従来の他例を示す回路図である。FIG. 4 is a circuit diagram showing another conventional example.

【符号の説明】[Explanation of symbols]

1,2 電源端子 3 定電圧発生回路 4 バイアス用抵抗 5,6 演算増幅器(負荷) 7,8 分圧用抵抗 9,10 バッファ用トランジスタ 11,12,13,14, ダイオード 15,16 ダーリントン用トランジスタ 1, 2 Power supply terminal 3 Constant voltage generation circuit 4 Bias resistor 5,6 Operational amplifier (load) 7,8 Voltage dividing resistor 9,10 Buffer transistor 11, 12, 13, 14, Diode 15,16 Darlington transistor

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 第1,第2の電源端子間に第1,第2の
増幅器が縦積み接続され、前記第1,第2の増幅器の共
通電源接続点と定電圧発生回路の出力との間にバッファ
を介在させ、前記バッファ内に含まれるトランジスタの
ベースには、特性変動を小さくするようにダイオードが
接続されていることを特徴とする電圧発生回路。
1. A first power supply terminal and a second power supply terminal are vertically stacked and connected between a first power supply terminal and a second power supply terminal, and a common power supply connection point of the first and second amplifiers and an output of a constant voltage generation circuit. A voltage generating circuit characterized in that a buffer is interposed therebetween and a diode is connected to a base of a transistor included in the buffer so as to reduce characteristic fluctuation.
【請求項2】 トランジスタがダーリントン接続された
ものである請求項1記載の電圧発生回路。
2. The voltage generating circuit according to claim 1, wherein the transistors are Darlington-connected.
JP3235262A 1991-09-17 1991-09-17 Voltage generation circuit Pending JPH0573163A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3235262A JPH0573163A (en) 1991-09-17 1991-09-17 Voltage generation circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3235262A JPH0573163A (en) 1991-09-17 1991-09-17 Voltage generation circuit

Publications (1)

Publication Number Publication Date
JPH0573163A true JPH0573163A (en) 1993-03-26

Family

ID=16983485

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3235262A Pending JPH0573163A (en) 1991-09-17 1991-09-17 Voltage generation circuit

Country Status (1)

Country Link
JP (1) JPH0573163A (en)

Similar Documents

Publication Publication Date Title
US4079336A (en) Stacked transistor output amplifier
JP2990889B2 (en) Magnetic head drive circuit
US3914704A (en) Feedback amplifier
US4977336A (en) Schmitt-trigger circuit having no discrete resistor
US4369410A (en) Monolithically integrable transistor amplifier having gain control means
US4599578A (en) Protection circuit
EP1181773B1 (en) Overvoltage protection
US4092552A (en) Bipolar monolithic integrated push-pull power stage for digital signals
US3936731A (en) Amplifier with fast recovery after input signal overswing
JP3242422B2 (en) Broadband amplifier
JPH0573163A (en) Voltage generation circuit
US5144169A (en) Operational amplifier circuit
JPH05218799A (en) Impedance multiplier
US4267521A (en) Compound transistor circuitry
US5196809A (en) High gain, low distortion, faster switching transistor
JP2759226B2 (en) Reference voltage generation circuit
JP2600239B2 (en) amplifier
JPS5915124Y2 (en) power amplifier circuit
JPH0517695Y2 (en)
JPS6119548Y2 (en)
JPH07170134A (en) Amplifier circuit
JPH0212049B2 (en)
JP3120580B2 (en) Impedance compensation circuit
JPS58154911A (en) Gain control amplifier
JP2996551B2 (en) Current mirror circuit device