JP3120580B2 - Impedance compensation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an impedance compensating circuit in a transmitting / receiving IC for communication in which a plurality of transmitting circuits or receiving circuits are connected to a common transmission medium to perform communication.

[0002]

2. Description of the Related Art Conventionally, for example, a differential receiving circuit that outputs high or low depending on whether a voltage difference between two input pins is larger or smaller than a certain threshold value is configured as shown in FIG. . In FIG. 3, reference numeral 301 denotes a comparator circuit which compares the voltages of the non-inverting input and the inverting input and outputs the result to the open collector output. Reference numeral 302 denotes a first DC bias application unit, which applies a DC bias determined by the voltage division ratio of the resistance element 308 and the resistance element 309 and the voltage of the DC power supply 313 to the non-inverting input of the comparator circuit unit 301. 3
03 is a first capacitor, one end of which is connected to the input B. Reference numeral 304 denotes a second DC bias application unit, which applies a DC bias determined by the voltage division ratio of the resistance element 310 and the resistance element 311 and the voltage of the DC power supply 313 to the comparator circuit unit 301.
Is applied to the inverting input. A second capacitor 305 has one end connected to the input A. A resistance element 306 has one end connected to the first capacitor 303 and the other end connected to the inverting input of the comparator circuit unit 301. A resistance element 307 has one end connected to the second capacitor 305 and the other end connected to the non-inverting input of the comparator circuit unit 301. 308
Reference numerals 311 to 311 denote resistance elements, which constitute the first DC bias applying unit 2 and the second DC bias applying unit 4. 3
Reference numeral 12 denotes a resistance element that pulls up an open collector output of the comparator circuit unit 301. Reference numeral 313 denotes a DC power supply, which includes a comparator circuit unit 301, a first DC bias application unit 302, and a second DC bias application unit 30.
4 is supplied with power.

Next, the operation of the conventional technique will be described. The receiving circuit thus configured has the following equation: (VA−VB)> Vcc · β / α where α = R5 // R6 / (R2 + R5 // R6) = R3 // R4 / (R1 + R3 // R4) β = R5 LOW is output when / (R5 + R6) -R4 / (R3 + R4), and High is output when (VA-VB) <Vcc · β / α. This is shown in FIG. According to this circuit system, the in-phase input voltage range and the operating input voltage range can be freely set by appropriately selecting α, and the input impedance can be determined as R1 + R2 + R3 // R4 + R5 // R6. This input impedance is set such that a sufficient value can be ensured even when divided by the number of receiving circuits connected in parallel to the common transmission medium. 314 and 3
Reference numeral 15 denotes a diode mounted to protect the input terminal of the IC from a negative surge voltage.

[0004]

If the receiving circuit of FIG. 3 is realized by a bipolar IC, an equivalent circuit of the input stage at the time of power-off is as shown in FIG. In FIG. 4, reference numeral 401 denotes 1 in FIG.
R2, R5, R
6, the resultant resistance value ZA = R2 + R5 // R6. 40
2 is a resistance impedance ZB indicated by 102 in FIG.
1, R3, R4, combined resistance value ZB = R1 + R3 // R4
Becomes Reference numeral 403 denotes a diode indicated by reference numeral 103 in FIG. 3, and forms an NPN transistor with the epitaxial layer. Reference numeral 404 denotes a parasitic PNP transistor composed of a P-type resistor R6, an epitaxial layer, and ground.

In FIG. 4, when a voltage is applied to the input A with respect to the input B, the transistor 403 is turned on, and the collector-emitter voltage VCE becomes about 0.1 V, and the emitter-base voltage VBE of the transistor 404 is about 0.1 V.
When the total voltage becomes 7 V or more, that is, 0.8 V or more, both transistors are turned on, and the impedance between input A and input B becomes low.

[0006]

According to the present invention, an anode is connected to the ground side between two input pins of a receiving circuit and a ground, and the two output pins or the two output pins are connected. Two diodes for connecting the cathodes to the input pins are externally connected.

[0007]

According to the present invention, it is possible to maintain the impedance of the receiving circuit at a high impedance even when the power is cut off by the above-described method.

[0008]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a differential type receiving circuit which outputs high or low depending on whether a voltage difference between two input pins is larger or smaller than a certain threshold value. Therefore, the description is omitted here. In FIG.
Is a resistance impedance between the input A and the ground, 102 is an input impedance between the input B and the ground 103 is a diode for surge protection in which the anode is connected to the ground and the cathode connected to the input connected to the input A, and 104 is the ground. It is a diode for surge protection in which the anode is connected and the cathode is connected to the input connected to input B. Reference numeral 105 denotes a range of a circuit built in one chip as an IC, and other than these are circuit components externally provided outside the IC. Reference numerals 106 and 107 denote diodes for keeping the impedance at the time of power shutdown high.

The operation of the impedance compensating circuit configured as described above will be described with reference to an equivalent circuit shown in FIG. Here, the equivalent circuit before connecting the diodes 106 and 107 has been described in the related art, so that the description is omitted here. When the forward voltage of the diode 107 is set to a value lower than the base-emitter voltage VBE of the NPN transistor 403, the VBE of the NPN transistor 403 is kept below the voltage at which the transistor is turned on, so that the off state is maintained. When the NPN transistor 403 maintains the off state, the base current of the PNP transistor 404 does not flow, so that the PNP transistor 404 also maintains the off state. NPN transistor 403, P
When the input A is viewed from the input B when the NP transistor 404 is off, the impedance becomes a series impedance of the resistance element 401 and the diode 107, which is maintained almost at the resistance value of the resistance element 401 and becomes a high impedance. The diode 106 also functions to maintain a high impedance when viewing the input B from the input A.

As described above, according to this embodiment, it is possible to keep the impedance of the receiving circuit at a high impedance even when the power is cut off.

[0012]

By compensating for the decrease in impedance when power is cut off due to parasitic elements with a simple external diode, there is no need to externally connect a resistor or transistor to maintain the impedance when power is cut off.
The circuit can be reduced to a compact IC on a single chip.

[Brief description of the drawings]

FIG. 1 is a configuration diagram when an impedance compensating circuit according to an embodiment of the present invention is applied to an operation-type receiving circuit IC.

FIG. 2 is an equivalent circuit diagram of an embodiment of the present invention.

FIG. 3 is a configuration diagram of a conventional operation type receiving circuit.

FIG. 4 is an equivalent circuit diagram of a conventional operation type receiving circuit.

[Explanation of symbols]

 101 Resistance impedance between input A and ground 102 Resistance impedance between input B and ground 103 Surge protection diode 104 Surge protection diode 105 IC circuit unit 106 Impedance compensation diode 107 Impedance compensation diode

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04L 25/02 H04B 1/18

Claims (1)

(57) [Claims] 1. A resistance element between two output pins of a differential transmission circuit or two input pins of a differential reception circuit and a ground, and an anode on the ground side, respectively. In a transmitting / receiving IC circuit having a surge protection diode connecting a cathode to an input pin side in parallel, two output pins of the transmitting circuit or two of the receiving circuit are provided.
An anode is connected to the ground side between the two input pins and the ground, and two diodes are connected externally to the two output pins or the two input pins. An impedance compensation circuit for preventing the impedance between the two output terminals or between the two input terminals from becoming low when the power is shut off.