EP0056809B1

EP0056809B1 - Cascode current source

Info

Publication number: EP0056809B1
Application number: EP81902131A
Authority: EP
Inventors: Wilson David Pace
Original assignee: Motorola Inc
Current assignee: Motorola Solutions Inc
Priority date: 1980-08-05
Filing date: 1981-07-13
Publication date: 1985-06-05
Also published as: IT1142954B; JPS57501154A; EP0056809A4; JPH0261804B2; WO1982000550A1; US4345217A; EP0056809A1; IT8148984A0

Description

Field of the Invention

This invention relates to current producing circuits and more- particularly to a cascode current circuit for high voltage, high accuracy applications.

Background of the Prior Art

Current producing circuits such as current mirror circuits find wide applications in integrated circuit uses. A well known current mirror circuit, as shown in Fig. 1, utilized in contemporary monolithic circuits comprises a diode coupled in parallel to the base-emitter path of an output transistor. Typically the diode is fabricated as a transistor with the base connected to the collector as understood with the base-emitter area being perfectly matched to the base-emitter area of the output transistor such that the output current (lout) appearing at the collector of the output transistor is substantially equal to the input current (l_in) supplied to the diode. Generally, using standard monolithic processing techniques, tout can be closely matched to l_in. However, the matching between tout and l_in is seriously degraded with variations in the voltage appearing at the output which are supplied to the output matched transistor. Thus, in some applications requiring very tight matching tolerance, for instance, 1 percent or less, between l_in and lout with variations in the output voltage, the foregoing described current mirror circuit becomes inadequate.
Additionally, there are some applications which require precision NPN current mirrors of the type described above having a 1% matching tolerance specification between the input and output currents and in which the voltage at the output may exceed the collector to emitter breakdown voltage (BV_cEo) of the NPN transistors fabricated with contemporary monolithic processes. For example, some Subscriber Loop interface Circuits (SUCs) that provide conversion between a balanced bidirectional transmission path and a pair of unidirectional transmission paths as known in the art require current mirror circuits having the aforementioned precision requirement which must withstand voltages up to 60 volts. However, most present day integrated circuit process techniques results in a BV_cEo of the NPN transistors equal to approximately 45 volts; which is considerably less than the transistors may be subjected to in the foregoing environment.
Thus, there is a need for a current sourcing circuit suitable for utilization in high voltage and high accuracy applications.

Summary of Invention

Accordingly, it is an object of the present invention to provide a cascode current circuit for providing an output current for high voltage, high accuracy applications.
In accordance with an aspect of the present invention there is provided a current source comprising an input circuit for receiving an input current supplied at an input and for providing an output current at an output which is substantially equal in magnitude to said input current and means coupled between the input circuit and the output to form a cascode circuit for buffering the input circuit from variations in the voltage appearing at the output, the cascode circuit including a pair of transistors connected as a Darlington amplifier with the emitter of the first transistor of the pair of transistors being connected to the input circuit, the base of the first transistor being connected to the emitter of the second transistor and the collectors of the first and second transistors being coupled to the output of the current source and a third transistor of complementary conductivity type to the pair of transistors with the base thereof connected to the base of the second transistor, the collector connected to the emitter of the first transistor, the emitter being connected with the base of the first transistor and the bases of the second and third transistor being connected to a node at which is supplied a reference potential.

Brief Description of the Drawings

FIG. 1 is a schematic diagram of a current mirror circuit generally known in the art;
FIG. 2 is a schematic diagram illustrating a cascode circuit utilizing the current mirror circuit of FIG. 1;
FIG. 3 is a schematic diagram illustrating a Darlington configured cascode circuit in combination with the current mirror circuit of FIG. 1; and
FIG. 4 is a schematic diagram illustrating the preferred embodiment of the present invention.

Detailed Discussion of the Preferred Embodiment

FIG. 1 illustrates current mirror circuit 10 which is well known in the art and is shown as comprising diode 12 connected in parallel to the base-emitter of transistor 14. Terminal 16 is generally coupled to an input load, for instance, a resistor coupled to a voltage potential which provides a current l_in supplied to the inter connection between the anode of diode 12 and the base oftran- sistor 14. As understood, diode 12 may be realized by a transistor having the base connected to the collector thereof such that with the base-emitter areas of the two devices being perfectly matched the output current 1₀ produced at output node 18 is substantially equal to the input current l_in Generally, with present-day monolithic processes the match between the output current at node 18 to the input current at node 16 can be maintained within a 3-5% of one another. However, serious degradation in a match between the two currents occurs if the voltage appearing at output terminal 18 should vary (it being understood that node 18 would be coupled to a source of potential).
Turning to the remaining figures wherein like parts to those in FIG. 1 are referenced by the same reference numerals, FIG. 2 shows a cascode current circuit 20 including an input portion comprising the current mirror circuit described above with respect to FIG. 1 and an output cascode portion comprising single NPN transistor 22. Transistor 22 which has its collector-to-emitter path connected in cascode with the transistor 14 provides a buffering therebetween with the output voltage which would be supplied at node 18 with the base of transistor 22 being coupled to a substantially constant bias potential 24 that provides a potential V_e. Any variations in the voltage appearing at node 18 are not transferred to transistor 14 since the collector voltage thereof is kept constant wherein the output current match with respect to the input current is maintained with variations in the voltage appearing at terminal 18.
Cascode circuits are known per se and reference is made to IEE Journal of Solid Stage Circuits, Vol. SC-4, No. 4, August 1979, pages 734-741.
A problem with the cascode arrangement of FIG. 2 results because of the base current error produced by transistor 22. For example with the beta of transistor 22 equal to 50, the base current comprises 2% of the output current l_o This prevents a very precision current circuit from being established.
Turning to FIG. 3, the cascode current source 20 can be modified to include a cascode output portion comprising a second or driving transistor 26 connected with cascoded transistor 22 to form a Darlington amplifier arrangement. This cascode arrangement maintains the mirror accuracy by buffering the matched transistors 12 and 14 from voltage swings occurring at node 18 in the manner discussed above while introducing less than 0.1 % base current error because of the much higher beta factor of the Darlington arrangement over the single cascoded structure. Hence, the NPN Darlington arrangement of transistors 22 and 26 reduces base current errors that otherwise plague the single NPN cascode arrangement of FIG. 2. The use of a Darlington configuration in the output stage of a current amplifier is known and reference is made to U.S. Patent No. 4,030,042.
A problem with the cascode circuit arrangement of FIGS. 2 and 3 is that using contemporary integrated circuit processing techniques and collector-emitter breakdown voltage, BV_CEO of the NPN devices is approximately 45 volts. However, in some applications it has been found that the voltage appearing at node 18 may be greater than 60 volts and may change from 10 to 60 volts which is beyond the '40-45 volt breakdown capabilities of the NPN transistors.
Turning now to FIG. 4 there is shown cascode current circuit 30 of the preferred embodiment of the invention that is suitable for manufacture in integrated circuit form wherein the matching between current l_in to the current 1₀ is maintained within a 1% tolerance with substantial voltage changes occurring at node 18 and which has all of the advantages of the circuit of FIG. 3 while reducing any reverse current errors that may occur due to transistor 22 being operated above the BV_CEO voltage thereof. As illustrated, cascode current circuit 30 comprises a PNP lateral transistor 28 coupled to the Darlington connected transistors 22 and 26 of the cascode output portion of the circuit. The emitter of transistor 28 is connected to the interconnected base and emitter electrodes of transistors 22 and 26 respectively with the base coupled with the base of transistor 26 to bias potential 24. The collector of PNP transistor 28 is returned to the collector of the matched transistor 14.
In operation, the PNP transistor 28 is rendered conductive as the collector-emitter breakdown voltage of transistor 22 is exceeded and reverse base current begins to flow out of the base thereof to clamp the voltage at the base of transistor 22 even though the voltage appearing at node 18 increases beyond the BV_CEO of the device. The reverse base current error is severely limited since this current is returned through the collector of transistor 28 to matched transistor 14. Hence, the output circuit portion including the Darlington NPN transistors 22 and 26 and PNP transistor 28 maintains a high output impedance at terminal 18 for voltages appearing at the output greater than the BV_CEO characteristics of the NPN devices. Thus the current source of FIG. 4 severely eliminates variations in the output current 1₀ and protects driver transistor 26 when the BV_CEO of the NPN transistors is exceeded.
Tests on cascode current circuits fabricated utilizing the teachings of the present invention indicate less than a 1% change in the output current 1₀ with voltage variations at the output from 10 volts to 80 volts at terminal 18 with typical NPN transistors having a 45 volt BV_ceo characteristic.

Claims

1. A cascode current source comprising an input circuit (12, 14) for receiving an input current (fI_N) supplied to an input (16) and for providing an output current (1₀) at an output (18) which is substantially equal in magnitude to said input current and characterised by means (22, 26, 28) coupled between the input circuit and the output (18) to form a cascode circuit for buffering the input circuit (12, 14) from variations in the voltage appearing at the output (18), the cascode circuit including a pair of transistors (22, 26) connected as a Darlington amplifier with the emitter of the first transistor (22) of the pair of transistors being connected to the input circuit, the base of the first transistor (22) being connected to the emitter of the second transistor (26) and the collectors of the first and second transistors being coupled to the output (18) of the current source and a third transistor (28) of complementary conductivity type to the pair of transistors with the base thereof connected to the base of the second transistor (26), the collector connected to the emitter of the first transistor (22), the emitter being connected with the base of the first transistor (22) and the bases of the second (26) and third (28) transistors being connected to a node at which is supplied a reference potential (V_B).

2. A cascode current mirror, comprising an input current mirror comprising a pair (12, 14) of matched semiconductor devices for providing an output current (1₀) at an output (18) thereof substantially equal to an input current (l_IN) supplied at an input (16) thereof and characterised by a cascode circuit including a first transistor (22) of a first conductivity type having the emitter-collector path coupled in series between the input current mirror and the output (18), a second transistor (26) of the first conductivity type having an emitter connected to the base of the first transistor, a collector connected with the collector of the first transistor to the output (18) and a third transistor (28) of complementary conductivity type having a base connected with the base of the second transistor (26) to a circuit node for receiving a reference potential (Vg), an emitter connected to the base of the first transistor (22) and a collector connected to the emitter of the first transistor (22).

3. A cascode current circuit comprising an input transistor (14) for producing output current (1₀) at the collector thereof in response to an input current (lI_N) being provided to the base thereof, the emitter thereof being coupled to a first reference potential supply terminal, characterised by a cascode.transistor (22) the emitter-collector path of which is coupled between said collector of said input transistor and an output terminal (18), a driver transistor (26) having a base coupled to a node for receiving a second reference potential, an emitter coupled to the base of said cascode transistor (22), and collector coupled to the collector of said cascode transistor (22); a transistor (28) of complementary conductivity type to said cascode transistor (22) and driver transistor (26) and having a base coupled to said base of said driver transistor (26), an emitter coupled to said base of said cascode transistor (22) and a collector coupled to said emitter of said cascode transistor (22).