JPH0573101A - Abnormal output inhibiting circuit - Google Patents

Abstract

PURPOSE:To stabilize the operations of a system by stopping the operations of the system when a CPU runs away, and holding this state. CONSTITUTION:When a CPU 1 executes normal operations, pulse signals in a prescribed cycle are supplied to a pulse cycle decision circuit 2. As the result, since signals at an L level are outputted from an abnormality generation storage circuit 3, an AND circuit 4 is turned to an opened state and control signals are supplied through the AND circuit 4 to a final output circuit 6. When the CPU 1 runs away, however, pulse signals in a certain cycle longer than the prescribed cycle are supplied to the pulse cycle decision circuit 2 or no pulse signal is supplied. As the result, the output of the abnormality generation storage circuit 3 is inverted to an H level and after that, this state is held. Therefore, the AND circuit 4 is turned to a closed state and control signals Y are cut off.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an abnormal output prohibition circuit, and more particularly to an abnormal output prohibition circuit capable of surely inhibiting a control output from the CPU when the CPU of a device using the CPU runs away.

[0002]

2. Description of the Related Art For example, in a power steering control device for a vehicle, the detection output of a steering angular velocity sensor or a torque sensor attached to a steering shaft, the output of a vehicle speed sensor, etc. are input to a CPU, and the power steering is performed from the CPU. The control signal necessary for control is obtained. For example, a drive control signal of a motor that controls the operation of a hydraulic cylinder that drives the wheels to the left and right is obtained.

However, if the CPU runs out of control for some reason and outputs an abnormal control signal, the operation of the steering wheel by the driver is greatly affected. So C
Conventionally, a countermeasure against a PU running out of control has been proposed.

As one of the countermeasures, there is one in which a watchdog timer is externally attached to the CPU. This is the CPU
Periodically output a pulse from the watchdog timer to the watchdog timer to monitor this pulse,
When the pulse stops being input in a predetermined cycle, it is determined that the CPU has run out of control, and a reset signal is output from the watchdog timer to restore the normal operation of the CPU and operate the system normally. It was made to let.

[0005]

However, according to this conventional device, when the runaway of the CPU is continued, the system is repeatedly stopped and restarted, and the operation becomes unstable. . An object of the present invention is to eliminate the above-mentioned problems of the conventional device, and when the CPU runs out of control, stop the system operation and hold it to ensure the stable operation of the system. To provide an abnormal output prohibition circuit.

[0006]

In order to achieve the above object, the present invention takes a pulse train output from a CPU as an input, and the period of the pulse train is a predetermined period or a period longer than this. A pulse cycle determining circuit for determining whether or not a cycle occurs, and an abnormality occurrence storage circuit that inverts the state and holds it when the cycle becomes longer than expected and prohibits the control signal from being supplied to the controlled means. It is characterized in that it is equipped with.

[0007]

According to the present invention, the pulse cycle determining circuit can quickly and accurately determine whether the CPU is normal or abnormal. Then, when it is determined that an abnormality has occurred, the abnormality occurrence storage circuit stores this,
A signal that prohibits the control signal from being supplied to the controlled means is output.

As a result, the control signal will not be supplied to the controlled means even if the CPU temporarily returns to normal for some reason after the CPU goes out of control, and thus the unstable operation of the controlled means. Can be prevented.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to the drawings. FIG. 1 shows a block diagram of an embodiment of the present invention.

In the figure, reference numeral 1 is, for example, a detection output of a steering angular velocity sensor or a torque sensor, an output of a vehicle speed sensor or the like,
Based on this, the CPU outputs a control signal Y required for power steering control. Reference numeral 2 denotes a pulse cycle determination circuit that receives a pulse signal (for example, a clock signal) P having a constant frequency as an input during normal operation output from the CPU 1. It is an abnormality occurrence memory circuit which receives a detection signal output as a trigger signal as a trigger signal, inverts the state, and holds the inverted state.

Reference numeral 4 is an AND circuit, 5 is an external output circuit (for example, a display lamp drive circuit), and 6 is a final output circuit (for example, an actuator drive circuit).

In this embodiment, when the CPU 1 is operating normally, the pulse signal P having a predetermined cycle is supplied to the pulse cycle determination circuit 2. As a result, since the L level signal is output from the abnormality occurrence storage circuit 3, the AND circuit 4 is opened, and the control signal Y is supplied to the final output circuit 6 through the AND circuit 4. Therefore,
The controlled means or system controlled by the CPU 1 operates by receiving a normal control signal.

However, when the CPU 1 runs out of control, the pulse signal P having a cycle longer than a predetermined cycle is supplied to the pulse cycle determination circuit 2 or the pulse signal P is not supplied. Then, the output of the abnormality occurrence storage circuit 3 is inverted to the H level, and this state is maintained thereafter. Therefore, the AND circuit 4 is closed and the control signal Y continues to be cut off. As a result, the abnormal control signal is not supplied to the final output circuit 6, and the abnormal operation of the system can be prevented.

The external output circuit 5 receives the output of the abnormality occurrence storage circuit 3 as an input and drives a display lamp or the like for notifying normality or abnormality of the system.

Next, a specific example of the pulse cycle determination circuit 2 and the abnormality occurrence storage circuit 3 will be described with reference to FIG. In the figure, the same or equivalent parts as in FIG. 1 are designated by the same reference numerals.

The pulse cycle judging circuit 2 is connected as shown in the figure, and includes a NAND circuit 21, a differentiating circuit including a capacitor 22, resistors 23 and 24, a clipper including a diode 25, a resistor 26, and a transistor 27. ,
It is composed of an integrating circuit composed of a resistor 28, a resistor 29 and a capacitor 30.

Further, the abnormality occurrence storage circuit 3 includes a resistor 31,
It is composed of voltage dividing resistors 32 and 33, a comparator 34, resistors 35 and 36, and a protection diode 37. Comparator 3
4 is given a hysteresis characteristic by the resistors 32, 33 and 36.

Next, the operation of this embodiment will be specifically described with reference to the waveform diagrams of FIGS. 2 and 3. When the CPU 1 is operating normally, the pulse signal P having a constant cycle is output from the CPU 1 to the pulse cycle determination circuit 2. This pulse signal is input to the NAND circuit 21 and the waveform thereof is shaped so as to have a form shown in FIG. The signal A is differentiated by the differentiating circuit composed of the capacitor 22, the resistors 23 and 24, and is clipped by the diode 25 to remove the negative signal. Therefore, the waveform of signal B is shown in Fig. 3 (B).
As shown in.

When the signal B is input to the base of the transistor 27, the transistor 27 turns on when the base voltage is equal to or higher than a predetermined value V1, and turns off when the base voltage becomes lower than the predetermined value V1. Therefore, the signal waveform of the emitter of the transistor 27 becomes as shown in FIG. Since the signal C is integrated by the integrating circuit composed of the resistor 29 and the capacitor 30, the waveform of the signal D is as shown in FIG.

The signal D is input to the inverting input terminal (-) of the comparator 34 having the hysteresis characteristic of the abnormality occurrence storage circuit 3. The values of the resistors 32, 33 and 36 connected to the non-inverting input terminal (+) of the comparator 34 can be 36 KΩ, 12 KΩ and 470 KΩ, respectively.

When the CPU 1 is operating normally and the signal A is continuously input to the pulse cycle judging circuit 2, D> E, so the output of the comparator 34 becomes L level. There is.

On the other hand, when some abnormality occurs in the CPU 1 and the period of the pulse signal P supplied from the CPU 1 to the pulse period determination circuit 2 becomes large or the supply of the pulse is stopped, the level of the signal D is changed. Decreases sharply and E> D. Then, the output F of the comparator 34
Is inverted to H level as shown in FIG. When the output of the comparator 34 becomes H level, the voltage of the non-inverting input terminal (+) becomes high due to the hysteresis characteristic. Therefore, for example, from the CPU 1 the signal A
Even if the normal pulse is output again and the level of the signal D returns to the normal level, the relationship of E> D is maintained.

Incidentally, the reset of the abnormality occurrence storage circuit 3 is
This can be done by turning the power off once and then turning it on again.

[0024]

As is apparent from the above description, according to the present invention, when the CPU goes out of control, it is detected that the cycle of the pulse train output from the CPU becomes large or that no pulse is generated. Accordingly, since the control signal from the CPU is not supplied to the controlled means, it is possible to reliably prevent the controlled means from performing an abnormal operation due to the runaway of the CPU.

Further, even if a runaway of the CPU is temporarily canceled or a pulse of a predetermined cycle is generated from the CPU, the stop of the supply of the control signal to the controlled means is maintained, so that the controlled target is controlled. It is possible to eliminate the fear that the operation of the means is stopped and the operation is repeated and the operation becomes unstable.

[Brief description of drawings]

FIG. 1 is a schematic block diagram of an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a specific example of a main part of the block diagram.

FIG. 3 is a waveform diagram for explaining the operation of the circuit of FIG.

[Explanation of symbols]

1 ... CPU, 2 ... Pulse cycle determination circuit, 3 ... Abnormality occurrence storage circuit, 4 ... AND circuit, 5 ... External output circuit, 6 ... Final output circuit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Nobuaki Suzuki Nobuaki Suzuki, 1st floor of Meiji Life Building, 1st floor, Meiji Life Building, 6 Shimizu-koji, Wakabayashi-ku, Sendai City, Miyagi Prefecture (72) Hiromichi Kobayashi Wakabayashi-ku, Sendai City, Miyagi Prefecture 1st floor of Meiji Life Building, 6th Shimizu Koji

Claims (1)

[Claims] 1. An abnormal output inhibiting circuit for inhibiting supply of a control signal output from a runaway CPU to a controlled means, wherein a pulse train output from the CPU is input to the abnormal output inhibit circuit. A pulse cycle determination circuit for determining whether the cycle is a planned cycle or a cycle longer than this, and when the cycle becomes larger than the planned cycle, the state is inverted and held, and the control signal is An abnormality output prohibition circuit, comprising: an abnormality occurrence storage circuit that prohibits supply to controlled means.