JPH0573060A - Automatic rhythm playing device - Google Patents

Abstract

PURPOSE:To provide the automatic rhythm playing device which selects plural piece of rhythm information differing in data length and plays by restarting a read from the head address of a storage area after the final address of the storage area is reached. CONSTITUTION:A player selects a desired kind of rhythm (e.g. samba) by operating one of rhythm selection switches 34 of a rhythm selecting circuit 33. A CPU 51 after loading the number of skips of rhythm of samba in a skip register R2 reads the head address of the rhythm of samba set by a matrix circuit 332 included in the rhythm selecting circuit 33 and supplies rhythm information in the address of a ROM 31 specified by an address register R1 to sound source oscillators 171-177. This operation is repeated to advance the read address of the ROM 31 when the skip register R1 indicates 0. Consequently, the playing device can play even when the size of the storage area is different with the kind of rhythm.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an automatic rhythm player, and more particularly to an automatic rhythm player capable of selectively playing a plurality of rhythm types.

[0002]

2. Description of the Related Art Conventionally, an automatic rhythm player is disclosed in JP-A-47-2.
As disclosed in Japanese Patent No. 7519, the memory stores information on a plurality of rhythm types, and means for selectively setting the rhythm type is provided so that the performer can select a desired rhythm type. It is known to read out designated rhythm information from the memory when a start is instructed.

[0003]

In these conventional automatic rhythm players, the address generating counter is fixed, and it is necessary to make the number of steps common to each rhythm. There are many types of rhythm, and the length of rhythm information varies depending on the type. There are also those that repeat in units of one bar, and those that repeat in two measures and four measures.

The present invention has been made in view of this point.
It is an automatic rhythm player that can select and play a plurality of rhythm information having different data lengths.

[0006]

In order to achieve the above-mentioned object, an automatic rhythm player according to the present invention stores different types of rhythm information in a plurality of storage areas and sequentially reads out the rhythm information. In an automatic rhythm player that plays various rhythms, the rhythm type selecting means for selecting the type of rhythm information and the final address of the storage area storing the rhythm information selected by the rhythm type selecting means And a deciding means for deciding that the rhythm information is repeatedly read from the rhythm information storage area designated by the rhythm type selecting means.

[0007]

As described above, in the present invention, the determination means for determining the final address of the storage area is provided, and after the read address reaches the final address, the reading is restarted from the top address of the storage area. ..

[0008]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of an embodiment of the present invention, and is a block diagram in the case of reading rhythm information prewritten in a memory by software. In the configuration, this embodiment includes an arithmetic processing unit (CPU) 51 for performing arithmetic processing based on a predetermined program, and a program storage memory (for example, ROM) 52 in which an operation program of the CPU 51 is stored in advance. A microprocessor 50 and a random access memory (RAM) 53 including a plurality of writable and readable storage areas are provided.
The plurality of storage areas of the RAM 53 are used as at least the address register R1, the skip register R2, and the step register R3. Further, a rhythm storage memory (ROM) 31 and a rhythm selection circuit 33, a start / stop command switch (S switch) 141, a T-type flip-flop (hereinafter T / FF) 142, and a variable resistor 153.
, Clock oscillator 151, sound source oscillators 171-177,
Volume control resistor 181, amplifier 182, speaker 183
It consists of and.

The rhythm selection circuit 33 has a matrix circuit 331 as a first setting unit for preset storing the number of skips for each rhythm type, and a second preset address for the ROM 31 for each rhythm type. A matrix circuit 332 as a setting unit of the above, and a rhythm type selection switch 34 for selecting a desired rhythm. For example, as the type of rhythm, the samba rhythm is written from ROM 31 to addresses 0 to 15, the slow rock rhythm is written from addresses 16 to 39, and other rhythms are written after address 40. If it is rare, the samba selection switch 341 is connected to the row line l1 of the matrix circuits 331 and 332, the slow lock selection switch 342 is connected to the row line l2, and other switches 343 for selecting various rhythms. 34n are connected to the corresponding row lines 13 to ln. The matrix circuit 332 has a row line l1 and a column line r.
The first address (0th address) of the samba rhythm is set and stored by not connecting any of 1 to r7 with a diode, and the beginning of the slow rock rhythm by connecting the row line 12 and the column line r5 with a diode. Address (No. 16
Address) and connecting the row line l3 and the column lines r4 and r6 with diodes respectively, leading address of other rhythms following slow rock (address 40)
The setting switches are stored in the memory, and in the same way as below, select switches 344-34.
Set and store the start address corresponding to the n rhythm. Also,
The matrix circuit 331 includes a row line l1 and a column line r8,
r9 is connected by a diode to set the skip number 3 of samba rhythm, and the row line 12 and the column line r9 are connected by diode to skip number 2 of slow rock rhythm.
Set and store.

FIG. 2 is a flow chart for explaining the operation of FIG. A rhythm storage memory (ROM) 31 stores the shortest note of the rhythm pattern at one address. For example, in the case of a samba rhythm as shown in FIG. 3, as shown in Table 1, if the rhythm of an eighth note is stored at one address and the leading address is the 0th address,
It is stored in the storage area of 16 addresses up to 15. In the case of slow rock rhythm as shown in Fig. 4, as shown in Table 2, triplet notes are stored at one address, the first address is the 16th address, and the 24th addresses up to the 39th address. Stored in the memory area.

[Table 1]

[Table 2]

Next, the operation when the present invention is achieved by software will be described with reference to FIGS. 1 and 2. In the initial state, the CPU 51 determines whether or not the output of the T / FF 142 is the “H” signal, thereby determining whether or not the S switch 141 is pressed and the start command is issued.
If no start command is issued, the process stands by as it is, and if a start command is issued, the process proceeds to the next step. S switch 14
When 1 is pressed, the T / FF 142 derives the “H” signal and supplies it to the CPU 51, and also the clock oscillator 151.
A clock generation command signal is given to.

Next, the performer operates one of the rhythm type selection switches 34 of the rhythm selection circuit 33 to select a desired type of rhythm (for example, samba). Depending on the CP
U51 is a matrix circuit included in the rhythm selection circuit 33.
Number of samba rhythm skips preset in 331
(3) is saved in a save register (not shown) included in the RAM 53 and loaded into the skip register R2, and then the matrix circuit 33 included in the rhythm selection circuit 33.
The first address (0th address) of the samba rhythm set in 2 is successively read out and loaded into the address register R1, and the step number is loaded into the step register R3. This number of steps is stored in ROM31 as the samba rhythm.
It corresponds to the number of addresses (16) stored in, and is calculated, for example, by dividing the number of skips (3) from 48 (48/3 = 16).

Then, the CPU 51 uses the address register R1.
The rhythm information of the address (that is, the first address) of the ROM 31 designated by 1 is successively output in bit parallel and the rhythm information output is given to the corresponding sound source oscillators 171 to 177. As a result, a predetermined tone for each type of musical instrument is generated from the sound source oscillator corresponding to the bit storing the logic "1" at address 0 of the ROM 31, and the volume control variable resistor 181 and the amplifier 182 are set. It is given to the speaker 183 via the speaker and generated.

Subsequently, the CPU 51 determines whether the output of the T.FF 142 is an "H" signal, and if the output of the T.FF 142 is an "H" signal, one reference clock input is given from the clock oscillator 151. When the reference clock is given, the number of skips in the skip register R2 is subtracted by a numerical value 1 and updated and loaded, and it is determined whether the number of skips is 0 or not. As a result, the above operation is repeated until the reference clock signal of the skip number preset in the skip register R2 is given from the clock oscillator 151, and when the content of the skip register R2 becomes 0, the number of addresses loaded in the address register R1. Is added with a numerical value of 1 and is updated and loaded, thereby advancing the address of the ROM 31 to be continued. Then CP
U51 subtracts the numerical value 1 from the number of steps (16 in the case of samba rhythm) stored in the step register R3, and the subtracted value is updated and loaded in the step register R3. Then, the CPU 51 reloads the skip number saved in the save register into the skip register R2, and then determines whether or not the number of steps loaded in the step register R3 is zero. If the number of steps is not 0, the data of the address (1st address) of the ROM 31 designated by the address register is output again, the rhythm information is output again, and the above operation is repeated until the number of steps becomes 0 in the same manner. .. Then, by the time the number of steps becomes 0, the rhythm of the samba for two bars shown in FIG. 3 stored in the ROM 31 is successively generated.

By the way, when it is determined that the number of steps stored in the step register R3 has become 0 in the state of determining whether or not the number of steps is 0, the matrix circuit 332 returns to the address register R1 again. Load the beginning address of the samba rhythm that has been set,
Set the number of steps (16) in the step register R3,
After that, the same operation is repeated.

Then, in order to stop the generation of the selected rhythm, the S switch 141 is pressed again, and the TF
Since the output of F142 is inverted to a low level (hereinafter "L") signal, the CPU 51 successively generates the rhythm information of the address of the ROM 31 designated immediately before, and then returns to the initial state.

When the rhythm selection circuit 33 selects to generate the slow lock rhythm as shown in FIG. 4, the skip register R2 has a skip count of 2
Is loaded and the address register R1 stores the slow rock rhythm information at the head address (that is, the 16th address).
Address), the number of steps 24 is loaded into the step register R3, and the same operation as described above is performed.

[0018]

As described above, according to the present invention, the determination means for determining the final address of the storage area is provided, and after the read address reaches the final address, the reading is restarted from the top address of the storage area. Therefore, even if the size of the storage area differs depending on the rhythm type, it is possible to play.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a flow chart for explaining the operation of FIG.

FIG. 3 is a samba rhythm score.

FIG. 4 is a rhythm score of slow rock.

[Explanation of symbols]

 50 Microprocessor 51 CPU 31 Rhythm memory 141 Start-stop switch 142 T-type flip-flop 153 Tempo adjustment variable resistor 182 Amplifier 183 Speaker

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[Procedure amendment]

[Submission date] June 12, 1991

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] Full text

[Correction method] Change

[Correction content]

[Document name] Statement

Title of invention Automatic rhythm player

[Claims]

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an automatic rhythm player, and more particularly to an automatic rhythm player which can selectively play a plurality of types of rhythms, that is, rhythm information.

[0002]

2. Description of the Related Art Conventionally, as an automatic rhythm player of this kind, one disclosed in Japanese Patent Laid-Open No. 47-27519 as described below is known. From the rhythm information of a plurality of types of rhythms that is composed of a series of data and stored in the memory, the rhythm desired by the performer, in other words, the rhythm information to be read is selected and designated by the selection designating means such as a selection switch. To do. A series of data of the rhythm information to be selected and designated to be read is sequentially read from the time of selection and designation by the selection and designation means.

[0003]

However, in the above-mentioned one, the rhythm information to be read is changed because a series of data is read from the time when the selection designating means selects and specifies the rhythm information to be read. In this case, it is necessary to measure the timing of selection and designation by the selection and designation means, which poses a problem of burdening the player with the performance.

In order to solve such a problem, the present invention allows a user to freely select and designate rhythm information from a plurality of types of rhythm information when changing the rhythm information to be read. An object of the present invention is to provide an automatic rhythm player that can reduce the performance burden on a person.

[0005]

In order to achieve the above-mentioned object, an automatic rhythm player according to the present invention comprises: (a) storage means for storing a plurality of types of rhythm information composed of a series of data, (b) selection designating means for selectively designating the rhythm information to be read out from a plurality of types of rhythm information stored in this storage means, (c) read out in the series of data sequentially read out from the storage means Detecting means for detecting that the data to be read is data at the end of the bar of the rhythm information regarding the series of data, and (d) by this detecting means, the data to be read is the data at the end of the bar of rhythm information regarding the series of data. When it is detected that a series of data of the rhythm information to be read newly selected and specified by the selection specifying means is read sequentially from the head data. It is to have a read-out means.

[0006]

When changing the rhythm information to be read, when the rhythm information to be read is newly selected and designated, the data read out in the series of data which is being sequentially read at present is the rhythm relating to that series of data. When it is detected that the data is at the end of the bar of information, a series of data of newly selected and designated rhythm information to be read is read from the head data.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a specific embodiment of the automatic rhythm player according to the present invention will be described with reference to the drawings. In FIG. 1, which shows a block diagram in the case of reading rhythm information written in the memory in advance by software, in the present embodiment, arithmetic processing for arithmetic processing based on a predetermined program is performed. Unit (CPU) 51 and a microprocessor 50 including a program storage memory (for example, ROM) 52 in which an operation program of the arithmetic processing unit (CPU) 51 is stored in advance, and a random number including a plurality of writable and readable storage areas Access memory (RAM) 53
And are provided. This random access memory (R
AM) 53 has a plurality of storage areas, at least an address register R1, a skip register R2, and a step register R.
It is used as 3rd grade. Further, a rhythm storage memory (ROM) 31, a rhythm selection circuit 33, a start / stop command switch (S switch) 141, a T-type flip-flop (T / FF) 142, a clock oscillator 151,
A variable resistor 153, sound source oscillators 171-177, a volume control resistor 181, an amplifier 182, and a speaker 183 are provided.

The rhythm selection circuit 33 has a matrix circuit 331 as a first setting section for preset storing the number of skips for each rhythm type, and a leading address of a rhythm storage memory (ROM) 31 for each rhythm type in advance. 2nd setting stored
It includes a matrix circuit 332 as a setting unit for the, and a rhythm type selection switch 34 for selecting a desired rhythm.
For example, as the type of rhythm, the samba rhythm is written in the rhythm storage memory (ROM) 31 from addresses 0 to 15, and the slow rock rhythm is written from addresses 16 to 39. If other rhythms are written after address 40, the samba selection switch 341, which is one of the rhythm type selection switches 34, is the matrix circuit 33.
1 and the row line 11 of the matrix circuit 332, similarly the slow lock selection switch 342, which is one of the rhythm type selection switches 34, is connected to the row line 12, and the other rhythm type selection switches 34. Selection line 343-34n for the corresponding row line l3
~ Ln. Then, the matrix circuit 332 is
By connecting neither the row line l1 nor the column lines r1 to r7 with a diode, the head address (0th address) of the samba rhythm is set and stored, and the row line l2 and the column line r5 are connected with a diode. Set the start address (address 16) of the slow rock rhythm, and set the line l
3 and the column lines r4 and r6 are respectively connected by diodes to set and store the leading address (address 40) of another kind of rhythm following slow lock, and similarly, the rhythm of each selection switch 344-34n. The head address corresponding to is set and stored. Further, the matrix circuit 331 sets the skip number 3 of the samba rhythm by connecting the row line l1 and the column lines r8 and r9 with a diode, and connects the row line l2 and the column line r9 with a diode to slow lock. The rhythm skip number of 2 is set and stored.

By the way, a rhythm memory (ROM)
The shortest note, which is one piece of data of the rhythm pattern, is stored in 31 at one address. For example, in FIG.
If the rhythm of the samba is as shown in, the rhythm of the eighth note is stored in one address as shown in Table 1, and if the first address is the 0th address, the 16th up to the 15th address is recorded. The rhythm information of the samba composed of a series of data is stored in the address storage area for each data in the address order. In the case of a slow rock rhythm as shown in FIG. 4, as shown in Table 2, one address similarly stores a triplet note, which is one piece of data, and the leading address is the 16th address. , The slow clock rhythm information composed of a series of data is stored in the storage area of 24 addresses up to the 39th address in order of the data.

[Table 1]

[Table 2]

Next, the operation of the operation program according to this embodiment will be described with reference to the flow chart shown in FIG. In the initial state, the arithmetic processing unit (CPU) 51 has a T-type flip-flop (TFF) 14
By determining whether the output of 2 is the "H" signal, the start / stop command switch (S switch) 14
It is determined whether 1 has been pressed and a start command has been issued (step S1). If no start command has been issued, the process waits as it is, and if a start command has been issued, the process proceeds to the next step S2. If the start / stop command switch (S switch) 141 is pressed to give a start command,
The flip-flop (T · FF) 142 derives an “H” signal and supplies the “H” signal to the arithmetic processing unit (CPU) 51, and also supplies a clock generation command signal to the clock oscillator 151.

Next, the performer operates one of the rhythm type selection switches 34 of the rhythm selection circuit 33 to select a desired type of rhythm (for example, samba) (step S).
2). In response to this selection, the arithmetic processing unit (CPU) 51 causes the matrix circuit 331 included in the rhythm selection circuit 33 to preset the samba rhythm skip count 3
Is saved in a save register (not shown) included in the random access memory (RAM) 53 (step S3), and after being loaded in the skip register R2 (step S4), it is included in the rhythm selection circuit 33. The leading address (0th address) of the samba rhythm set in the matrix circuit 332 is continuously loaded into the address register R1 (step S5), and the number of steps is loaded into the step register R3 (step S).
6). This number of steps corresponds to the number of addresses 16 stored in the rhythm storage memory (ROM) 31 as the samba rhythm, and for example, the number of skips 3 is divided from 48 (48/3 = 1).
6) Calculated by

Subsequently, the arithmetic processing unit (CPU) 51 is provided with a rhythm memory (RO) designated by the address register R1.
M) Rhythm data at address 31 (that is, the head address) is successively output in bit parallel (step S7), and rhythm data output is given to the corresponding sound source oscillators 171 to 177 (step S).
8). As a result, the rhythm storage memory (ROM) 31
The tone generator oscillators 171 to 177 corresponding to the bit storing the logic "1" at the address 0 generate a predetermined musical tone for each type of musical instrument, and transmit it through the volume control variable resistor 181 and the amplifier 182. Is given to the speaker 183 and generated.

Further, the arithmetic processing unit (CPU) 51 determines whether the output of the T-type flip-flop (TFF) 142 is an "H" signal (step S9), and the T-type flip-flop (T If the output of the (FF) 142 is the "H" signal, the system waits until one reference clock input is given from the clock oscillator 151 (step S10), and when the reference clock is given, the skip number of the skip register R2 is a numerical value 1. Subtract and load update (step S11),
Next, it is determined whether or not the skip number is 0, and the process is repeated until it becomes 0 (step S12). As a result, the above-described operation is repeated until the reference clock signal of the skip number set in advance in the skip register R2 is given from the clock oscillator 151, and when the content of the skip register R2 becomes 0, the number of addresses loaded in the address register R1. Is added with a numerical value of 1 and is updated and loaded, whereby the address to be continued in the rhythm memory (ROM) 31 is advanced (step S13). Subsequently, the arithmetic processing unit (CPU) 51
Subtracts the numerical value 1 from the number of steps stored in the step register R3 (16 in the case of samba rhythm), and the subtracted value is updated and loaded into the step register R3 (step S14). Then, the arithmetic processing unit (CPU) 51
After reloading the skip count saved in the save register into the skip register R2 (step S1
5) It is determined whether the number of steps loaded in the step register R3 is 0 (step S16). If the number of steps is not 0, the address of the rhythm storage memory (ROM) 31 designated by the address register again (first
The data of the address) is continuously output and the rhythm data is output again, and the above-described operation is repeated in the same manner until the number of steps becomes 0. By the time the number of steps reaches 0, the rhythm of the two-bar samba shown in FIG. 3 stored in the rhythm storage memory (ROM) 31 is successively generated.

By the way, when it is determined that the number of steps stored in the step register R3 has become 0 in the determination state of whether or not the number of steps is 0, the matrix circuit is sent to the address register R1 again.
The head address of the samba rhythm set in 332 is loaded, the step number 16 is set in the step register R3, and the same operation is repeated thereafter.

Then, in order to stop the generation of the selected rhythm, when the start / stop command switch (S switch) 141 is pressed again, the output of the T-type flip-flop (T · FF) 142 becomes an “L” signal. In order to invert, the arithmetic processing unit (CPU) 51 reads out and generates the rhythm data of the address of the rhythm storage memory (ROM) 31 whose address has been designated immediately before, and then returns to the initial state.

If the rhythm selection circuit 33 selects to generate the slow-lock rhythm as shown in FIG. 4, the skip register R2 is loaded with the number of skips 2, and the address register R1. Is loaded with the leading address (that is, the 16th address) in which slow rock rhythm information is stored, and the step number R is loaded with the step number 24, and the same operation as described above is performed.

[0017]

Therefore, when changing the rhythm information to be read, the performer selects and specifies new rhythm information to be read without measuring the timing of selection specification, so that the rhythm information is sequentially read at present. At the end of the bar in the series of data, a series of data of new rhythm information is read out. Therefore, when changing the rhythm information to be read, it is possible to freely select and specify the rhythm information from a plurality of types of rhythm information, while reducing the performance burden on the performer.

[Brief description of drawings]

FIG. 1 is a block circuit diagram of a specific embodiment of an automatic rhythm player according to the present invention.

FIG. 2 is a flowchart of the operation program described in FIG.

FIG. 3 is a rhythm chart of samba.

FIG. 4 is a rhythm music chart of slow rock.

[Description of symbols] 31 Rhythm storage memory 33 Rhythm selection circuit 34 Rhythm type selection switch 50 Microprocessor 51 Arithmetic processing unit 52 Program storage memory 53 Random access memory 141 Start / stop command switch 142 T-type flip-flop 151 Clock oscillator 153 Variable resistor 171-177 Sound source oscillator 181 Sound source adjustment resistor 182 Amplifier 183 Speaker 331, 332 Matrix circuit

Claims (2)

[Claims] 1. An automatic rhythm player for playing various rhythms by storing different types of rhythm information for each of a plurality of storage areas and sequentially reading the rhythm information for selecting the type of rhythm information. Rhythm type selection means, and determination means for determining the final address of the storage area storing the rhythm information selected by the rhythm type selection means, and storing the rhythm information specified by the rhythm type selection means. An automatic rhythm player characterized in that rhythm information is repeatedly read from a region. 2. The automatic rhythm according to claim 1, wherein the judging means judges whether or not the step number is 0 by subtracting 1 from the step number every time the address advances. Musical instrument.