JPH0572554A - Liquid crystal display panel - Google Patents

Abstract

PURPOSE:To mount the liquid crystal display panel which has a picture element electrode divided into two display electrodes to compensate a level shift in voltage as to an active matrix type liquid crystal display panel where thin film transistors(TFT) corresponding to respective picture elements are arranged in matrix. CONSTITUTION:Each picture element electrode P consists of a 1st display electrode P11 connected to the source electrode of a 1st thin film transistor(TFT) T1 and a 2nd display electrode P21 connected to the source electrode of a 2nd TFT T2. The drain electrode of the 1st TFT T1 is connected to 1st drain bus lines DBD, DBD2... applied with a data voltage, 2nd drain bus lines DBE1, DBE2... are formed in parallel to gate bus lines GB1, GB2..., and a ground potential is applied from a position parallel to the gate bus lines GB1, GB2....

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display panel,
In particular, it relates to an active matrix type liquid crystal display panel in which thin film transistors (TFTs) corresponding to respective pixels are arranged in a matrix. Since the active matrix type liquid crystal display device is as thin as the simple matrix type liquid crystal display device, it is widely used as various display devices for laptop personal computers, word processors, portable televisions and the like. That is, since the active matrix type liquid crystal display device drives each pixel independently by the thin film transistor provided corresponding to the pixel, even if the number of lines is increased as the display capacity is increased, the simple matrix type liquid crystal display device is used. Unlike a display device, there is no problem of a reduction in contrast and a reduction in viewing angle due to a reduction in drive duty, and color display with the same quality as that of a cathode ray tube (CRT) is possible.
The use as a flat display device is expanding. In recent years, further improvement in display quality has been demanded for such active matrix liquid crystal display devices.

[0002]

2. Description of the Related Art FIG. 6 is an equivalent circuit diagram of a conventional liquid crystal display panel and is an equivalent circuit diagram of one pixel controlled by a thin film transistor (TFT). FIG. 7 is a drive voltage waveform diagram for driving a conventional liquid crystal display panel. In FIG. 6, reference numeral T is a thin film transistor, P
Reference numeral ₁ is a pixel electrode connected to the source of the thin film transistor T, and P ₀ is a solid common electrode provided to face the plurality of pixel electrodes P ₁ with a liquid crystal layer interposed therebetween.

As shown in FIG. 6, in the conventional liquid crystal display panel, when the thin film transistor T is turned off,
It is known that at the time of turning on, the charge accumulated in the capacitance C _GS of the channel portion of the transistor T flows into the capacitance C _LC side of the liquid crystal, and the level shift ΔV of the write voltage occurs as shown in FIG. Since the capacitance C _LC of the liquid crystal differs greatly depending on its dielectric anisotropy when the thin film transistor T is turned on and when it is turned off, only by adjusting the voltage V _C on the common electrode P ₀ side, this superimposed DC voltage is obtained. It was difficult to compensate the component ΔV. As a result, the liquid crystal is decomposed and ions are accumulated at the interface between the liquid crystal and the electrode, which may cause a problem such as burn-in of the display.

Conventionally, in order to mitigate or prevent such a phenomenon as burn-in, a method of adding a storage capacitor C _S shown by a broken line in FIG. 6 has been adopted. The storage capacitor C _S is provided in parallel to the pixel (the capacity of the liquid crystal C _LC), adapted to have several times the capacitance of the capacitor of the pixel (the capacity of the liquid crystal C _LC). FIG. 8 is a diagram schematically showing the structure of a conventional thin film transistor having a storage capacitor. In the figure,
Reference numerals 11 and 14 denote glass electrodes provided to face each other, 12 (12 ₁ , 12 ₂ ) denotes a silicon nitride (SiN) film, and 13 denotes a liquid crystal layer.

As shown in FIGS. 6 and 8, a transparent electrode (ITO) P ₂ for forming a storage capacitor is formed on an insulating glass substrate 11, and the transparent electrode P ₂ and
The pixel P ₁ facing each other through the SiN film 12 constitutes a storage capacitor C _S. The liquid crystal capacitance C _LC is composed of the pixel electrode P ₁ and the common electrode P ₀ facing each other with the liquid crystal layer 13 interposed therebetween.

According to the method of providing the storage capacitor C _S in parallel with the pixel (C _LC ), the charge storage capacitor is added to the thin film transistor T, and the image quality can be improved. However, in the manufacturing process, in the structure as shown in FIG. 8, as compared with the process in which the charge storage capacitor is not added, the process of providing the lower transparent electrode (P ₂ ) and the insulating film for charge storage (12 _It is necessary to perform two extra steps of providing ₁ ), which complicates the manufacturing process and reduces the manufacturing yield.

[0007]

SUMMARY OF THE INVENTION To solve the above problems
Therefore, the method shown in FIG. 9 has been conventionally proposed (
(See Kaihei 2-242228). Here, FIG. 9 is a conventional invention.
2 shows an equivalent circuit of the liquid crystal display panel according to the above. In Figure 9
As shown, the thin film transistor matrix substrate (Figure
(Corresponding to the glass substrate 11 in 8))
Elementary electrode P is two display electrodes P₁₁And P _{twenty one}Consists of
And one display electrode P₁₁Contacts the gate bus line GB
One thin film transistor T connected₁Source S₁Contact
And the other display electrode P _{twenty one}Is the gate bus line
The other thin film transistor T connected to GB₂Source of
S ₂It is connected to the. Here, the two display electrodes P₁₁Oh
And P_{twenty one}A counter substrate (Fig.
Transparent electrode P on the glass substrate 14 in FIG. 8) ₀(P
_Ten, P₂₀) Is electrically separated for each pixel.
(Indicated by a broken line in FIG. 10). Also, one thin film
Transistor T₁Drain D₁Is the data voltage
Drain bus line (data side) connected to DBD
And the other thin film transistor T₂Drain D
₂Is the drain bus line DBE held at ground potential
It is connected to the.

FIG. 10 is a layout pattern diagram of a liquid crystal display panel as a related technique to which the invention shown in FIG. 9 is applied. As shown in FIG. 10, a layout pattern of a liquid crystal display panel as a related technique to which the invention of FIG. 9 is applied is that a plurality of drain bus lines DBD ₁ , DBD ₂ , ... The drain bus lines DBE ₀₁ , DBE ₀₂ , ... On the data side are alternately arranged, and the drain bus lines DBD ₁ , DBD ₂ , ... And DBE ₀₁ , DB on the data side and the ground side are alternately arranged.
Multiple gate bus lines that are orthogonal to E ₀₂ , ...
GB ₁ , GB ₂ , ... are arranged.

By the way, when the pixels are arranged in an in-line type, the three primary colors are usually mixed.
The pixel array has a length ratio of 3: 1 in the vertical direction (drain bus side in the case of a thin film transistor matrix) and in the horizontal direction (gate bus side in the case of a thin film transistor matrix). Specifically, each pixel electrode P (P ₁₁ , P ₂₁ ) is, for example, 100 μm
The size is × 300 μm, and the horizontal direction is 1
The pitch is about 00 μm.

Further, in the liquid crystal display panel, each wiring (drain bus lines DBD ₁ , DBD ₂ ,
…; DBE ₀₁ , DBE ₀₂ , ... and gate bus lines GB ₁ , GB ₂ ,
It is necessary to provide a bonding pad for each of these bonding pads, and this bonding pad needs to have a gap (pitch) between adjacent bonding pads of about 80 μm. Therefore, in the layout pattern of the liquid crystal display panel shown in FIG. 10, it is difficult to mount the drive circuit with the current technology.

In view of the problems of the above-described conventional liquid crystal display panel, the present invention compensates the level shift of the writing voltage caused by the capacitance of the channel portion of the thin film transistor by dividing the pixel electrode into two display electrodes. The purpose is to enable mounting of such a liquid crystal display panel.

[0012]

According to the present invention, a thin film transistor
Langista T₁, T₂, The thin film transistor T₁, T₂ To the source of
The pixel electrode P to be connected and the gate electrode to connect the gate electrodes to each other.
Tobas Line GB₁, GB₂,…, And, drain electrode comrades
Drain bus line DBD to connect₁, DBD₂,…; DBE₁, DBE₂,
Insulating thin film transistor matrix substrate with ...
A liquid crystal layer between the plate and the thin film transistor matrix substrate.
And a transparent counter electrode P disposed opposite to each other.₀: P_Ten, P₂₀
In a liquid crystal display panel having a counter substrate on which is formed
Each pixel on the thin film transistor matrix substrate.
Pole P is the same gate bus line GB₁, GB₂Connected to, ...
Two thin film transistors T₁, T₂First thin film tiger
Register T₁First display electrode P connected to the source electrode of
₁₁And and the second thin film transistor T₂On the source electrode of
Second display electrode P connected_{twenty one}Composed of the above
1 thin film transistor T₁The drain electrode has a data voltage
Applied first drain bus line DBD₁, DBD₂Contact with, ...
And the second thin film transistor T₂Drain electrode
Is the second drain bus line DB that is held at ground potential
E₁, DBE₂, And connected to the first display electrode P₁₁And the
Second display electrode P_{twenty one}A counter substrate facing the other through a liquid crystal layer
Upper counter electrode P₀: P_Ten, P₂₀ Is an electrical signal for each pixel electrode.
A liquid crystal display panel formed separately into
2 drain bus lines DBE₁, DBE ₂, ... are the gate bars
Sline GB₁, GB₂It is formed so that it is parallel to
2 drain bus lines DBE₁, DBE₂, ... against earth
Place the gate bus line GB ₁, GB₂From a position parallel to
A liquid crystal display panel characterized by being applied
Provided.

[0013]

According to the liquid crystal display panel of the present invention, the second drain bus lines DBE ₁ , DBE ₂ , ... Are the gate bus lines GB ₁ ,
GB ₂ , ... are formed in parallel with each other, and a ground potential is applied to the second drain bus lines DBE ₁ , DBE ₂ , ... from a position parallel to the gate bus lines GB ₁ , GB ₂ ,. It is supposed to do.

That is, on the long side of the pixel electrode P,
Second drain bus line DBE₁, DBE ₂Earth against
An electric potential is applied. This allows the thin film
Writing caused by the capacitance of the channel part of the transistor
The level shift of the built-in voltage is applied to the two display electrodes from the pixel electrode.
The liquid crystal display panel that was divided and compensated for
The technology can also be implemented.

[0015]

Embodiments of the liquid crystal display panel according to the present invention will be described below with reference to the drawings. FIG. 1 is a layout pattern diagram showing an embodiment of a liquid crystal display panel according to the present invention. The layout pattern shown in FIG. 1 is similar to the layout pattern shown in FIG.
No. 242228) is applied.

As is clear from the comparison between FIG. 1 and FIG. 10, in the layout pattern of the liquid crystal display panel of the present embodiment, a plurality of drain bus lines DBD ₁ , DBD ₂ , ...
The drain bus lines DBE ₁ , DBE ₂ , ... On the ground side are arranged so as to be orthogonal to. Then, all the ground side drain bus lines are commonly connected, and the ground potential is applied from the ground side drain bus lines DBE ₁ , DBE ₂ , ... Located between the gate bus lines GB ₁ , GB ₂ ,. It has become.

Here, as is clear from FIG.
Also in the example layout pattern, all pixel electrodes P
Display electrode P on the other side_{twenty one}Thin film transistor connected to
Star T₂Commonly connected drains of the ground side drain
Bus line (ground side drain bus line in Fig. 10)
In DBE₀₁, DBE₀₂, ...) are provided,
The bus line on the source side is the pixel matrix of the liquid crystal display panel.
It is provided only inside. That is, the drain on the data side
In-bus line DBD₁, DBD₂Ground side drain parallel to
For the in-bus line, the ground side dray in FIG.
Bus line DBE₀₁, DBE₀₂Mark the earth potential as
No bonding pad is provided to add
And a bonding pad for applying the ground potential
The gate bus line GB₁, GB₂Earth parallel to,…
Side drain bus line DBE₁, DBE ₂To be provided in
become.

As described above, the liquid crystal display panel of this embodiment is
As shown in FIG. 9, the
Formed on a glass substrate (corresponding to the glass substrate 11 in FIG. 8).
One pixel electrode P is connected to two display electrodes P₁₁And P_{twenty one}
And one display electrode P ₁₁Gate bus line GB₁,
GB₂, One of the thin film transistors T connected to₁Saw
Space S₁To the other display electrode P._{twenty one}The gate bar
Sline GB₁, GB₂The other thin film transistor connected to
T₂Source S₂Connect to. Here, the two display
Pole P₁₁And P_{twenty one}Opposed to the liquid crystal layer
A transparent electrode on the substrate (corresponding to the glass substrate 14 in FIG. 8).
Pole P₀(P_Ten, P₂₀) Is electrically separated for each pixel
(Shown by the broken line in FIG. 1). Also, on the other hand
Thin film transistor T₁Drain D₁Is the data voltage
Applied drain bus line (data side) DBD₁, DBD₂,
... and the other thin film transistor T₂of
Drain D₂Is a drain bussler held at ground potential
It is connected to the inn. And the drain on the ground side
All bus lines are commonly connected and ground potential is drain
Bus line DBE₁, DBE₂, ... is applied from
It

That is, each pixel electrode P is formed to have a size of, for example, 100 μm × 300 μm when pixels are arranged in an in-line type. On the long side of the pixel electrode P, the ground side drain bus line DBE is provided. _The ground potential is applied to ₁ , DBE ₂ , .... As a result, a liquid crystal display panel in which the level shift of the writing voltage caused by the capacitance of the channel portion of the thin film transistor is compensated by dividing the pixel electrode into two display electrodes can be implemented by the present technology. can do. That is, since the length of the pixel electrode P on the long side is, for example, about 300 μm, the gate bus lines GB ₁ , GB ₂ ,
The bonding pads for the ground-side drain bus lines DBE ₁ , DBE ₂ , ... Can be provided between the bonding pads for ... And the driving circuit can be mounted by the current mounting technology.

FIG. 2 is a layout pattern diagram showing another embodiment of the liquid crystal display panel of the present invention. In the layout pattern of FIG. 1 described above, the gate bus lines GB ₁ , GB ₂ , ...
Ground side drain bus line DB provided in parallel with
The ground potential is applied from all of E ₁ , DBE ₂ , ..., But the ground side drain bus lines DBE ₁ , DBE provided parallel to the gate bus lines GB ₁ , GB ₂ ,. ₂ ...
Is 1 for each pixel column (display electrode of each column).
It is not necessary to provide each book, for example, as shown in FIG.
It is also possible to provide a drain bus line (DBE ₁ ) on the ground side only for the first row or for every several rows and apply the ground potential from the drain bus line. In this way, for example, if the ground side drain bus lines provided in parallel to the gate bus lines GB ₁ , GB ₂ , ... The mounting density of the electrodes P can be improved.

FIG. 3 is a layout pattern diagram showing still another embodiment of the liquid crystal display panel of the present invention. 3, the gate bus line GB ₃ in the third column corresponds to the gate bus line GB ₁ of the first column, so that the same pattern is repeated in the vertical direction. The liquid crystal display panel shown in FIG. 3 is a drain bus line on the ground side (horizontal direction) provided in parallel with the gate bus lines GB ₁ , GB ₂ , ...
DBE ₀ is provided for the thin film transistors (T ₂ ) of the two pixel columns. Pixel electrodes are symmetrically provided on both sides of one drain bus line (DBE ₀ ). That is, the pixel electrodes Pa (P ₁₁ a, P ₂₁ a) and Pb (P ₁₁ b, P ₂₁ b) are symmetrically provided with the horizontal drain bus line DBE ₀ as the axis of line symmetry. .. As a result, compared with the liquid crystal display panel of FIG. 1, the number of drain bus lines DBE _{0 in} the horizontal direction can be reduced to half, and the mounting density of the pixel electrodes P can be improved.

FIG. 4 is an equivalent circuit diagram for explaining the operation of the liquid crystal display panel of the present invention, and FIG. 5 is a drive voltage waveform diagram for driving the liquid crystal display panel of the present invention. Figure 4
And as shown in FIG. 5, in the conventional matrix,
According to the present invention, a negative voltage shift occurs in the positive frame and a positive voltage shift occurs in the negative frame, although the negative voltage shift occurs in both the positive and negative frames. That is, as shown in FIG. 4A, in the positive frame, when the thin film transistor is turned off, a negative shift voltage V ₊ = −C _g / (C _LC + C _g ) · V _D is generated, and As shown in FIG. 4 (b), when the thin film transistor is turned off in the negative frame, a positive shift voltage V ₋ = C _g / (C _LC + C _g ) · V _D is generated. Since each pixel is separated, the DC voltage component is completely compensated for each pixel. (JP-A-2-2422
No. 28).

Here, as shown in FIG.
Applied data voltage (drain voltage) V_DIs constant
Since it is designed to input at a low value, the data
Pressure V _DWas originally written by correcting
Data can be input to each pixel. That is,
In this embodiment, the data side drain bus line DBD₁, DBD
₂The signal voltage (data voltage V_D) To the thin film
Change in data voltage due to channel capacitance of transistor
The voltage level to correct
There is.

[0024]

As described above in detail, according to the liquid crystal display panel of the present invention, the level shift of the write voltage caused by the capacitance of the channel portion of the thin film transistor when the pixel electrode is divided into two display electrodes. It is possible to mount a liquid crystal display panel that compensates for the above.

[Brief description of drawings]

FIG. 1 is a layout pattern diagram showing an embodiment of a liquid crystal display panel according to the present invention.

FIG. 2 is a layout pattern diagram showing another embodiment of the liquid crystal display panel of the present invention.

FIG. 3 is a layout pattern diagram showing still another embodiment of the liquid crystal display panel of the present invention.

FIG. 4 is an equivalent circuit diagram for explaining the operation of the liquid crystal display panel of the present invention.

FIG. 5 is a drive voltage waveform diagram for driving the liquid crystal display panel of the present invention.

FIG. 6 is an equivalent circuit diagram of a conventional liquid crystal display panel.

FIG. 7 is a drive voltage waveform diagram for driving a conventional liquid crystal display panel.

FIG. 8 is a diagram schematically showing a structure of a conventional thin film transistor having a storage capacitor.

FIG. 9 is a diagram showing an equivalent circuit of a liquid crystal display panel according to a conventional invention.

FIG. 10 is a layout pattern diagram of a liquid crystal display panel as a related technique to which the invention shown in FIG. 9 is applied.

[Explanation of symbols]

P ... pixel electrode P ₀ ... counter electrode P ₁₁ ... first display electrode P ₂₁ ... second display electrodes T ₁ ... first thin film transistor T ₂ ... second TFT _{DBD 1, DBD 2, DBD 3} ... first Drain bus line DBE ₀ , DBE ₁ , DBE ₂ , DBE ₃ … Second drain bus line GB ₁ , GB ₂ , GB ₃ … Gate bus line

Claims (4)

[Claims] 1. A thin film transistor (T ₁ , T ₂ ), a pixel electrode (P) connected to the source of the thin film transistor, a gate bus line (GB ₁ , GB ₂ , ...) Connecting the gate electrodes, and
Drain bus line (DB
_{D 1, DBD 2, ...;} DBE 1, DBE 2, ...) and a thin film transistor matrix substrate of insulating formed is translucent counter electrode which are arranged on opposite sides of the liquid crystal layer in the thin film transistor matrix substrate In a liquid crystal display panel having a counter substrate on which (P ₀ : P ₁₀ , P ₂₀ ) is formed, each pixel electrode (P) on the thin film transistor matrix substrate has the same gate bus line (GB ₁ , GB ₂ , ...) connected to the source electrode of the first thin film transistor (T ₁ ) of the two thin film transistors (T ₁ , T ₂ ), and the second thin film transistor (P ₁₁ ). The drain electrode of the _first thin film transistor (T ₁ ) is composed of a second display electrode (P ₂₁ ) connected to the source electrode of (T ₂ ). DBD ₁ , DBD ₂ , ...) and is connected to the second thin film transistor. The drain electrode of the transistor (T ₂ ) is the second drain bus line (DB
E ₁ , DBE ₂ , ...) and is opposed to the first display electrode (P ₁₁ ) and the second display electrode (P ₂₁ ) through the liquid crystal layer on the counter substrate (P ₀ : P ₁₀ , P ₂₀ ) is a liquid crystal display panel formed by being electrically separated for each pixel electrode, wherein the second drain bus line (DBE ₁ , DBE ₂ , ...) Is connected to the gate. It is formed so as to be parallel to the bus lines (GB ₁ , GB ₂ , ...), and the ground potential is applied to the second drain bus line from a position parallel to the gate bus line. LCD display panel. 2. The second drain bus line (DBE ₁ , D
_2. The liquid crystal display panel according to claim 1, wherein all BE ₂ , ..., Are connected in common and the ground potential is applied from at least one location. 3. The first and second display electrodes (P ₁₁ ,
P ₂₁ ) is formed so that the first and second thin film transistors (T ₁ , T ₂ ) connected to the first and second display electrodes are parallel to the gate bus lines (GB ₁ , GB ₂ , ...). Said second
The drain bus lines (DBE ₁ , DBE ₂ , ...) of the second drain bus lines (DB
_2. The liquid crystal display panel according to claim ₁ , wherein E ₁ , DBE ₂ , ...) Are used in common in two columns of thin film transistors. 4. The first drain bus line (DBD ₁ , D
_2. The liquid crystal display panel according to claim 1, wherein the data voltage applied to BD ₂ , ..., Has a voltage level for correcting a change in the data voltage caused by the channel capacitance of the thin film transistor.