JPH0572238A - Peak voltage value detection circuit - Google Patents

Abstract

PURPOSE:To realize the detection circuit capable of accurately detecting the peak voltage value of an inputted AC signal at a high speed. CONSTITUTION:A peak voltage value detection circuit is equipped with a peak detection circuit 10 consisting of a transistor T and a condenser C, a full-wave rectification circuit 20 subjecting an input signal to full-wave rectification and a differentiation circuit 30 differentiating the output of the full-wave rectification circuit 20. Further, an offset current supply 40 generating the offset current pulse allowed to flow to the transistor T of the peak detection circuit 10 from the output of the differentiation circuit 30 and a gate signal G, the transmission gate 50 opened and closed by the gate signal G to input the output of the full- wave rectification circuit 20 to the peak detection circuit 10 and a reset circuit 60 resetting the output of the peak detection circuit 10 to a predetermined voltage level are provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a peak voltage value detection circuit for an input AC signal. For example, in a magnetic disk device, when the off-track of the magnetic head is detected and the head position is corrected, it is necessary to detect the peak value of a minute voltage output from the magnetic head accurately and at high speed. There is.

There is a demand for a peak voltage value detection circuit for detecting the input peak voltage value accurately and at high speed.

[0003]

2. Description of the Related Art FIG. 6 is a diagram for explaining a conventional example. In the figure, 10 is a peak detection circuit composed of a transistor T and a capacitor C, 20 is a full-wave rectification circuit composed of transistors T1 and T2, 50 is a transmission gate, and 60 is a reset circuit.

Further, Vcc is a power source of a transistor, and I is a constant current source. In the above circuit, a full-wave rectifier circuit composed of transistors T1 and T2 is used to input voltages Vi + and V +.
i- is full-wave rectified and input to the peak detection circuit 10 via the transmission gate 50. In the peak detection circuit 10, when the transmission gate 50 is in the conductive state, the input voltage is applied to the base of the transistor T, the transistor T is turned “on”, and the capacitor C is charged with a voltage proportional to the input voltage.

The voltage charged in the capacitor C becomes the output voltage Vo. The reset circuit 60 is a capacitor C
Is discharged and reset to the initial state.

[0006]

The base-emitter voltage V _BE of the transistor T of the peak detection circuit 10 of the above-mentioned conventional example is not proportional to the input voltage and changes with time, so that an accurate peak voltage value can be obtained. No detection can be done. Further, when the offset current is constantly flowing, the charge stored in the capacitor C is discharged after the input signal reaches the peak value, which makes high-speed operation impossible.

The present invention is intended to realize a peak voltage value detection circuit capable of detecting the peak voltage value of an input signal accurately and at high speed.

[0008]

FIG. 1 is a block diagram for explaining the principle of the present invention. 10 in the figure is a transistor T
And a capacitor C, a peak detecting circuit 20, a full-wave rectifying circuit for full-wave rectifying an input signal, and a differentiating circuit 30 for differentiating the output of the full-wave rectifying circuit 20.

Reference numeral 40 is an offset current source for generating an offset current pulse to be passed through the transistor T of the peak detection circuit 10 from the output of the differentiating circuit 30 and the gate signal G, and 50 is opened / closed by the gate signal G. Reference numeral 60 is a transmission gate for inputting the output of the full-wave rectifier circuit 20 to the peak detection circuit 10. Reference numeral 60 is a reset circuit for resetting the output of the peak detection circuit 10 to a predetermined voltage. As a result, the electric charge charged in the capacitor C due to the offset current is eliminated.

[0010]

The input signal is full-wave rectified by the full-wave rectifier circuit 20, and the output is input to the differentiator circuit 30. Differentiating circuit 30
Then, by differentiating the input signal, the rising edge of the full-wave rectified output is detected, a pulse current synchronized with the rising edge is generated, and this pulse current and the gate signal G are input to the offset current source 40 to obtain the offset current. Generate a pulse.

The output subjected to full-wave rectification by the full-wave rectification circuit 20 is input to the peak detection circuit 10 through the transmission gate 50 to turn on the transistor T and charge the capacitor C. When the input voltage decreases from the peak value, the offset current pulse is at "0" level, the transistor T is "off", and the charge charged in the capacitor C is not discharged. There is no decrease in charging efficiency due to discharge.

Further, by opening the transmission gate 50 by the gate signal G delayed through the delay circuit 70,
The response speed can be increased by starting the operation after putting the transistor T in the standby state.

Further, a second peak voltage value detection circuit 200 having the same configuration with an input voltage of "0" is provided, and a difference output circuit 80 outputs the peak voltage value detection circuit 100 and the second peak voltage value detection circuit 100.
The peak voltage value can be accurately detected by taking the difference between the outputs of the peak voltage value detection circuit 200.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIGS. 2 and 3 are views (1) and (2) for explaining an embodiment of the present invention. Reference numeral 10 in the figure is a peak detection circuit, which includes a transistor T and a capacitor C, and
0 is a full-wave rectifier circuit, which is composed of transistors T1 and T2, 50 is a transmission gate, and transistor T
3, a reset circuit 60 is composed of transistors T5 and T6.

Reference numeral 30 is a differentiating circuit, which is composed of transistors T7 to T12, resistors R1 to R5, and capacitor C1, 40 is an offset current source, and transistors T13 to T16 and resistor R6 form an AND circuit 41. The transistors T17 to T22 and the resistors R7 to R9 form a delay circuit 70.

E is a constant voltage source and I is a constant current source. Further, A, B and C of FIG. 2 are connected to A, B and C of FIG. 3, respectively. FIG. 4 is a time chart of the embodiment of the present invention. FIG. 4 shows the operation of the embodiment of the present invention shown in FIGS.
The time chart will be explained.

The input voltage is shown, the thick line shows the + side input voltage Vi +, and the broken line shows the − side input voltage Vi−. The output of the full-wave rectifier circuit 20 obtained by full-wave rectifying the + side input voltage Vi + and the − side input voltage Vi− of is shown.

The output of the differentiating circuit 30 obtained by differentiating is shown. Differentiation is performed by the resistor R1 and the capacitor C1 shown in FIG. Is output to a comparator including transistors T10 and T11 to generate a pulse current.

The gate signal G is shown. The output is obtained by ANDing the gate signal G with the pulse current of the transistors T13 and T15.

By the transistors T17 to T21, Δ
It is the gate signal G delayed by t time. Δt is set to be longer than the time during which the transistor T of the peak detection circuit 10 is on standby.

The voltage charged in the capacitor C of the peak detection circuit 10 is shown. By passing a pulsed current to the transistor T of the peak detection circuit 10, the transistor T is set in a stamped state, the transistor T3 is turned “on” by the delayed gate signal G, and the output of the full-wave rectification circuit 20 is peaked. Since the signal is input to the detection circuit 10, the response can be speeded up.

Further, RS in FIG. 2 indicates a reset signal,
When the reset signal RS is input, the electric charge charged in the capacitor C is discharged through the transistor T6 to be reset. The reset level shown in in Fig. 4 is
It is a value determined by the transistors T5 and T6, slightly lower than the output when there is no input, and it is from "0" V to the capacitor C.
Charging can be performed faster than charging and the response speed can be increased.

FIG. 5 is a diagram for explaining another embodiment of the present invention, in which a second peak voltage value detection circuit 200 having the same configuration as that described in FIG.
By calculating the difference between the output of the peak voltage value detection circuit 100 and the output of the second peak voltage value detection circuit 200, the output voltage Vo that is proportional to the input signal can be accurately output.

FIG. 4 shows the output voltage Vo in this configuration.

[0025]

According to the present invention, the offset current supplied to the peak detecting transistor is set to a pulse current, whereby the electric charge charged in the capacitor can be prevented from being discharged. Further, the response can be speeded up by inputting an input signal after the peak detection transistor is set to the standby state.

Further, two peak voltage value detection circuits having the same structure are used, and one input has an input voltage to be detected,
The other input is left uninput, and the difference between the two peak voltage value detection circuits is taken to obtain an output that is accurately proportional to the input signal.

[Brief description of drawings]

FIG. 1 is a block diagram illustrating the principle of the present invention.

FIG. 2 is a diagram for explaining an embodiment of the present invention (1)

FIG. 3 is a diagram (2) illustrating an embodiment of the present invention.

FIG. 4 is a time chart of an example of the present invention.

FIG. 5 is a diagram for explaining another embodiment of the present invention.

FIG. 6 is a diagram illustrating a conventional example.

[Explanation of symbols]

 100 Peak Voltage Value Detection Circuit 200 Second Peak Voltage Value Detection Circuit 10 Peak Detection Circuit 20 Full Wave Rectifier Circuit 30 Differentiation Circuit 40 Offset Current Source 50 Transmission Gate 60 Reset Circuit 80 Difference Output Circuit T, T1 to T22 Transistors R1 to R9 Resistor C, C1 Capacitor E Constant voltage source I Constant current source

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Takayoshi Ikegami 2-1, Kitaichijo Nishi, Chuo-ku, Sapporo-shi, Hokkaido Fujitsu Hokkaido Digital Technology Co., Ltd.

Claims (4)

[Claims] 1. A peak voltage value detection circuit (100) for an input AC signal, the peak detection circuit (10) including a transistor (T) and a capacitor (C), and a full wave for full-wave rectifying an input signal. A rectifying circuit (20), a differentiating circuit (30) for differentiating the output of the full-wave rectifying circuit (20), an output of the differentiating circuit (30) and a gate signal (G),
An offset current source (40) that generates an offset current pulse that flows in the transistor (T) of the peak detection circuit (10) and an output of the full-wave rectification circuit (20) that is opened and closed by the gate signal (G). A peak voltage comprising: a transmission gate (50) input to the peak detection circuit (10); and a reset circuit (60) resetting an output of the peak detection circuit (10) to a predetermined voltage level. Value detection circuit. 2. The offset current source (40) is composed of a logical product circuit (41) which performs a logical product of the pulse voltage output from the differentiating circuit (30) and the gate signal (G),
The peak voltage value detection circuit according to claim 1, wherein a pulsed offset current is generated. 3. A delay circuit (70) for delaying the gate signal (G) for a predetermined time is provided, and the peak detection circuit (1) is provided.
Peak according to claim 1, characterized in that after the transistor (T) of 0) is activated, the transmission gate (50) is opened by the gate signal (G) delayed by the delay circuit (70). Voltage detection circuit. 4. The peak detection circuit (10), which is the same as the constituent elements of the peak voltage value detection circuit (100), the full-wave rectification circuit (20), the differentiating circuit (30), and the offset current source. (40) and the transmission gate (50)
A second peak voltage value detection circuit (200) including a second peak voltage value detection circuit (200), the full-wave rectification circuit (20) of the second peak voltage value detection circuit (200) has no input, and a differential output circuit (80) The peak voltage value detection circuit according to claim 1, wherein the difference between the output of the peak voltage value detection circuit (100) and the output of the second peak voltage value detection circuit (200) is calculated and output.