JPH0572131B2 - - Google Patents

Description

[Detailed Description of the Invention] [Summary] Regarding a phase shift circuit, particularly a phase shift circuit for obtaining an output signal by arbitrarily shifting the phase of an input signal from 0° to 360°, a filter consisting of L, C, and R is used. The purpose is to provide a 0° to 360° phase shift circuit made of semiconductor elements that can be integrated without using a 0° to 360° phase shift circuit.
a separation unit that separates into a phase-separated signal and a π/2 phase-separated signal; and a 0-phase and π/2-phase separated signal that receive the 0-phase and π/2-phase separated signals and have a mutual phase difference of 90° and 180°.
a distribution unit that distributes into 2-phase and π-phase distribution signals, and receives the 0-phase, π/2-phase, and π-phase distribution signals and decomposes them into a plurality of types of phase-shifted signals each having a phase range; a weighting synthesis section that weights each amplitude and then synthesizes the same, and is configured to generate an output signal in which a phase shift proportional to the weighting is added to the input signal according to a weighting control signal. do.

[Industrial application field]

The present invention relates to a phase shift circuit, and particularly to a phase shift circuit for obtaining an output signal by arbitrarily shifting the phase of an input signal from 0° to 360°.

Phase shifting circuits that arbitrarily shift the phase of an input signal are often required in various fields. For this reason, various implementation means including delay lines and the like have been proposed. However, the implementation methods to date have targeted relatively low-frequency input signals (for example, several tens of MHz or less), and have targeted high-frequency input signals of several hundred MHz or higher, and have been able to arbitrarily shift this over a range of 0° to 360°. There are few ways to achieve this.

[Conventional technology]

FIG. 17 is a diagram showing an example of a general device to which the present invention is applied. In this figure, the present device is specifically a regenerative repeater 10, which is appropriately inserted in the middle of a transmission path and plays the role of recovering waveform distortion and attenuation of a signal. The input IN becomes an input signal DT equalized by an equalization amplifier circuit 11, and a clock CK component thereof is extracted by a timing extraction circuit 12.
The extracted clock CK is applied to the identification circuit 14 through the cable 13, and this clock CK identifies whether the input signal DT is "1" or "0". Using the identified "1" and "0", the transmission signal is regenerated by the regeneration circuit 15 and sent out again to the transmission path OUT.

In the identification circuit 14, when the input signal DT is punched out using the clock CK, the punching is performed for each DT.
This is done approximately at the center of the bit, and each bit is identified.
This punching can be performed relatively accurately when the signal DT is at a low speed. However, as the signal DT becomes faster, the pulse width of each bit becomes narrower, causing small jitters that cause the punching to fail. For example, in a transmission line using optical fiber, in order to handle high-speed signals of several 100 Mb/s, a regenerative repeater 10 (optical/electrical converter (IN side) and electrical/optical converter (OUT side) are installed at both ends of the regenerative repeater 10) ), the regenerated clock CK is the input signal
Accurate phase synchronization with DT is required.

Conventionally, cable 1 was used for such phase synchronization.
A subtle phase shift was applied to the clock CK that was transmitted at 3. That is, the cable 13 is cut little by little while observing with an oscilloscope or the like, and the cable length is gradually shortened to add the desired phase shift.

In response to a desire to eliminate such manual phase shifting work, a phase shifting circuit using a filter was proposed. FIG. 18 is an example of a conventional phase shift circuit,
Consists of filters. This phase shift circuit 20 will be inserted in the middle of the cable 13 shown in FIG. Both the input signal S _io and the output signal S _put have a frequency of _0.
However, S _put has a phase shift added to S _io . For this phase shift, a phase shift control signal S _c is applied from the outside to shift the center frequency _c of the filter.

FIG. 19 is a characteristic diagram for explaining the principle _of a conventional phase shift circuit.
By shifting the center frequency _c to _c ', a phase shift of Δθ is added.

FIG. 20 is a diagram showing an example of the waveform of an output signal obtained by adding a phase shift to the input signal, and the phase of the input signal S _io is changed by Δθ
The dotted line shows the output signal S _put when shifted by .

[Problem that the invention seeks to solve]

Since the conventional phase shift circuit 20 consists of a filter,
It is constructed using an inductance L, a capacitor C, and a resistor R as basic elements. However, according to such a filter, the center frequency of the filter
Since a variable L or variable C is required to shift _c , there is a problem in that a wide band cannot be expected.
Also, the higher the frequency of the input signal, the more variable L.
There is also the problem that adjustment of variable C becomes difficult. Furthermore, there is a disadvantage that relatively large elements such as variable L and variable C must be provided.

The present invention does not use filters made of L, C, and R, and is made of semiconductor elements that can be integrated.
The purpose of this invention is to provide a phase shift circuit.

[Means for solving problems]

FIG. 1 is a diagram showing the principle configuration of a phase shift circuit according to the present invention. In this figure, the separation unit 31 inputs the input signal S _io
In response, a 0-phase separated signal S _s0 and a π/2-phase separated signal S _s90 having a phase difference of 90° are generated.

The distribution unit 32 receives 0 phase and π/2 phase separated signals S _s0 ,
In response to S _s90 , a 0-phase distribution signal S _d0 , a π/2-phase distribution signal S _d90 and a π-phase distribution signal S _d180 having phase differences of 90° and 180° are generated.

The weighted synthesis unit 33 has 0 phase, π/2 phase and π
The phase distribution signals S _d0 , S _d90 , and S _d180 are received and decomposed into a plurality of types of phase shift signals each having a phase range, and the amplitude components of each are weighted and then combined.

The phase shift circuit 30 receives a weighting control signal from the outside.
S _w is received and the above weighting is determined. This weighting determines the amount of phase shift of S _put with respect to S _io .

[Effect]

The 0-phase separated signal S _s0 and the π/2-phase separated signal S _s90 from the separation unit 31 can be arithmetically expressed as cos θ and sin θ, respectively. In the weighted synthesis section 33, a
The calculation cos θ+b sin θ is first performed. a and b are amplitude components of the phase-shifted signal within the combining section 33. The calculation result is √ ² + ² cos(θ−φ), where φ determines the amount of phase shift. Since this φ is tan ⁻¹ [b/a], tan ⁻¹ [b/a], that is, the phase shift amount φ can be arbitrarily set by controlling a:b using the weighting control signal S _w . This φ is 0°~
In order to cover up to 360°, multiple types of phase shift signals each having a phase range are required, and for this reason, the distribution unit 32 increases the number of phase shift signals.

Thus, the phase shift circuit 30 of the present invention has the following configurations: 0°, 90°,
Since the phase shift amount can be controlled by calculation based on a typical phase shift signal of 180°, there is no need for variable L or variable C, and the range from 0° to 360° is achieved using only semiconductor elements. A phase shift over .degree. is possible.

〔Example〕

FIG. 2 is a diagram showing an embodiment according to the present invention. In this figure, the distribution section 32 is a first distributor 32
1 and a second distributor 322, which receive the 0-phase and π/2-phase separated signals S _s0 and S _s90 from the separating section 31, respectively. The first distributor 321 receives S _s0 and generates 0-phase and π-phase distribution signals S _d0 and S _d180 having a phase difference of 180°, and the second distributor 32
2 receives S _s90 and has a mutual phase difference of 180° π/
A two-phase distribution signal S _d90 and a 3π/two-phase distribution signal are generated. However, the 3π/2-phase distribution signal is not used.

The weighting distribution unit 33 includes a first weighting combiner 331 and a second weighting combiner 332 at the first stage, and also includes third to seventh weighting combiners 333 to 337 at the middle, rear, and final stages. These weighting combiners 331 to 337 all have the same configuration and commonly receive the same weighting control signal S _w .
The phase-shifted signals received and output by each weighted combiner are S〓 ₁ , S〓 ₁ ′, S〓 ₂ , S〓 ₃ , S〓 ₃ ′, S
〓 ₄ ,
S〓 ₅ , S〓 ₆ and S〓 ₇ , S〓 ₇ is the desired output signal S _put , and each phase-shifted signal S〓 ₁ to S〓 ₇ has an individual phase range, and each phase Range 0°~90°,
It is clearly indicated in the diagram as 90° to 180°, etc. During this time, various signal routes are formed, and the target output signal _Sput is generated while passing through a phase range corresponding to the desired amount of phase shift.

FIG. 3 is a circuit diagram showing an example of the separating section, which is simply composed of a CR circuit. capacitor 42
(capacitance value C ₁ ) and the resistor ₄₃ (resistance value _{R 2} ) _{. put1} )
and a π/2 phase separated signal with a phase delay of 45° from this
S _s90 (voltage V _put2 ) is generated between resistor 41 (R ₁ ) and capacitor 44 (C ₂ ).

FIG. 4 is a complex plane diagram showing the phases of the separated signals S _s0 and S _s90 , and there is a phase difference of 90° (=45°×2). The phase difference of 90° is created as shown in Figure 3.
This is because the following relationship holds between V _put1 (S _s0 ), V _put2 (S _s90 ), and S _io .

V _put1 = −j1/ωC ₁ /R ₁ −j1/ωC ₁・V _io (1) V _put2 = R ₂ /R ₂ −j1/ωC ₂・V _io (2), where R ₁ = 1 /ωC ₁ and R ₂ = 1/ωC ₂ , it can be expressed as V _put1 = 1-j/2・V _io (3) V _put2 = 1+j/2・V _io (4) Therefore, V _put1 , that is, S _s0 has a phase difference of 90° with respect to V _put2 , that is, S _s90 .

FIG. 5 is a circuit diagram showing a specific example of a distributor, and shows the first distributor 321 of FIG. 2. In FIG. The second distributor 322 also has exactly the same configuration. This is, so to speak, a differential amplifier (indicated by 51) type, which receives a signal S _s0 and obtains S _d180 and S _d0 having a phase difference of 180° from one output and the other output. I is a constant current source, and V _ref is a reference voltage. This type of distributor is suitable for high speed operation.

FIG. 6 is a circuit diagram showing another specific example of the distributor, and although the first distributor 321 is shown, the same applies to the second distributor 322. It is of the one-transistor type (indicated by 61), as it were, and receives the signal S _s0 at its base and obtains S _d180 and S _s0 at its collector and emitter, respectively. These have a mutual phase difference of 180°. If a PNP type transistor is used instead of the NPN type shown in the figure, the relationship between 0° and 180° will be reversed.

FIG. 7 is a circuit diagram showing a specific example of a weighted combiner, in which the first weighted combiner 331 is shown as a representative, but the other second to seventh weighted combiners 332 to 3 are shown as a representative example.
37 also has exactly the same configuration. Moreover, all of these weighting combiners 331 to 337 are weighted, that is, the phase amount is controlled by the same weighting control signal S _w . If the weighting control signal S _w is made different for each weighting combiner, etc., then
This is because the regularity of the phase range described above shown in FIG. 2 is lost.

The first weighting combiner 331 receives the 0-phase distributed signal
When S _d0 is input, the first differential amplifier 71 and π/2
When the phase distribution signal S _d90 is input, the second differential amplifier 72
are connected in parallel between the collectors of the corresponding transistor pairs to obtain the phase-shifted signals S〓 ₁ and S〓 ₁ ', and the weighting control signal S _w is input, and these first and second differential amplifiers 71 and a third differential amplifier 73 which extracts weighting currents I _a and I _b from the common emitter side of each of 72 . The weighting ratio is determined by the balance between the voltage of the signal S _w and the reference voltage V _ref3 . For example, if V _ref3 is OV, the voltage of S _w changes between +3 and -3V, and the maximum of I _a (minimum of I _b )
~The minimum of I _a (maximum of I _b ) can be set arbitrarily. this
I _a :I _b forms the ratio of a:b in φ=tan ^-1 [b/a] (phase shift amount) described above, and (a:
When b) is varied from (1:0) to (0:1), φ changes between 0° and 90°. The phase shift signal S〓 ₁ in the figure is a signal from 0° to 90° as shown in Fig. 2, and when setting it to 0°, set I _a to the minimum and I _b to the maximum, and set it to 90°. When setting, set I _a to the maximum and I _b to the minimum, and when setting it to 45° in between, set I _a = I _b . The magnitude of I _a and I _b is determined by the level of signal S _w . If this level is +3V, it is the maximum of I _a (minimum of I _b ), and if this level is -3V, it is the minimum of I _a (maximum of I _b ). In addition,
The sum of I _a and I _b is always constant (I _R ) due to constant current source I.
It is. Therefore, a 45° phase shift in S〓 ₁ is
It is obtained when I _a =I _b =I _R /2, that is, when the level of S _w and the level of V _ref3 become almost equal.

Thus the weighting of I _a and I _b , i.e. S _d0 and S _d90
Since weighting has been performed, it is necessary to further synthesize these to obtain S〓 ₁ and S〓 ₁ ′. The composition of S〓 ₁ is
This can be easily achieved by sharing the load resistor 74 with the transistors 711 and 721. In addition, to synthesize S〓 ₁ ', the load resistor 75 is connected to the transistors 712 and 7
This can be easily done by sharing it with 22. these
S〓 ₁ and S〓 ₁ ′ are both the weighting combiner 33 of the next stage.
3,334, but the weighting synthesizer 33
5, 336 and 337, only one output is used, the other remains unused.

FIG. 8 is a circuit diagram showing another specific example of the weighting synthesizer, and similar to FIG. 7, the first weighting synthesizer 3
31, but other combiners 332 to 337
This also applies to However, only the side that outputs the phase-shifted signal S〓 ₁ is shown, and the side that outputs S〓 ₁ ' has the same configuration, so its description will be omitted. In the example shown in the figure, transistors 81 and 82 are provided which receive the 0-phase distribution signal S _d0 and the π/2-phase distribution signal S _d90 at their bases, respectively.
Anti-fixed resistors 83 and 84 are provided for adjusting weighting currents I _a and I _b , respectively. Reference numeral 74 denotes the load resistance for synthesis described above (FIG. 7). In this case, the semi-fixed resistors 83 and 84 are interlocked so that they are inversely proportional to each other. The reason why it is inversely proportional is clear from the explanation of I _a and I _b in Fig. 7. In this type of weighting synthesizer, the weighting control signal S _w is inputted from semi-fixed resistors 83 and 84 . Generally, in a regenerative repeater, once the phase of the clock CK is adjusted, it is not adjusted frequently thereafter, so such a semi-fixed resistor can be used satisfactorily.

Referring again to FIG. 7, FIG. For example, a phase-shifted signal
Looking at S〓 ₁ (same as for S〓 ₁ ′), it was found that its amplitude fluctuates depending on the phase (0° to 90°). Such amplitude fluctuations are undesirable for performing highly accurate phase shifting. Here, the reason why amplitude fluctuations that follow the phase occur is as follows. The gains of the first and second differential amplifiers 71 and 72 in _FIG .
Assuming G ₂ , the above-mentioned calculation result, √ ² + ² cos (θ−φ), can be expressed as √ ₁ ² + ₂ ² COS (θ−φ) (5). Here, the weighting currents flowing through the first and second differential amplifiers 71 and 72, respectively, are I _a and I _b , so the gains G ₁ and G ₂ are: G ₁ = R _L ÷ [V _T /I _a +R _e ] (6) G ₂ = R _L ÷ [V _T /I _b + R _e ] (7). However, R ₁ is the resistance value of the load resistors 74 and 75, and R _e is the resistance value of the transistors 711, 712, 72.
The resistance value of each emitter side resistor 76 to 79 of 1,722, V _T is V _T =kT/q (8), where k is Boltzmann's constant, T is absolute temperature, and q
is a charge, and V _T /I _a and V _T /I _b each represent the emitter resistance of the transistor. After all, what can be seen from the above equations (6) to (8) is that the gains G ₁ and G ₂ change according to the fluctuations of I _a and I _b . Therefore, in order to suppress such amplitude fluctuations of the phase-shifted signal, it is desirable to provide an amplitude fluctuation compensator.

FIG. 9 is a diagram showing a weighting synthesizer with an amplitude fluctuation compensator, and the first weighting synthesizer 3 in FIG.
In place of the constant current source I of 31, an amplitude fluctuation compensator 90
This corresponds to the one with .

First, the principle of this compensation section 90 will be explained. Figure 10 is a graph showing amplitude fluctuations, where the vertical axis shows the amplitude (√ ₁ ² + ₂ ² ) of the phase-shifted signal (S〓 ₁ , S〓 ₁ ') in Figure 9, and the vertical axis shows the weight. The voltage V _w of the attachment control signal S _w is shown below. What is clear from this graph is that the amplitude reaches its maximum when V _w becomes equal to the reference voltage V _ref3 .

FIG. 11 is a graph showing the relationship between the sum of weighted currents and the amplitude, and the sum current I _c (=I _a
+I _b ) has a nearly linear relationship with the amplitude (√ ₁ ² + ₂ ² ). Considering the graphs in FIGS. 10 and 11, it is sufficient that the sum current I _c exhibits a characteristic opposite to that in FIG. 10.

FIG. 12 is a graph showing the relationship between the sum current and the weighted control signal voltage, and has a valley-shaped characteristic that exactly cancels out the mountain-shaped characteristic shown in FIG. 10.

FIG. 13 is a diagram showing an embodiment of the amplitude fluctuation compensator, which is composed of a compensation control circuit 91 and a current source circuit 92 controlled by a compensation control voltage V _c outputted from the compensation control circuit 91. This voltage V _c shows a change similar to the curve in FIG. 12.

FIG. 14 is a circuit diagram showing a specific example of the compensation control circuit, which includes a simulation circuit section 100 and a voltage synthesis section 101, and outputs a compensation control voltage V _c . 102 is a level shifter for level adjustment, but it has nothing to do with the essence of this circuit 91. Therefore, the composite voltage (V _c ) in the voltage synthesizer 101 is depicted as being applied to the current source circuit 92 at the same level.

FIG. 15 is a level chart of the main part in FIG. 14, and shows the simulated voltages V ₁ and V ₂ as well as the compensation control voltage V _c (=V ₁ +V ₂ ) and the weighted control signal voltage.
Shows the relationship with V _w . In conclusion, the purpose is to create a compensation control voltage V _c with the characteristics shown in FIG. ₁₂ , which can cancel out the characteristics shown in _FIG . V _c =
V ₁ +V ₂ ) (dotted line in Figure 15). simulated voltage
V ₁ and V ₂ are connected to the simulation circuit section 1 that simulates the differential amplifiers 71 and 72 shown in FIGS. 7, 9, and 13.
This is the voltage generated at 00. In short, the differential amplifier 71 that caused the characteristics shown in FIG.
A circuit equivalent to 72 is simulated, characteristics equivalent to those shown in FIG. 10 are reproduced, and this is generated as V _c .

Output signal with less amplitude fluctuation due to the measures mentioned above
S _put is obtained, but this does not mean that amplitude fluctuations have completely disappeared; some fluctuations remain. Such residual fluctuations are not desirable for the clock CK in the previously described regenerative repeater 10 (FIG. 17) of several hundred MHz or more.

FIG. 16 is a diagram showing an example of the use of the circuit of the present invention, in which the timing extraction circuit 1 in the regenerative repeater 10
2 is a block diagram depicting part 2 in more detail. This constitutes a timing circuit 110 as a whole, and a phase shift circuit 30 of the present invention is inserted between a filter 111 and a limiter amplifier 112. Inserting it here is convenient because the residual fluctuations mentioned above will not appear on the clock CK. If it were to be placed before the filter 11, it would be undesirable because it would likely increase the jitter of the clock CK. Therefore, as shown in the figure, it is placed before the limiter amplifier 112. Since the output of filter 111 is a sine wave, jitter does not increase. The limiter amplifier 112 has a high gain and functions as a waveform shaper, and can sufficiently absorb the above-mentioned residual fluctuations in amplitude.

〔Effect of the invention〕

As described above, according to the present invention, a phase shift circuit that can be assembled as a semiconductor integrated circuit without using variable L or variable C at all, and that can be used in a wide band and high frequency is realized.

[Brief explanation of the drawing]

FIG. 1 is a basic configuration diagram of a phase shift circuit according to the present invention,
FIG. 2 is a diagram showing an embodiment of the present invention, FIG. 3 is a circuit diagram showing an example of a separation section, and FIG. 4 is a separation signal
A complex plan view showing the phase of S _s0 and S _s90 , Fig. 5 is a circuit diagram showing one specific example of a distributor, Fig. 6 is a circuit diagram showing another specific example of a distributor, and Fig. 7 is a weighting diagram. FIG. 8 is a circuit diagram showing another specific example of a weighted synthesizer, FIG. 9 is a diagram showing a weighted synthesizer with an amplitude fluctuation compensation section, and FIG. 10 is a circuit diagram showing a specific example of a weighted synthesizer. A graph showing the amplitude fluctuation, Fig. 11 is a graph showing the relationship between the sum of weighted currents and amplitude, Fig. 12 is a graph showing the relation between the sum current and the weighting control signal voltage, and Fig. 13 is a graph showing the amplitude fluctuation compensation. 14 is a circuit diagram showing a specific example of the compensation control circuit, FIG. 15 is a level chart of the main part in FIG. 14, and FIG. 16 is an example of use of the circuit of the present invention. 17 is a diagram showing an example of a general device to which the present invention is applied, FIG. 18 is an example of a conventional phase shift circuit, and FIG. 19 is for explaining the principle of a conventional phase shift circuit. FIG. 20 is a diagram showing an example of the waveform of an output signal obtained by adding a phase shift to the input signal. In the figure, 30...phase shift circuit, 31...separation section, 32...distribution section, 33...weighting synthesis section,
321, 322...distributor, 331-337...
Weighting synthesizer, S _io ...input signal, S _put ...output signal, S _w ...weighting control signal.

Claims (1)

[Claims] 1. A 0 _{-phase separated signal S s0 and a π/2-phase separated signal S s90 having a} phase difference of 90° from each other upon receiving the input signal S io
a separation unit 31 that receives the 0-phase and π/2-phase separated signals S _s0 , S _s90 and generates 0-phase distributed signals S _d0 and π/2-phase distributed signals having mutual phase differences of 90° and 180°; a distribution unit 32 that distributes the signal S _d90 and the π-phase distribution signal S _d180 ; and the 0-phase, π/2-phase and π-phase distribution signals S _d0 ,
A weighting synthesis unit 3 receives S _d90 and S _d180 and decomposes them into multiple types of phase-shifted signals each having a phase range, weights each amplitude, and then synthesizes the signal.
3, and the weighting control signal S _w from the outside
determine the weighting by and add a phase shift proportional to the weighting to the input signal _Sio
In the phase shift circuit that generates S _put , the distribution unit 32 includes a first distributor 321 and a second distributor 322 that receive the 0-phase and π/2-phase separated signals S _s0 and S _s90 , respectively, and The weighted synthesis unit 33 receives the 0-phase and π/2-phase distribution signals S _d0 and S _d90 and generates phase-shifted signals (S〓 ₁ ,
a first weighting synthesizer 331 that outputs S〓 ₁ '; and receiving the π/2-phase and π-phase distribution signals S _d90 and S _d180 , generates a phase-shifted signal S〓 ₂ in the phase range of 90° to 180°; a second weighting synthesizer 332 that outputs the phase range signals S〓 ₁ and S〓 ₂ ;
0° to 180° and 180° to 360° phase-shifted signals S〓 ₃ , S〓 ₃ ′
a third weighted synthesizer 333 that outputs a phase-shifted signal S〓 1 ′, S〓 2, and a fourth weighted synthesizer 333 that receives the phase-shifted signals S〓 ₁ ′, S〓 ₂ and outputs a phase-shifted signal S〓 ₄ in the phase range of 90° to 270°. a synthesizer 334; receiving the phase-shifted signals _S〓3 , _S〓4 ;
a fifth weighting synthesizer 335 that outputs a phase shift signal S〓 ₅ in the range _of 0° to ₂₇₀ °; a sixth weighting synthesizer 336 that outputs a phase signal S〓 ₆ ; and a sixth weighting synthesizer ₃₃₆ that outputs a phase signal S〓 ₆ ;
a seventh weighting synthesizer _{337 that outputs a phase-shifted signal S〓 7 of} 0° to 360° _;
A phase shift circuit characterized by: 2 The separating section 31 connects the capacitor 42 and the resistor 4
1 and a second CR circuit consisting of a resistor 43 and a capacitor 44 are directly connected, and the input signal S _io is received at an intermediate connection point between the capacitor 42 and the resistor 43. Then, the 0-phase separation signal S _s0 is output from the intermediate connection point between the resistor 41 and the capacitor 42, and the π/
Claim 1 for outputting a two-phase separated signal S _s90
Phase shift circuit described in section. 3. The first and second dividers 321 and 322 each include a differential amplifier 51, and the base of one transistor of a pair of transistors constituting the differential amplifier 51 receives the 0-phase and π/2-phase separated signal S. _s0 , S _s90 , the base of the other transistor receives a reference voltage V _ref , and the 0-phase, π/2-phase and π-phase distribution signals S _d0 , S The phase shift circuit according to claim 1, which outputs either _d90 or _Ss180 . 4. The first and second distributors 321 and 322 each include a transistor 61, which receives one of the 0-phase and π/2-phase separated signals S _s0 and S _s90 at its base, and receives the 0-phase separated signal S s0 and S s90 at its collector and emitter. phase, π/2 phase and π phase distribution signals S _d0 , S _d90 ,
Claim 1 which outputs any of S _d180
Phase shift circuit described in section. 5 The first to seventh weighted synthesizers 331 to 33
7 is a first differential amplifier 71, a second differential amplifier 72 whose collectors are connected in parallel to the first differential amplifier 71, and a common terminal of the first and second differential amplifiers 71 and 72, respectively. A third differential amplifier 73 extracts weighted currents I _a and I _b from the emitter side, and each signal input side transistor in the first and second differential amplifiers 71 and 72 has a predetermined phase difference from the previous stage. A pair of signals having a predetermined phase are received at each base, and the phase-shifted signal having a predetermined phase is outputted to the next stage, and the signal input side transistor in the third differential amplifier 73 receives the weighting control signal S _w
2. A phase shifting circuit according to claim 1, which receives: 6 The first to seventh weighted synthesizers 331 to 33
7, a pair of transistors 81 and 82 each receiving a pair of signals having a predetermined phase difference from the previous stage at each base, and a predetermined weighting current for these.
Consisting of resistors 83 and 84 that flow I _a and I _b , respectively,
The resistors 83 and 84 are semi-fixed resistors that are adjusted according to predetermined weighting, and both resistors 83 and 84 are semi-fixed resistors that are adjusted according to predetermined weighting.
2. The phase shifting circuit according to claim 1, wherein the phase shifting circuits are interlocked in an inversely proportional relationship. 7. The phase shift circuit according to claim 5, wherein an amplitude variation compensator 90 for suppressing amplitude variation of the phase shift signal is provided on the common emitter side of the third differential amplifier 73. 8 The amplitude fluctuation compensator 90 includes a current source circuit 92 connected to the common emitter side of the third differential amplifier 73, and a sum of the weighted currents I _a and I _b flowing through the third differential amplifier 73. A compensation control circuit 91 that controls the current I _c is provided, and the compensation control circuit 91 controls the weighting control signal S _w and the third differential amplifier 7.
8. The phase shift circuit according to claim 7, which receives the reference voltage V _ref3 of No. 3 as an input and outputs a compensation control voltage V _c for changing the sum current I _c . 9 The compensation control circuit 91 includes a simulation circuit section 1 that simulates the first and second differential amplifiers 71 and 72.
9. The phase shift circuit according to claim 8, comprising a voltage synthesis section 101 that outputs the compensation control voltage V _c which is a synthesis of the collector voltages V ₁ and V ₂ appearing in the simulation circuit section 100 .