JPH0572108B2 - - Google Patents

Description

[Detailed description of the invention]

This invention relates to improvements in semiconductor integrated circuit devices. Integrated Injection Logic (hereinafter referred to as Integra Injection Logic)
This will be explained using a circuit device (hereinafter referred to as "IIL/IC") as an example. FIGS. 1a to 1e are cross-sectional views showing the main steps of a conventional IIL/IC structure in order to better understand the structure. However, what is shown here is the case of one output (fan-out). That is, this IIL IC is manufactured by forming an n-type high impurity concentration (referred to as n ⁺ type, hereinafter referred to as this) buried layer 2 on a p-type silicon substrate 1, as is generally done in bipolar ICs. , an n-type low impurity concentration (referred to as n ^- type, hereinafter referred to as this) epitaxial layer 3 is grown, and then an oxide film 10 is grown.
1 and a nitride film 201, which is an oxidation-resistant film, are sequentially formed and patterned into a predetermined shape. Using this as a mask, the n ^- type epitaxial layer 3 is etched to a predetermined depth, and then etched by ion implantation. A p-type ion implantation layer 4 for a channel cut prevention layer is formed, and selective oxidation is performed using the nitride film 201 as a mask to form an isolation oxide film 102 (FIG. 1a).
Next, after removing the nitride film 201 and the oxide film 101, a thin oxide film 103 is formed again, and this is passed through a required resist mask (the resist mask at this stage is not shown). After implanting boron ions to selectively form the p ^- type layer 6 on the n ^- type epitaxial layer 3, a resist mask 301 with the desired pattern is formed again, and this is used to implant boron ions through the oxide film 103. by implanting p ⁺ into the n ^- type epitaxial layer 3.
Form layers 7, 8, 9 (FIG. 1b). Next, after removing the resist mask 301, a phosphor glass film 401 is grown on the entire upper surface by CVD method, and then
This phosphorus glass film 401, the p ^- type layer 6 and the p ⁺ type layers 7, 8, and 9 are annealed simultaneously.
A p ^- type layer 6a and p ⁺ type layers 7a, 8a, 9a are formed [FIG. 1c]. Next, a window is formed in the phosphor glass film 401 and the oxide film 103 in a part above the p ^- type layer 6a, and an n type impurity is introduced therethrough, and annealing is performed to form an n ⁺ type layer 10a. At the same time, the p ^- type layer 6a becomes the p ^- type layer 6b, and the p ⁺ type layer 7
A, 8a, and 9a are grown into 7b, 8b, and 9b, respectively [Figure 1 d]. Next, windows are opened on each of the p ⁺ type layers 7b and 9b, and the above n ⁺ type layer 1 is opened.
Electrode wiring is carried out through the metal silicide layer 501 along with the upper window part of 0a, and an injector electrode 11 is connected to the p ⁺ type layer 7b which is the emitter of the pnp transistor, and an injector electrode 11 is connected to the p + type layer 7b which is the collector of the pnp transistor and which operates in the reverse direction. For taking out the electrode connected to the p ^- type layer 6b which is the base of the transistor
An input electrode 12 is provided on the p ⁺ type layer 9b, and further,
n ⁺ , which is the collector of a reverse-operating npn transistor
Output electrodes 13 are connected to the shaped layer 10a to complete this IIL gate [first
Figure e]. The above shows a basic 1-output IIL gate, but
Figure 2 is a plan view of this conventional IIL gate with three outputs and two inter-gate wirings.
14 and 15 are the first collector C ₁ and the second collector C 1 , respectively.
The three output electrodes 21 and 22 connected to the collector C ₂ and the third collector C ₃ are inter-gate wirings. The three collectors C ₁ , C ₂ , and C ₃ are arranged in the order of distance from the input (base) electrode 12 . Now, as shown in FIG. 3, the current amplification factor β _u of the reverse operation npn transistor decreases more greatly in the high current region of the collector current I _c as the collector is farther away from the base electrode 12. This is thought to be because the base resistance increases as the collector is farther away from the base electrode. Further, it is known that there is a power delay characteristic as shown in FIG. 4 between the gate propagation delay time t _pd of IIL and the power consumption P _d . (for example,
Semiconductor Transistor Research Group, IEICE Technical Report SSD76~
89, p37: High Speed IIL with Self-Aligned
Double Diffusion Injector〔S ² L〕). Here, if the base area is the same and the pnp transistor characteristics are the same, an inversely proportional relationship such as t _pdnio ∝β _u ^-0.15 will hold as shown in Figure 5, so as shown in Figure 6, the collector far from the base electrode (The larger the distance D _CB between the collector and base electrode)
The minimum delay time t _pdnio increases. Therefore, in the performance of IIL gates manufactured using conventional manufacturing methods, there are differences in characteristics between each output electrode, as shown in Table 1. be restricted. Furthermore, even if the manufacturing method is the same, the current amplification factor β _u
As shown in FIG. 7, is proportional to the ratio S _C /S _B of the collector area S _C to the base area S _B. In the conventional structure, as shown in FIG. 2, the base region consisting of a p ^- type region (6b) and connected p ⁺ type regions (8b) and (9b) extends below the inter-gate wirings 21 and 22. As shown in Table 1, the base area S _B
is large, so the ratio S _C /S _B with the collector area S _C becomes very small, and the current amplification factor β _u becomes small,
The minimum delay time t _pdnio becomes large even in the collector C ₁ closest to the base electrode, and the power supply current Iinj also increases.
The delay time t _pd also increases when it is set to about 200 μA/gete.

[Table] Also, Figure 8 is a diagram showing that the gate minimum delay time _tpdnio differs depending on the relative position of each terminal.
Even if the collector-base distance D _CB is the same,
The minimum delay time t _pdnio is smaller when the injector electrode is closer to the collector electrode (curve B) than when the injector electrode is closer to the base electrode (curve A). In the case of the former (injector-base-collector arrangement), Figure 9 shows the 10th
The figure is a schematic cross-sectional view for explaining the configuration and operation in the latter case (injector-collector-base arrangement), where I is the injector terminal, B is the base terminal, C is the collector terminal, and E is the grounded emitter terminal. be. In both Figures 9 and 10, Figure a shows the current when the gate output switches from a low level to a high level (L→H), and Figure b shows the current when the gate output switches from a high level to a low level (H→H).
The arrow indicates the current when L). The npn transistor, which operates in the opposite direction from H to L, turns on,
When I _po flows, this means that the base current I _ioj supplied from the injector acts as the base current of the npn transistor. The distance to the active base region of is smaller in the case of FIG. 10, the base current is supplied earlier, and the npn transistor turns on faster in the case of FIG. 10 than in the case of FIG. Also, when changing from L to H, the npn transistor is turned off, so IIL is a saturation type logic (however, if Schottky clamp is used, saturation is small). ], and in order for an npn transistor, which is a switching transistor, to go from a deep ON state to an OFF state, the excess charge (holes) accumulated in the active region must be removed from the base terminal. On the other hand, the base current I _ioj from the injector
is always flowing in, and there is a flow flowing out to the base terminal. Therefore, if there is an active base region between the base terminal and the injector as shown in Fig. 10, excess charge will drift to the base terminal and flow through with the flow of I _ioj mentioned above, but as shown in Fig. 9. If there is an active base region apart from the flow of I _ioj , excess charge will only flow by diffusion,
It takes a longer time to remove excess charge than in the case of FIG. 10, and as a result, switching from L to H is also faster in FIG. 10 than in FIG. 9. In other words, it can be seen that the gate operation speed is faster with the injector-collector-based arrangement. However, in the conventional IIL structure, it is difficult to adopt this arrangement when the number of collector outputs increases. This invention has been made in view of the above points, and includes a first base extraction region formed on one side of the collector array of the first NPN transistor at a position equidistant from each position of the collector. A low-resistance conductor layer is formed as an input terminal, and a second transistor is formed on the emitter of a second transistor provided on the other side of the collector arrangement and equidistant from these collectors.
A semiconductor integrated circuit that forms an injector terminal by forming a low-resistance conductor layer, increases operating speed by adopting an injector-collector-base arrangement, and further suppresses variations due to differences in distance between the input terminal and each collector region. The purpose is to obtain equipment. Figures 11a to 11f show an embodiment of this invention IIL/IC.
Figure 1a is a cross-sectional view showing the main stages of the manufacturing process to better understand the basic structure of the
Parts equivalent to ~e are indicated by the same symbols. In this embodiment as well, the steps up to a and b in FIG. 1 in the conventional example are carried out in exactly the same way. After that, p ⁺ which should become the base electrode and injector electrode extraction layer
After opening a window in the oxide film 103 on the shaped layers 9 and 7, a polysilicon film 601 is deposited on the entire upper surface, boron ions are implanted, and annealing is performed. At this time, p ^- layer 6a, p ⁺ type layers 7a, 8a,
9a is formed (FIG. 11a). Next, the polysilicon film 601 is patterned to form a p ⁺ type layer 9.
A portion 601 that extends from above a to the isolation oxide film 102 adjacent thereto, and a portion 6 that extends from the p ⁺ type layer 7a to the isolation oxide film 102 adjacent thereto.
The oxide film 10 is removed at this time, leaving only the oxide film 11.
3, the above-mentioned remaining polysilicon film 60
A thin oxide film 105 is formed over the entire upper surface of the oxide film 105, and then a nitride film 2 is formed over the entire upper surface of the thin oxide film 105.
02 [Fig. 11b]. p ⁺ type layer 7a, 9
A window is formed in the nitride film 202 and oxide film 105 on the p ^- type layer 6a and the emitter electrode extraction region (7a) to be connected to the injector terminal of the constant current circuit and the base electrode to be connected to the input terminal. After forming the extraction area (9a),
Leaving the window opening above the p ^-type layer 6a and masking it with a resist film 302 so as to cover the other window openings, arsenic ions are implanted, and the n ^-type layer 10 to become the collector layer is replaced with the p ^-type layer. 6a [FIG. 11c]. Next, the resist film 302 is removed and annealing is performed to complete the n ⁺ type collector layer 10a of the npn transistor, and the p ^- type layer 6
b and p ⁺ type layers 8b and 9b are completed. Thereafter, a silicide-forming metal film 500 of P _t , P _d , W, M _p, etc. is formed on the entire upper surface and sintering is performed to form a metal silicide film 501 only on the silicon and polysilicon surfaces (FIG. 11d). Next, only the gold film 500 is removed using, for example, aqua regia, and a passivation film 401 (for example, a phosphorus glass film) is deposited thereon, and then a contact window is opened using a required resist mask 303. At this time, an etching solution that does not attack the nitride film is used, and a window larger than the contact hole in the nitride film 202 is opened, and the contact hole is formed from the nitride film 202 (FIG. 11e). Thereafter, the resist mask 303 is removed and the connection wiring 13 is formed using a low resistance metal such as Al or _Au as in the conventional method, thereby completing this embodiment (FIG. 11f). Now, the first advantage of this embodiment is that the collector (output) electrode 13 and the base (input)
The effective distance D _CB to the electrode 12 can be reduced by almost half. That is, in the conventional device, the width of the Al wiring protrudes beyond the width of the contact portion of the electrode, so the distance D _CB cannot be made smaller due to the restriction of the wiring width. In this embodiment, a low resistance polysilicon film 601 and a metal silicide film 5 are used.
Oxide film 1 is used to separate the base electrode wiring using 01 and 01.
Since the metal silicide film 501 is pushed out onto the top of the oxide film 105 and the nitride film 202, there is no restriction as in the conventional device, and the end of the metal silicide film 501 directly contacts the ends of the oxide film 105 and the nitride film 202 at the location indicated by A in FIG. 11f. Since the width remaining after patterning the oxide film 105 and the nitride film 202 becomes substantially the above-mentioned D _CB , its value can be reduced. FIG. 12 shows a plan view of an embodiment of the present invention.
The YY sectional view in FIG. 12 is shown in FIG. 11f, and the Z-
A Z cross-sectional view is shown in FIG. A signal input is supplied from the wiring 12 and is input from the base extraction terminal 9b of the first transistor to the base layer 6b through the first low resistance conductor layer 601 provided in parallel to the collector arrangement of the first transistor. The output is from each collector 10a to wiring 13, 14,
15. The injector input is supplied from wiring 11 and
The second low resistance conductor layer 611 provided parallel to the collector arrangement of the transistors is input to the emitter 7b of the second transistor, and this is input from the collector 8b of the second transistor to the base 6b of the first transistor. By adopting such a configuration, (a) an injector-collector-base arrangement is provided corresponding to each collector of the first transistor, and gate operation can be made faster. (b) through the first and second low resistance conductor layers;
Signal input or injector input is performed simultaneously from positions equidistant from each collector of the transistor, thereby suppressing variations in characteristics due to differences in distance between the input terminal and each collector region. Table 2 shows examples of these uniform characteristics. (c) Since input signals are supplied to each base lead-out terminal 9b using the first low-resistance conductor layer 601, the base area as a wiring path as in the conventional example is unnecessary, and the base area S _B can be reduced. This increased the ratio of collector area S _C /base area _B and increased current amplification factor β _u . Therefore the delay time
t _pdnio becomes smaller and faster.

[Brief explanation of the drawing]

Figures 1a to 1e are cross-sectional views showing the main manufacturing process of conventional IIL-IC, and Figure 2 is a cross-sectional view of the conventional IIL-IC.
The plan view of IIL-IC, Figures 3 and 4, shows the relationship between collector current I _C and current amplification factor β _u of a conventional IIL gate having three collectors C ₁ , C ₂ , and C ₃ and power consumption P Figure 5 shows the _relationship between current amplification factor β _u and minimum delay time t _pdnio , and Figure 6 shows the relationship between _collector and base electrode distance D. Figure 7 is a diagram showing the relationship between _CB and minimum delay time t _pd . Figure 7 is a diagram showing the relationship between collector-base area ratio S _C /S _B and current amplification factor β _u .
The figure shows the minimum delay time depending on the relative position of each terminal.
_Figure 9 is a schematic sectional view to explain the configuration and operation of the injector-base-collector arrangement, and Figure 10 is the configuration of the injector-collector-base arrangement. and a schematic sectional view for explaining its operation, 1st
1A to 1F are cross-sectional views showing the main stages of manufacturing an embodiment of the present invention, FIG. 12 is a plan view of this embodiment, and FIG. 13 is a Z-Z cross-sectional view of FIG. 12. . In the figure, 6b is a base layer, 8b and 9b are base extraction layers, 10a is a collector layer, 11 is an injector terminal, 12 is a base terminal (electrode wiring),
13, 14, 15 are collector terminals (electrode wiring),
21 and 22 are interconnections between logic gate circuit devices; 5
01 is a metal silicide film, and 601 and 611 are polysilicon films. Note that the same reference numerals in the figures indicate the same or corresponding parts.

Claims (1)

[Claims] 1. A second semiconductor substrate formed on a first conductivity type semiconductor substrate.
an emitter formed of a conductivity type high impurity concentration diffusion layer, a second conductivity type low impurity concentration diffusion layer formed on this layer, a base formed on the emitter, and a plurality of emitters formed on the base. a first transistor consisting of a collector; and a collector of the second transistor.
a second transistor having a conductivity type low impurity concentration diffusion layer as a base, an emitter formed thereon, and a collector having the base of the first transistor, and having the base of the first transistor as an input; In a gate circuit in which the collector of the first transistor is an output and the emitter of the second transistor is an injector terminal, a plurality of the first transistors are arranged on one side of the collector arrangement of the first transistor. A first low-resistance conductive layer is formed on the base lead-out regions of the first transistors formed at positions equidistant from respective positions of the collectors, and
The emitters of the transistors are provided on the other side of the collector arrangement of the first transistors, equidistant from the respective positions of the plurality of collectors, and the emitters of the transistors are provided on the other side of the collector arrangement of the first transistors, and a second A semiconductor integrated circuit device characterized by forming a low resistance conductive film.