JPH057135A - Waveform shaping circuit and digital signal analyzer - Google Patents

Abstract

PURPOSE:To apply stable waveform shaping to an inputted digital signal without being affected by its amplitude change or an offset. CONSTITUTION:An inputted digital signal is inputted to an intermediate voltage detection circuit 15 via a level shifter 12. The intermediate voltage detection circuit 15 detects an intermediate voltage V0 between a high level and a low level of the inputted digital signal and outputs the voltage to a subtractor 22 of a control circuit 21. The control circuit 21 outputs a difference signal between the intermediate voltage V0 and the reference voltage Vr to the level shifter 12 via a low pass filter 25 to control the shift of the level shifter 12 in a direction that the intermediate voltage V0 approaches the reference voltage Vr. The digital signal subjected to level shift by the level shifter 12 is inputted to a comparator 20 using the reference voltage Vr as a threshold voltage, in which the signal is subjected to waveform shaping.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a waveform shaping circuit for shaping and outputting an input digital signal, and a digital signal input in synchronization with a clock signal such as a logic analyzer or an error measuring device. The present invention relates to a digital signal analysis device for analysis.

[0002]

2. Description of the Related Art Generally, in a digital signal analyzer such as the logic analyzer or the error measuring device described above, a digital signal input from the outside is shaped by a waveform shaping circuit composed of a comparator. After that, the binary decision is made.

In this type of waveform shaping circuit, it is necessary to set the operating point of the comparator to the best operating point that corresponds to the offset of the input digital signal and is not affected by noise. In order to set this operating point, one of the following three methods has been conventionally performed.

(1) A method of manually setting the threshold level (reference voltage) for the comparator to an optimum state while monitoring the output waveform of the comparator.

(2) A method of eliminating the influence of offset by inputting an input digital signal to a comparator via a capacitor.

(3) A method in which a DC average level of an input digital signal is assumed in advance and is manually changed by a level shifter and input to a comparator.

However, in the methods (1) and (3) described above, manual setting of the operating point is troublesome, and the setting operation must be performed every time the level or offset of the input signal changes.

In the method (2) described above, the digital signal input to the comparator according to the mark ratio (ratio between the total number of generated bits and the number of marks included therein) of the input digital signal. Since the offset voltage of changes, the waveform cannot be reliably shaped with a fixed threshold.

Therefore, a method of inputting the intermediate voltage between the high level voltage and the low level voltage of the input digital signal as a threshold value to the comparator is also conceivable.

However, this method is effective in the case of a relatively low-speed comparator having a wide common-mode input range, but like the comparator for waveform shaping of an ultrahigh-frequency (several GHz) signal, the common-mode input range is If it is extremely narrow,
There is a problem that the comparator itself is saturated due to the change in the offset voltage of the input signal, and the normal waveform shaping operation cannot be performed.

On the other hand, a digital signal analyzer for performing binary judgment of a waveform-shaped digital signal and analyzing the digital data has been conventionally constructed as shown in FIG.

That is, the measured data signal input to one input terminal 1 is the reference voltage Vr from the reference voltage generator 2.
The waveform is shaped by the comparator 3 whose threshold value is. Since this reference voltage Vr is set to the best value in advance by any of the methods described above, the fluctuation component in the amplitude direction of the measured data signal shown in (a) of FIG. 18 is (b) of FIG. The waveform is shaped as shown in (4) and is input to the data input terminal D of the discriminator 4 formed of a D-type flip-flop.

The clock signal input to the other input terminal 5 is also input to the clock terminal CP of the discriminator 4 via the variable delay unit 6.

The variable delay unit 6 is adjusted in advance so that the clock signal rises at the timing when the binary level of the data signal input to the discriminator 4 is most stable.

As this adjustment, the output signal of the comparator 3 shown in FIG. 18B and the clock signal shown in FIG. 18C are displayed on a two-phenomenon oscilloscope, and the rising timing of the clock signal is Almost halfway point between digital signal state transition points I and II (point with the largest phase margin)
Conventionally, a method of manually adjusting the delay amount of the variable delay unit 6 so that the variable delay unit 6 is located in the position is set.

In this manner, the digital signal from the comparator 3 is binary-identified at the rising timing of the clock signal input to the discriminator 4, and its determination output is input to the data analysis unit 7 together with the clock signal. Then, predetermined data analysis is performed.

However, in the conventional digital signal analysis apparatus having such a configuration, in addition to the manual adjustment of the above-mentioned waveform shaping circuit, the delay amount must be manually adjusted, and these differences may occur depending on the operator's individual difference. There is a problem that the set amount is likely to be different and the analysis result is also different.

Further, when observing a waveform with an oscilloscope for adjustment, not only is the connection between the devices complicated, but the oscilloscope connection also disturbs the signal waveform,
It may cause malfunction. In particular, as described above, when connecting a cable for waveform observation to an ultrahigh frequency (several GHz) signal, the waveform is greatly disturbed and it becomes difficult to perform accurate adjustment.

For this reason, there is a method of providing a monitor terminal for observing a waveform in the digital signal analysis device, but it is still inconvenient since the waveform observing equipment such as an oscilloscope must be always prepared. there were.

An object of the present invention is to provide a waveform shaping circuit and a digital signal analysis device which solve the above-mentioned problems.

[0021]

In order to solve the above problems, the waveform shaping circuit of the present invention includes a level shifter (12) for variably controlling a DC offset voltage of an input digital signal, and an output from the level shifter. A comparator (20) that compares the digital signal with a predetermined reference voltage and shapes and outputs the waveform, and detects and outputs an intermediate voltage between the high level voltage and the low level voltage of the digital signal output from the level shifter. The intermediate voltage detecting means (15), the intermediate voltage outputted from the intermediate voltage detecting means and the predetermined reference voltage, and the DC offset for equalizing the intermediate voltage with the predetermined reference voltage. And a control means (21) for outputting a control signal for changing the voltage to the level shifter.

The digital signal analyzer of the present invention compares the level shifter (52) for variably controlling the DC offset voltage of the input digital signal with the digital signal output from the level shifter, and compares it with a predetermined reference voltage. A comparator (60) for waveform shaping and output, an intermediate voltage detection circuit (55) for detecting and outputting an intermediate voltage between the high level voltage and the low level voltage of the digital signal output from the level shifter, and the intermediate Receiving the intermediate voltage output from the voltage detection circuit and the predetermined reference voltage, outputting a control signal for changing the DC offset voltage to the level shifter in order to make the intermediate voltage equal to the predetermined reference voltage. First control means (6
1) and a variable delay device (7) for relatively varying the phase between the input clock signal and the output of the comparator.
1) and the output of the comparator, the phase of which is relatively changed by the variable delay device, and the clock signal, and the sign of the output signal of the comparator at the rising or falling of the clock signal is determined. A discriminator (72), an error measuring device (75) for comparing the judgment signal from the discriminator with a reference signal corresponding to the input digital signal, and outputting an error signal, and In response to the output, a delay amount that is adjacent to each other and is approximately in the middle of the delay amount at which the error signal has the maximum value is detected, and the intermediate delay amount is sent to the variable delay device and output by the error measuring device. And a second control means (80) for reducing the error signal.

[0023]

With this configuration, in the waveform shaping circuit of the present invention, the input digital signal is input to the comparator via the level shifter and shaped by the predetermined reference voltage. Further, an intermediate voltage between the high level voltage and the low level voltage of the digital signal output from the level shifter is detected by the intermediate voltage detecting means and output to the control means together with the reference voltage. The control means outputs a control signal for making the intermediate voltage equal to the reference voltage to the level shifter to vary the DC offset voltage of the input digital signal.

Further, in the digital signal analyzing apparatus of the present invention, the output signal of the comparator and the clock signal input from the input terminal, which are waveform-shaped by the waveform shaping circuit having the same configuration as the waveform shaping circuit of the above-mentioned invention, are in between. The phase is changed by the variable delay device and input to the discriminator.
The decision signal from the discriminator is compared with the reference signal corresponding to the input digital signal by the error measuring device.
The error signal detected by the error measuring device is input to the second control means. The second control means, while receiving the error signal from the error measuring device, varies the delay amount of the variable delay device to detect an almost intermediate delay amount of the delay amounts which are adjacent to each other and maximize the error signal, Output to variable delay device.

[0025]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a waveform shaping circuit 10 of the first embodiment.
3 is a circuit diagram showing the configuration of FIG.

In FIG. 1, the input digital signal input to the terminal 11 is terminated by the input resistor R ₀ (for example, 50Ω) and input to the level shifter 12.

The level shifter 12 varies the average direct current (offset) voltage level of the input digital signal according to the magnitude of an error signal (control signal) Ve from the control circuit 21 described later. To this end, the level shifter 12 is configured, for example, as shown in FIG.

That is, the average DC voltage of the input digital signal is detected by the integrating circuit composed of the resistor R ₁ and the capacitor C ₁ and input to the adder 13. The adder 13 adds the error signal Ve to this average DC voltage, and outputs the added voltage via the resistor R ₂ . A capacitor C ₂ is provided between the resistor R ₂ and the terminal 11 to pass only the AC component of the input digital signal. Therefore, from the connection point between the capacitor C ₂ and the resistor R ₂ , a signal obtained by adding the output voltage from the adder 13 to the AC component of the input digital signal, that is, the error voltage Ve with respect to the input digital signal.
A signal whose level has been shifted is output.

The resistors R ₁ and R ₂ have a high resistance value of about several tens KΩ which does not affect the transmission impedance of 50Ω.

The output of the level shifter 12 is input to the intermediate voltage detection circuit 15 and a comparator 20 described later, as shown in FIG.

The intermediate voltage detection circuit 15 includes the level shifter 1
Maximum value detection circuit 16 for detecting the maximum voltage of the output signal of 2
And a minimum value detection circuit 17 for detecting the minimum voltage of the output signal of the level shifter 12 and an intermediate voltage between the output voltages of the detection circuits 16 and 17 and two resistors R _{3 of} the same resistance value connected in series with each other. , R ₄ is formed by the intermediate voltage output circuit 18 which outputs the voltage from the connection point.

The comparator 20 has one input terminal IN
The level of the output signal of the level shifter 12 input to
When it is higher than a predetermined reference voltage (hereinafter also referred to as threshold voltage) Vr applied to the other input terminal REF, a high level digital signal is output, and when it is lower, a low level digital signal is output. The comparator 20 is composed of a semiconductor element for ultra high frequency (for example, gallium-arsenic type FET) or the like.

The intermediate voltage Vo output from the intermediate voltage detection circuit 15 and the threshold voltage Vr are input to the control circuit 21 which is the control means of the waveform shaping circuit 10.
The control circuit 21 detects the difference between the input intermediate voltage Vo and the threshold voltage Vr by the subtractor 22 and outputs the difference voltage signal via the low pass filter 23 to the level shifter 1.
2 to control the shift amount of the level shifter 12 in the direction in which the intermediate voltage Vo matches the threshold voltage Vr.

FIG. 3 shows an example of more specific circuits of the intermediate voltage detection circuit 15 and the control circuit 21.

That is, the maximum value detection circuit 16 includes a diode 16 whose anode side is connected to the output of the level shifter 12.
a and a peak detector circuit in the positive direction formed by a capacitor 16b connected between the cathode of the diode 16a and the ground, and a connection point between the diode 16a and the capacitor 16b and a predetermined negative power source -V ₁ . A constant current source 16c for supplying a minute forward bias current to the diode 16a is connected between the two.

Further, the minimum value detection circuit 17 includes a diode 17 whose cathode side is connected to the output of the level shifter 12.
a and a negative peak detector circuit formed by a capacitor 17b connected between the anode side of the diode 17a and ground.
A constant current source 17c for flowing a minute forward bias current to the diode 17a is connected between the connection point with 7b and a predetermined positive power source + V ₁ .

[0038] Therefore, from the connection point between the diode 16a and the capacitor 16b of the peak value detector 16, of the digital signal output from the level shifter 12, or the negative power source -V ₁ voltage of a high level voltage is output, the minimum Diode 17a and capacitor 17b of the value detection circuit 17
A low-level voltage equal to or lower than the positive power supply + V ₁ voltage is output from the connection point with.

The forward bias currents from the constant current sources 16c and 17c for the diodes 16a and 17a have almost no effect on the input digital signal, and the nonlinearity of the detection operation of the diodes 16a and 17a is compensated. It is set to a current value of about 1 μA required for the operation.

The capacitance value of the capacitors 16c and 17c is about 1000 PF which can hold the peak value of the digital signal with a repetition period of 1 KHz or more, considering that the forward bias current to the diodes 16a and 17a is about 1 μA. Is set to the value of.

The subtractor 22 of the control circuit 21 is formed by a differential amplifier 22a and a feedback resistor 22b, and has an intermediate voltage V
A voltage corresponding to the difference between o and the threshold voltage Vr is output from the differential amplifier 22a. Resistor 23a and capacitor 23b
The low-pass filter 23 formed by
The error signal Ve from which the noise component is removed from the output of a is output to the level shifter 12.

Therefore, when the intermediate voltage Vo decreases with respect to the threshold voltage Vr, the output voltage of the differential amplifier 22a increases, so that the error signal Ve increases and the level of the digital signal output from the level shifter 12 increases. Rises overall. Conversely, when the intermediate voltage Vo rises with respect to the threshold voltage Vr, the output voltage of the differential amplifier 22a drops, so the error signal Ve drops and the level of the digital signal output from the level shifter drops overall. Will be done.

Next, the operation of the above waveform shaping circuit 10 will be described.

Now, temporarily, at time t ₀ , the level shifter 12
The intermediate value between the maximum value and the minimum value of the digital signal input to the comparator 20 is set as shown in FIG.
Is equal to the threshold voltage Vr.

In this case, since the output of the subtractor 22 of the control circuit 21 becomes zero, the digital signal input to the level shifter 12 is input to the comparator 20 as it is,
The waveform is shaped by the threshold voltage Vr.

At time t ₁ , it is assumed that the DC offset voltage of the input digital signal rises stepwise as shown in FIG. In response to this, the output signal of the level shifter 12 also rises and changes as shown in FIG.
6. The output voltage of the minimum value detection circuit 17 is also shown in FIG.
It changes stepwise as shown in FIG.

Therefore, the intermediate voltage Vo to the subtractor 22 is
Also changes stepwise as shown in (e) of the figure, and the output of the subtractor 22 largely changes in the negative direction as shown in (f) of the figure.

Therefore, the low-pass filter 23 outputs the error signal Ve which drops at a speed according to the time constant, as shown in FIG.

Therefore, the shift amount of the level shifter 12 also gradually increases to the negative side, so that the intermediate value of the digital signal input to the comparator 20 is the threshold voltage Vr as shown in FIG. Changes to match the direction.

As a result, at time t ₂ , the subtractor 2
The difference between the two input voltages becomes almost zero, and thereafter, this stable state is continued, and the waveform-shaped digital signal is reliably obtained from the output of the comparator 20.

After that, even if the offset of the input digital signal changes, the intermediate voltage of the digital signal input to the comparator is always feedback-controlled toward the threshold voltage Vr, so that a reliable waveform shaping operation can be performed. Will continue to be stable.

[0052]

[Second Embodiment] In the first embodiment, the control loop for controlling the shift amount of the level shifter 12 is always closed, but the shift amount for the input digital signal becomes a stable and proper amount. After that, the shift amount may be held to open the loop, and the detection operation of the intermediate voltage detection circuit 15 connected to the signal line may be stopped.

FIG. 5 shows the configuration of the hold type waveform shaping circuit 10 'of the second embodiment. The waveform shaping circuit 10 'receives a hold signal (stop signal) and holds the magnitude of the error signal, and a maximum value detection circuit 1 closed by the hold signal (stop signal).
6. It has switches 26 and 27 (stopping means) for applying a reverse bias voltage ± V ₂ to the diodes 16a and 17a of the minimum value detection circuit 17.

The waveform shaping circuit 10 'thus constructed
Then, when the hold signal (stop signal) is input after the shift amount of the level shifter 12 with respect to the input digital signal becomes an appropriate amount by the loop control similar to the above, the value of the error signal Ve giving the appropriate shift amount is the hold circuit. It is held at 25, and the shift amount of the level shifter 12 is fixed to an appropriate amount. Further, at this time, the diodes 16a, 1 of the both detection circuits 16, 17 of the intermediate voltage detection circuit 15 are
Since 7a is electrically separated from the digital signal line by the reverse bias voltage, it is possible to prevent the diode connection from adversely affecting this line (deterioration of high frequency characteristics).

In the waveform shaping circuit 10 'shown in FIG. 5, the reverse bias voltage ± V _{2 is} applied by the hold signal.
The case where the voltage is simply applied to the maximum value detection circuit 16 and the minimum value detection circuit 17 has been described. However, as in the intermediate voltage detection circuit 15 shown in FIG.
When a small amount of forward current is applied to a by the constant current sources 16c and 17c, switching between the constant current source and the reverse bias voltage ± V ₂ may be performed by a hold signal.

FIG. 6 shows a specific circuit configuration of the stop circuit 29 for stopping the detection operation of the intermediate voltage detection circuit 15 by switching the constant current sources 16c and 17c and the reverse bias voltage ± V ₂ . .

The stop circuit 29 receives the above-mentioned hold signal as a stop signal and switches the switches 26 'and 27' from the normal mode to the hold / limiter mode. In the normal mode, the diodes 16a and 17 are
Similarly to the above, a small forward bias current is supplied to a from the constant current sources 16c and 17c, so that the intermediate voltage detection circuit 15 detects the maximum value and the minimum value of the digital signal from the level shifter 12.

In the hold mode, it is sufficiently larger than the maximum and minimum values of the input digital signal (for example, 4
Reverse bias voltage ± V ₂ is applied to diode 16
a, 17a, the intermediate voltage detection circuit 15
Stops the operation of detecting the maximum value and the minimum value.

In the limiter mode, the diode 1
Since a reverse bias voltage ± V _{2 of} about 1.3 V in consideration of the forward voltage drop of 6 a and 17 a of 0.7 V is applied to the diodes 16 a and 17 a, the limiter is set to about ± 2 V with respect to the input digital signal. You can call.

As described above, in the circuit of FIG. 6, the voltage set as the reverse bias voltage ± V ₂ is variably controlled to be 4 V or 1.3 V depending on the state at that time. Both the hold mode and the limiter mode can be switched and used together with the normal mode described above. In FIG. 6, reference numerals 16d and 1
Reference numerals 7d are buffer amplifiers.

Further, if the stop circuit 29 is constructed as shown in FIG. 7, the diodes 16a and 17a can be operated as the limiter in both the normal mode and the hold mode.

In the stop circuit 29 shown in FIG. 7, the reverse bias voltage ± V _{3 of} about 0.6 V is always applied to the diodes 16a and 17a through the diodes 30 and 31. In addition, the switch 2 on the maximum value detection circuit 16 side
The constant current source 17c on the minimum value detection circuit 17 side is connected to the hold side of 6 ', and the constant current source 16c on the maximum value detection circuit 16 side is connected to the hold side of the switch 27' on the minimum value detection circuit 17 side. Are connected.

Therefore, in the normal mode, the diodes 16a and 17a have their respective constant current sources 16c,
The forward bias from 17c is applied to detect the maximum and minimum values of the input digital signal, as in the case of the circuit of FIG.

However, in this normal mode,
When the output voltage from the level shifter 12 becomes lower than -2V, the diode 17a and the diode 31 of the minimum value detection circuit 17 become conductive, so that the minimum value detection circuit 17 side has-.
Limiter will can take at 2V (-V ₃ -1.4V).

In the normal mode, when the output voltage from the level shifter 12 becomes higher than + 2V, the diode 16a and the diode 30 on the maximum value detection circuit 16 side become conductive, and the maximum value detection circuit 16 side is + 2V.
The limiter will be applied at (+ V ₃ + 1.4V).

In the above description, -1.4V is the voltage drop in the diodes 17a and 31, and + 1.4V is the voltage drop in the diodes 16a and 30.

In the hold mode, the diodes 16a and 17a are the constant current sources 17c and 16 respectively.
The reverse bias from the c side stops the maximum value / minimum value detection operation for the input digital signal.

However, in this hold mode,
If ± V ₁ = ± 1.3V is set, when the output voltage from the level shifter 12 becomes lower than −2V or higher than + 2V, it is −2V or + 2V as in the normal mode. The limiter is applied.

As the hold circuit 25 shown in FIGS. 5, 6, and 7, a digital hold circuit can be used as shown in FIG. 8 in addition to the analog hold circuit.

The hold circuit 25 shown in FIG. 8 converts the error signal Ve from the control circuit 21 into a digital value by the A / D converter 32, and converts the digital value when the hold signal (switching signal) is input. It is stored in the memory circuit 33. The digital value stored in the memory circuit 33 is converted into an analog voltage by the D / A converter 34, and the switch 35
Is output to the level shifter 12 via.

The switch circuit 35 outputs the error signal from the control circuit 21 as it is to the level shifter 12 when the hold signal is not input, and the signal from the D / A converter 34 when the hold signal is input. Is output. Since such a digital type hold circuit does not change the hold output as compared with the analog type hold circuit, it is advantageous when a long-time hold operation is required.

Further, in the above description, the subtractor 22 and the low-pass filter 23 were separately configured as specific circuits of the control circuit 21, but as shown in FIG.
It is also possible to simplify the control circuit by using an integral type circuit in which the output of 1a is fed back by the capacitor 21b.

In the above embodiment, if it is desired to know the shift amount in the level shifter 12, the error signal V
Read the size of e with a voltmeter, or as shown in FIG.
If the voltmeter 37 reads the difference in average DC voltage between the input and output of the level shifter 12 detected by the integrating circuit of the resistor R ₅ and the capacitor C ₅ , the level shifter 12
The shift amount of can be known. Also, the threshold level of the input digital signal can be known from this level shift amount. When the digital hold circuit 25 shown in FIG. 8 is used, since the shift amount in the level shifter 12 can be detected by the A / D converter 32, the circuit shown in FIG. 10 is unnecessary.

Further, although the above-mentioned embodiment has explained the waveform shaping circuit used at an ultra high frequency, the waveform shaping circuit of the present invention can be applied to a waveform shaping circuit of a low frequency band.

Further, as the comparator, not only the one composed of the gallium-arsenic type FET of the above-mentioned embodiment but also a comparator composed of, for example, a silicon bipolar transistor or a hetero bipolar transistor (HBT) may be used. . Further, as the level shifter, in addition to the configuration of the above embodiment, various types such as a level shifter composed of a DC blocking capacitor and a high frequency blocking coil can be used.

[0076]

[Third Embodiment] Next, a digital signal analyzing apparatus using the above waveform shaping circuit will be described.

FIG. 11 is a block diagram showing the configuration of the third embodiment of the digital signal analyzing apparatus of the present invention applied to an error measuring apparatus.

This error measuring device waveform-shapes the measured data signal input together with the clock signal, and then discriminates the binary judgment at the timing synchronized with the inputted clock signal, and inputs the discriminated signal. It is configured to compare with the data of the reference signal corresponding to the digital signal.

The measured data signal is input to the waveform shaping circuit 50 having the same structure as the waveform shaping circuit 10 of FIG.

That is, the measured data signal inputted from the input terminal 51 is terminated by the input resistance R ₀ (for example, 50Ω) and inputted to the level shifter 52. Level shifter 52
Changes the DC average (offset) voltage of the input measured data signal according to the magnitude of the error signal Ve.

The output of the level shifter 52 is input to the intermediate voltage detection circuit 55 and the comparator 60. The intermediate voltage detection circuit 55 detects the high-level peak voltage and the low-level peak voltage of the digital signal output from the level shifter 52 from the high-level peak detection circuit (maximum value detection circuit) 56 and the low-level peak detection circuit (minimum value). Each of them is detected by a detection circuit) 57, and an intermediate voltage Vo is output from the middle point of two equal resistors R.

The intermediate voltage Vo is applied to the reference voltage generator 5
The reference voltage (threshold voltage) Vr from 9 is input to the first control circuit 61.

First control circuit 61 which is the first control means
Is a subtraction circuit 62 that detects a difference between the reference voltage Vr and an intermediate voltage Vo, and a low-pass filter (hereinafter, LP) that outputs an error signal Ve obtained by integrating the subtraction output of the subtraction circuit 62.
(Referred to as F) 63, and the shift amount of the level shifter 52 is feedback-controlled so that the intermediate voltage Vo always approaches the reference voltage Vr.

The comparator 60 outputs a high level digital signal when the digital signal output from the level shifter 52 is higher than the reference voltage Vr, and outputs a low level digital signal when the voltage is lower than the reference voltage Vr to shape the waveform of the input digital signal.

As described above, the configuration described above is exactly the same as that of the waveform shaping circuit 10 shown in FIG. 1, and the details and modified examples of each part are based on the above description.

On the other hand, the clock signal input to the input terminal 70 is input to the discriminator 72 and the error measuring section 75 which is an error measuring device via the variable delay unit 71. The variable delay unit 71 delays the input clock signal according to the control signal and relatively changes the phase of the clock signal with respect to the measured data signal. As the variable delay device 71,
A variable-length slab line structure having a variable delay amount by varying the signal line length is used for ultra-high frequencies.

The discriminator 72 binary-determines the level of the digital signal output from the comparator 60 at the rising (or falling) timing of the clock signal input from the variable delay unit 71, and the discriminating output is It is output to the error measuring unit 75.

The error measuring section 75, which is the data analyzing section of the error measuring apparatus according to this embodiment, includes a reference data generator 76,
It is composed of a sign comparator 77, a mismatch counter 78, and a clock counter 79.

The reference data generator 76 receives the reference data having the same pattern as the data to be measured from the variable delay unit 7.
The signal is output to the code comparator 77 at a timing synchronized with the clock signal from 1.

The code comparator 77 determines whether or not the codes of the output of the discriminator 72 and the reference data match, and when they do not match, outputs a mismatch signal to the mismatch counter 78.

The disagreement counter 78 is provided in the control unit 8 which will be described later.
While receiving the gate signal from 0, the counting of the mismatch signal is continuously performed. The clock counter 79 has a control unit 8
While receiving the gate signal from 0, the clock signal output from the variable delay unit 71 is counted.

The control section 80 which is the second control means of this error measuring apparatus is composed of a microprocessor (CPU) or the like and mainly has two processing modes.

That is, in the first processing mode, the mismatch counter 78 and the clock counter 79 are simultaneously counted for a predetermined time, the count results of both counters are read, the code error rate is calculated, and the result is displayed on the display. This is a normal measurement process displayed on 81. In the second processing mode, before the measurement processing, the delay amount of the variable delay unit 71 with respect to the clock signal is continuously varied within a predetermined range to obtain error rate data corresponding to the delay amount and stored in the memory 80a. This is the optimum delay amount detection processing for detecting the delay amount that minimizes the error rate.

The A / D converter 65 shown in FIG. 11 has an error signal V from the first control circuit 61 of the waveform shaping circuit 50.
e is converted to a digital value, and this value is converted to the level shifter 52.
Is output to the control unit 80. Control unit 80
Stores this shift amount in the memory 80a or displays it on the display 81.

Next, the operation of this error measuring apparatus will be described.

When the measured data signal and the clock signal are input to the input terminals 51 and 70, the waveform shaping circuit 50 refers to the intermediate voltage Vo between the high level and the low level of the input measured data signal. The shift amount is controlled so as to match the voltage Vr.

This operation is exactly the same as the operation described with reference to FIG.

Therefore, from the comparator 60, as shown in FIG.
As shown in (a) of 2, the threshold voltage (reference voltage) V
The waveform is shaped by r, and the measured data signal having no fluctuation in the amplitude direction is output.

The fact that the shift amount of the level shifter 52 is stable means that the shift amount from the A / D converter 65 is displayed on the display 81 or the stability judgment processing is performed by the control unit 80 itself. You can check.

Next, the control unit 80 performs the above-mentioned optimum delay amount detection processing.

That is, the control unit 80 inputs the gate signal to the clock counter 79 for a predetermined time and then obtains the period T of the clock signal from the counting result. Then, as shown in (b ₁ ), (b ₂ ), and (b ₃ ) of FIG. 12, the delay amount of the variable delay unit 71 is changed from the initial value D ₀ to at least one cycle of the clock signal at a predetermined step d. While varying, the error rate is calculated for each predetermined step, and the result is stored in the memory 80a.
Remember.

FIG. 12C shows the change in the error rate with respect to the change in the delay amount stored in the memory 80a.
As is clear from this figure, for the output signal ((a) in the figure) of the comparator 60 having fluctuations in the phase component, the rise of the clock signal from (b ₁ ) to (b ₃ ) in the figure The change in the error rate when the timing is changed by 1.5 cycles becomes the maximum at the state transition point of the output signal of the comparator 60, and the maximum points are obtained at two points.

Based on the stored error rate data, the control section 80, for example, delays D ₂ and D ₆ that maximize the error rate.
The intermediate value D ₄ is automatically set in the variable delay unit 71 as the optimum delay amount with the largest phase margin.

After making the above settings, the control unit 80
Normal error measurement processing is performed, and the measured error rate is sequentially displayed on the display 81.

The level shift amount from the A / D converter 65 and the threshold level of the measured data signal calculated from the level shift amount and the reference voltage Vr to the comparator 60 are also displayed on the display 81 at any time. .

Further, in the error measuring device of the third embodiment, the subtraction result of the intermediate voltage and the reference voltage is inputted to the level shifter 52 via the LPF 63. However, as shown in FIG. The result is digitally converted into subtraction data by the A / D converter 65, the shift amount for the subtraction data to approach zero is calculated by the arithmetic control unit 90, and the calculated shift amount data is D / A converter. It may be configured to control the shift amount of the level shifter 52 by sending it to the control unit 66. In addition, the arithmetic control unit 90 includes a control unit 80.
In addition, it is configured as one CPU.

Further, the intermediate voltage output from the intermediate voltage detection circuit 55 is directly A / D converted, and the arithmetic control unit 90
Alternatively, the arithmetic control unit 90 may compare the intermediate voltage data with the reference voltage data and output shift amount data corresponding to the difference to the level shifter 52 via the D / A converter 65. It is possible. In this case, the arithmetic control unit 90 serves as the first control means.

Further, in the third embodiment, in order to set the optimum delay amount for the clock signal, from the maximum value of the error rate obtained by varying the delay amount for one cycle or more of the clock signal, Although the optimum value is determined, the delay amount at which the error rate becomes the minimum value may be set as it is as the optimum value. This is an effective method when the phase fluctuation of the input / output signal is large and the flat portion between D ₃ and D ₅ in FIG. 12C is extremely narrow.

Further, two delay amounts which give equal error rates instead of the maximum error rate as in the above embodiment (for example, FIG. 1).
The intermediate value of D ₃ and D ₅ ) of 2 may be set as the optimum delay amount.

By operating an input means such as a switch provided on the display, a series of operations for setting the optimum threshold voltage of the data signal under measurement is started, and after the operation is completed, the optimum delay amount is set. May be performed, and the set threshold level and delay amount may be displayed on the display.

Although the phase on the clock signal side is delayed in the third embodiment, this does not limit the present invention. For example, as shown in FIG. It may be provided between the input terminal 51 on the measured data signal side and the level shifter 52. Further, the variable delay unit 71 is provided between the level shifter 52 and the comparator 60, or
It may be provided between the comparator 60 and the discriminator 72.

Further, in the third embodiment, the waveform shaping circuit 50 having the same configuration as the waveform shaping circuit 10 shown in FIG. 1 shaped the waveform of the input signal. The waveform shaping circuit 10 'of the second embodiment (FIG. 5) having the function of stopping the operation of the voltage detection circuit 55 may be used. Similarly, the circuit having the limiter function shown in FIGS. 6 and 7 as a modification of FIG. 5 may be used.

Further, the circuit shown in FIG.
5 may be modified to form the digital type hold circuit described in FIG.

With this configuration, the arithmetic control unit 90 itself determines that the loop of the waveform shaping circuit 50 has reached the optimum shift amount, and outputs the hold signal (stop signal) to the switch circuit 35 and the stop circuit. Then, the optimum shift amount is fixedly set to the level shifter 52, and the detection operation of the intermediate voltage detection circuit 55 is stopped (the stop circuit 69 has the same configuration as the stop circuit 29 described above).

As described above, the arithmetic control unit 90 for controlling the setting of the optimum shift amount to the level shifter 52 and the control for stopping the intermediate voltage detection operation, and the control unit for controlling the setting of the optimum delay amount for the variable delay unit 71. By configuring 80 and one CPU, the optimum shift amount setting process and the optimum delay amount setting process for the measured data signal can be continuously performed by a series of programs by a simple key operation or the like. Further, there is an advantage that data can be exchanged with other devices easily by using the communication function of the CPU.

FIG. 16 shows a more specific example of the error measuring apparatus according to the third embodiment of the present invention. In particular, it is an example of an apparatus for performing error measurement of a data signal under measurement at an ultrahigh frequency.

In FIG. 16, the input data applied to the waveform shaping circuit 101 and the input clock applied to the variable delay device 102 are optimized as described above and output to the discriminator 103.

The data discriminated as described above by the discriminator 103 is fed to the 1 / N demultiplexer 104 by the 1 / N clock generated from the timing generator 105 based on the output clock of the variable delay unit 102. Demultiplexed to 1 / N. For example, when the input data is 10 GHz and N = 32, the input data is 3
The signal is demultiplexed to 10 MHz and error detection is performed by the error detection unit 106 as 32-channel data. This error result is displayed on the display unit 1 via the error counting unit 107.
08 and the synchronization control unit 109. The reference pattern generation unit 110 generates reference pattern data to be given to the error detection unit 106 according to the output from the synchronization control unit 109.

The error detection unit 106, the reference pattern generation unit 110, the error counting unit 107, and the synchronization control unit 10
9 is controlled by the 1 / N clock from the timing generator 105. A control unit 111 including a CPU controls each unit. Under the control of the control unit 111, the auto-search unit 112 controls the waveform shaping circuit 101 and the variable delay unit 102 to be in appropriate states, as in the above-described embodiments.

In this error measuring device, the data signal identified by the discriminator 103 at the optimum timing is divided into parallel data at a speed of 1 / N for error determination as in the above-described embodiment, and therefore, the ultra high frequency The error measurement of the data signal can be surely performed.

Although the above embodiment has been described with respect to an example in which the digital signal analyzing apparatus of the present invention is applied to an error measuring apparatus, it can be similarly applied to other digital analyzing apparatuses such as a logic analyzer.

[0122]

As described above, the waveform shaping circuit of the present invention determines the DC offset voltage of the input digital signal, that is, the intermediate voltage between the high level voltage and the low level voltage of the output signal of the level shifter. The shift amount of the level shifter is controlled so as to approach the threshold value, and the output signal of the level shifter is shaped into a waveform with a predetermined threshold value.

For this reason, the center of the amplitude of the digital signal input to the comparator is always made to coincide with a predetermined threshold value without any troublesome waveform observation or manual adjustment, and a reliable waveform is obtained. Can be shaped.

Further, in the waveform shaping circuit provided with the holding circuit for holding the magnitude of the error signal for the level shifter and the stopping means for stopping the operation of the intermediate voltage detecting circuit, the shift amount can be fixed to an appropriate amount. There is an effect that it is not necessary to deteriorate the high frequency characteristics of the signal path.

Further, as described above, the digital signal analyzing apparatus of the present invention is an error obtained by relatively varying the phase of the digital signal output from the waveform shaping circuit and the clock signal by a predetermined range. Based on the measurement result,
Configured to detect the delay amount for the identification timing to enter the optimum position between the adjacent state transition points of the digital signal input from the comparator to the discriminator, and set the delay amount in the variable delay device. Has been done.

For this reason, the operation point and the identification timing of the waveform shaping by the comparator can be determined without any error or individual difference due to the waveform disturbance without performing the complicated manual voltage adjustment and phase adjustment operation while observing the waveform. The optimum state can be set.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a first exemplary embodiment of the present invention.

FIG. 2 is a circuit diagram showing an example of a specific circuit of a main part of FIG.

3 is a circuit diagram showing an example of a specific circuit of a main part of FIG.

FIG. 4 is a signal diagram for explaining the operation of the embodiment.

FIG. 5 is a block diagram showing a configuration of a second exemplary embodiment of the present invention.

FIG. 6 is a circuit diagram showing a modified example of the main part of the second embodiment.

FIG. 7 is a circuit diagram showing a modified example of the main part of the second embodiment.

FIG. 8 is a circuit diagram showing a modified example of the main part of the second embodiment.

FIG. 9 is a circuit diagram showing a modified example of a main part of the first and second embodiments.

FIG. 10 is a circuit diagram for directly reading a shift amount.

FIG. 11 is a block diagram showing a configuration of a third exemplary embodiment of the present invention.

FIG. 12 is a diagram for explaining the operation of the third embodiment.

FIG. 13 is a principal block diagram showing a modification of the third embodiment.

FIG. 14 is a block diagram showing another modification of the third embodiment.

FIG. 15 is a block diagram showing another modification of the third embodiment.

FIG. 16 is a block diagram more specifically showing a main part of the third embodiment.

FIG. 17 is a block diagram showing a configuration of a conventional device.

FIG. 18 is a signal diagram for explaining the operation of the conventional device.

[Explanation of symbols]

10, 10 'waveform shaping circuit 12 level shifter 15 Intermediate voltage detection circuit 16 Maximum value detection circuit 17 Minimum value detection circuit 18 Intermediate voltage output circuit 20 comparator 21 Control circuit 22 Subtractor 23 Low pass filter 25 hold circuit 26, 27 switch 29 Stop circuit 32 A / D converter 33 memory circuit 34 D / A converter 35 switch 37 Voltmeter 50 waveform shaping circuit 52 level shifter 55 Intermediate voltage detection circuit 60 comparator 61 First Control Circuit 65 A / D converter 71 Variable delay device 72 discriminator 75 Error measuring section 76 Reference data generator 77 sign comparator 78 Mismatch counter 79 clock counter 80 Control unit 81 Display 90 Arithmetic control unit 101 Wave shaping circuit 102 Variable delay device 103 discriminator 104 1 / N demultiplexer 105 Timing generator 106 error detector 107 error counter 108 display 109 Synchronous control unit 110 Reference pattern generator 111 CPU 112 Auto Search Section

Claims (3)

[Claims] 1. A level shifter (12) for variably controlling a DC offset voltage of an input digital signal, and a comparator (2) for comparing a digital signal output from the level shifter with a predetermined reference voltage and shaping and outputting the waveform.
0), an intermediate voltage detecting means (15) for detecting and outputting an intermediate voltage between the high level voltage and the low level voltage of the digital signal output from the level shifter, and an intermediate voltage output from the intermediate voltage detecting means. And a predetermined reference voltage, the control means (21) for outputting to the level shifter a control signal for changing the DC offset voltage so as to make the intermediate voltage equal to the predetermined reference voltage. Waveform shaping circuit equipped. 2. A holding means (25) for holding the control signal output from the control means, and a stopping means for stopping the operation of the intermediate voltage detecting means when the control signal is held by the holding means. The waveform shaping circuit according to the first aspect, including (26) and (27). 3. A level shifter (52) for variably controlling a DC offset voltage of an input digital signal, and a comparator (6) for comparing the digital signal output from the level shifter with a predetermined reference voltage and shaping the waveform to output.
0), an intermediate voltage detection circuit (55) for detecting and outputting an intermediate voltage between a high level voltage and a low level voltage of the digital signal output from the level shifter, and an intermediate voltage output circuit from the intermediate voltage detection circuit. First control means (61) which outputs a control signal for changing the DC offset voltage to the level shifter so as to make the intermediate voltage equal to the predetermined reference voltage. ), A variable delay device (71) for relatively varying the phase between the input clock signal and the output of the comparator, and the output of the comparator whose phase is relatively varied by the variable delay device. A discriminator (72) that receives the clock signal and the clock signal and determines the sign of the output signal of the comparator when the clock signal rises or falls; An error measuring device (75) which compares the judgment signal from the discriminator with the reference signal corresponding to the input digital signal and outputs an error signal, and an error measuring device (75) which receives the output of the error measuring device and is adjacent to each other. A second delay amount that detects a delay amount approximately in the middle of the delay amount at which the signal reaches its maximum value and sends this intermediate delay amount to the variable delay device to reduce the error signal output from the error measuring device. Control means (80)
And a digital signal analysis device having.