JPH056999A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To provide a semiconductor device where the leak current occurrence between a source and a drain and between the drain and a gate by the reduction of cell area can prevented and the length of the channel region can be controlled. CONSTITUTION:A polycrystalline silicon film is stacked to cover the gate electrodes a and 2a made on as base 1, and is etched anisotropically to form irregular gate electrodes b and 2b where the angles of the tops are smooth shapes. This is constituted such that a source region 4, a channel region 6, and a drain region 5 are made in parts on the polycrystalline silicon film 13 being so made as to cover these gate electrodes b and 2b through a gate insulating film 3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device formed of a polycrystalline silicon semiconductor and a method of manufacturing the same, and more particularly to a MIS transistor and a method of manufacturing the same, and more particularly to gate leakage current and leakage current between a source region and a drain region. It relates to what can be reduced.

[0002]

2. Description of the Related Art FIG. 5 is a sectional view showing the structure of a conventional semiconductor device, particularly a MIS type transistor portion formed of a polycrystalline silicon semiconductor, as shown in Japanese Patent Laid-Open No. 57-60868. Is a base for forming a thin film polycrystalline silicon MIS transistor, 2 is a gate electrode, 3 is a gate insulating film,
Reference numeral 4 is a source region, 5 is a drain region, and 6 is a channel region. The gate electrode 2 is formed of a first polycrystalline silicon film of the first conductivity type, and the source region 4, the drain region 5 and the channel region 6 are formed of the same second polycrystalline silicon film, but the second polycrystalline silicon film is formed. After the polycrystalline silicon film is formed, only the source region 4 and the drain region 5 are made to have the same conductivity type to serve as the source region 4 and the drain region 5.
The gate electrode 2 and the source region 4, the drain region 5, and the channel region 6 are electrically insulated by the gate insulating film 3. This thin film polycrystalline silicon MIS transistor is, for example, a P-channel polycrystalline silicon MIS transistor.
When it is formed as a transistor and is used as a load portion of a storage element of a complete CMOS type SRAM, the base 1 is a single crystal silicon semiconductor substrate, a conductive type polycrystalline silicon film other than those described above, semiconductor silicon and a refractory metal. Before the first polycrystalline silicon for forming the gate electrode 2 is deposited, a metal silicide film, which is a compound of the above, is combined by well-known techniques such as deposition and photo-etching to form various electronic circuits. Except for a specific part, the entire surface is covered with an insulating film (not shown) so that the gate electrode 2 is not connected to the underlying conductive film at an unnecessary point.

Next, a method of manufacturing the polycrystalline silicon MIS transistor shown in FIG. 5 will be described with reference to FIGS. 6 and 7 (b). First, the electronic circuit is configured as described above, and unnecessary portions are all covered with the insulating film on the base 1.
For example, the first polycrystalline silicon film 7 of a certain conductivity type is reduced in pressure CV.
Film thickness of 15 using D (Chemical Vapor Deposition) method
After being deposited to about 0 nm, a resist film 8 is formed by the photolithography method (FIG. 6 (a)).

Next, using the resist film 8 as a mask, the first polycrystalline silicon film 7 is etched by, for example, RIE (Reactive Ion Etching) method to form the gate electrode 2. After removing the resist film 8, for example, low pressure CVD method. A gate insulating film 3 is formed by depositing, for example, an oxide film having a predetermined film thickness on the entire surface by using.

Further, a second polycrystalline silicon film 9 is formed thereon.
Is deposited to a predetermined film thickness by, for example, the low pressure CVD method (FIG. 7 (c)), and then a resist film 10 is formed by the photolithography method as shown in FIG. 7 (a). For example, BF ₂ ⁺ is implanted into the entire surface by using, for example, an ion implantation technique as a mask (FIG. 7A).

Finally, injected BF ₂ ⁺ boron (B)
P-type portions formed by diffusing ions into the second polycrystalline silicon film 9 by heat treatment become source regions 4 and drain regions 5, which are masked by the resist film 10 so that boron (B) ions do not diffuse. Channel part 6
(Fig. (B)).

[0007]

Since the conventional semiconductor device and the manufacturing method thereof are configured as described above, in order to reduce the memory cells occupying a large proportion of the chip area and increase the storage capacity. By reducing the area of each element constituting the memory cell, for example, a P-channel polycrystalline transistor used as a load of the memory cell, the area per memory cell (hereinafter referred to as cell size) is reduced and integrated. It is necessary to increase the degree. As a result, the distance between the source region 4 and the drain region 5, that is, the channel region 6 becomes shorter, punch-through occurs, the leak current increases, and the performance of the memory deteriorates. Further, when the P-type impurities in the source region 4 and the drain region 5 are diffused by the heat treatment, the channel region 6 becomes shorter, and in the worst case, the channel region 6 disappears.

Further, as shown in FIG. 5, since the gate electrode 2 has a rectangular cross-sectional shape, a strong electric field is likely to be generated between the gate electrode 2 and the source region 4, and the gate electrode 2 and the source region 4 are passed through the gate insulating film 3. There is a problem in that a leak current flows during that time, which deteriorates the performance as a memory, and the reliability of the gate insulating film 3 decreases.

The present invention has been made in order to solve the above problems. Even if the element area is reduced, the performance is deteriorated due to the leakage current between the source region and the drain region and between the gate electrode and the source region. It is an object of the present invention to provide a semiconductor device capable of obtaining a channel region having a desired length and a manufacturing method thereof.

[0010]

A semiconductor device according to the present invention is a thin film polycrystalline silicon having a gate electrode formed on a base substrate and a channel region formed on the gate electrode via an insulating film. In a device including a MIS transistor, the gate electrode is formed by connecting a plurality of convex first-layer gate electrodes formed on the base substrate with second-layer gate electrodes. 1 with irregularities
It is one gate electrode.

The semiconductor device according to the present invention further comprises a thin film polycrystalline silicon MIS transistor having a gate electrode formed on a base substrate and a channel region formed on the gate electrode via an insulating film. In things,
The corners of the upper end of the gate electrode are formed to have a smooth shape.

In the semiconductor device according to the present invention, the gate electrode is formed on a base substrate on which irregularities appear at regular intervals.

In the method of manufacturing a semiconductor device according to the present invention, the first polycrystalline silicon film deposited on the underlying substrate is etched to form a plurality of convex first-layer gate electrodes. And anisotropic etching of the second polycrystalline silicon film deposited so as to cover the gate electrode of the first layer to form a plurality of concave-convex molds with smooth corners at the upper end. The step of forming the second-layer gate electrode, the step of depositing a third polycrystalline silicon film on the insulating film formed so as to cover the second-layer gate electrode, and the step of forming the third polycrystalline silicon film. A source region and a drain region are formed in the third polycrystalline silicon film by ion implantation using a resist film formed so as to cover a portion of the crystalline silicon film corresponding to the upper portion of the second-layer gate electrode, as a mask, Channel just below the resist film It is intended to include a step for a region.

[0014]

In the semiconductor device according to the present invention, since the gate electrode has a plurality of convex shapes, the leak current between the source region and the drain region can be reduced and a channel region having a desired length can be formed. You can

Further, in the semiconductor device according to the present invention, since the corner portion of the upper end portion of the gate electrode has a smooth shape, the gate leak current flowing through the gate insulating film can be eliminated.

Further, in the semiconductor device according to the present invention, since the gate electrode is formed on the convex portion of the underlying substrate which originally has a certain degree of irregularities, the same effect can be obtained with the gate electrode having the same film thickness as the conventional one.

The method of manufacturing a semiconductor device according to the present invention comprises a first convex structure formed on a base substrate.
Since the second polycrystalline silicon film deposited so as to cover the gate electrode of the first layer is anisotropically etched to form the gate electrode of the second layer, the corner portion of the upper end has a smooth shape. Thus, it is possible to easily obtain a gate electrode including a plurality of uneven portions.

[0018]

1 is a cross-sectional view showing the structure of a semiconductor device according to an embodiment of the present invention, in which 1 is a base forming a polycrystalline silicon MIS transistor, and a and 2a.
Is a gate electrode of the polycrystalline silicon MIS transistor, and is for providing a characteristic step in the gate electrode of the polycrystalline silicon MIS transistor according to the present invention. b and 2b are gate electrodes, which are also characteristic of the present invention, for forming the gate electrode so that the corners of the upper end thereof have a smooth shape. The gate electrodes b and 2b are electrically Is electrically connected to the gate electrodes a and 2a. 3 is a gate insulating film, 4 is a source region, 5 is a drain region, and 6 is a channel region. Gate electrode a,
Since 2a and the gate electrodes b and 2b are formed of a polycrystalline silicon film having the same conductivity type, they are conductive as described above. The source region 4, the drain region 5 and the channel region 6 are formed of the same polycrystalline silicon film, and the source region 4 is formed after the polycrystalline silicon film is formed.
Only the drain region 5 and the drain region 5 have the same conductivity type, so that the source region 4 and the drain region 5 are used. Further, the gate electrodes a and 2 a and the gate electrodes b and 2 b are electrically insulated from the source region 4, the drain region 5 and the channel region 6 via the gate insulating film 3. The base 1 is
This polycrystalline silicon MIS transistor is formed as, for example, a P-channel polycrystalline silicon MIS transistor,
When used as a load of a memory cell of a complete CMOS type SRAM, a single crystal silicon semiconductor substrate, a polycrystalline silicon film of a conductivity type other than the above, or a metal silicide film which is a compound of semiconductor silicon and a refractory metal Although various electronic circuits are formed by combining the above materials by a technique such as deposition and photolithography, before depositing the polycrystalline silicon forming the gate electrodes a, 2a and the gate electrodes b, 2b,
A structure in which the entire surface except for a specific part is covered with an insulating film (not shown) so that the gate electrodes a and 2a and the gate electrodes b and 2b are not connected to the conductive film of the base 1 at unnecessary points. It has become.

Next, the polycrystalline silicon MI according to the present invention is used.
A method of manufacturing the S transistor will be described with reference to FIG. First, as described above, an electronic circuit is configured by combining a single crystal silicon semiconductor substrate, a polycrystalline silicon film, and a metal silicide film, and unnecessary portions are all formed on the base 1 covered with an insulating film. , A certain conductivity type polycrystalline silicon film is deposited with a film thickness X ₂ larger than that of a conventional gate electrode by using, for example, a low pressure CVD method, and the gate electrodes a and 2a are formed by using a photo-etching technique. (Fig. 2
(a)).

Then, on the entire surface, a polycrystalline silicon film 11 of the same conductivity type as the polycrystalline silicon film of the gate electrodes a and 2a is formed.
Is deposited by using, for example, a low pressure CVD method (FIG. 2 (b)).
). The thickness X ₃ of the polycrystalline silicon film 11 (the same figure (b)
Shows the two gate electrodes a and 2 shown in FIG.
The distance is set to be about 1/3 or less of the distance X ₁ between a. This is because the gate insulating film 3 and the channel region 6 are also formed in the gap between the two gate electrodes a and 2a. Also, 2
Since the two gate electrodes a and 2a and the polycrystalline silicon film 11 have the same conductivity type, they are electrically conductive.

Next, the polycrystalline silicon film 11 is partially etched by using, for example, an anisotropic etching technique to form the electrodes b and 2b of the second layer (FIG. 2 (c)).
At this time, the corners at the upper end of the polycrystalline silicon film 11 deposited on the gate electrodes a and 2a are rounded.

After that, a resist film 12 is formed by a photolithography technique, and using the resist film 12 as a mask, for example, an unnecessary polycrystalline silicon film 1 is formed by the RIE method.
1 is etched (FIG. 3 (a)).

Then, a gate insulating film 3 is formed by depositing, for example, an oxide film having a predetermined film thickness by using, for example, the low pressure CVD method, and then polycrystalline silicon having a predetermined film thickness by using the low pressure CVD method. A film 13 is formed, a resist film 14 is formed thereon by a photolithography technique, and then BF ₂ ^+, for example, is implanted using the resist film 14 as a mask by using, for example, an ion implantation technique (FIG. 2B). ).

Finally, BF ₂ ⁺ boron (B) is heat-treated and diffused in the polycrystalline silicon film 13 to form P.
The parts which become the mold become the source region 4 and the drain region 5, and the part where the boron (B) is not diffused by being masked by the resist film 14 becomes the channel region 6 (FIG. 3 (c)).
The length of the channel region 6 is a polycrystalline silicon film for forming the gate electrodes a and 2a if the ion implantation conditions for forming the source region 4 and the drain region 5 and the subsequent heat treatment time are kept constant. Can be controlled by adjusting the film thickness X ₂ and the distance X ₁ between the two gate electrodes a and 2a.

In this embodiment, as described above, the gate electrodes a and 2a formed on the base substrate 1 are connected by the gate electrodes b and 2b of the second layer to form a plurality of concave and convex portions 1. Since the two gate electrodes are formed, the length of the channel region 6 formed along the uneven portion, that is, the distance between the source region 4 and the drain region 5 is smaller than that of the channel region of the polycrystalline silicon MIS transistor having the conventional structure. Since it becomes longer, it is easy to suppress the occurrence of punch through, the leak current between the source region 4 and the drain region 5 can be reduced, and the length of the channel region 6 is the same as that of the ions when the source region 4 and the drain region 5 are formed. if implantation conditions and the subsequent heat treatment time even Oke set constant, the polycrystalline silicon film for forming the gate electrode a, the 2a and thickness X _2, 2 two gate electrodes a, between 2a Away X ₁ and enables controlled by adjusting the, from the channel region 6 is eliminated can be prevented from diffusing impurities from the source region 4 and drain region 5 during the heat treatment.

Further, the gate electrodes b and 2b are removed by the conventional structure because the corners of the upper end are smoothed by the anisotropic etching technique and do not reflect the shape of the underlying gate electrodes a and 2a. The strong electric field between the source region 4 and the gate electrode, which could not be achieved, is relaxed, and the gate leak current can be reduced.

A gate formed by forming two convex gate electrodes a and 2a on the base 1 and anisotropically etching the polycrystalline silicon film 11 deposited so as to cover the gate electrodes a and 2a. Since the two gate electrodes a and 2a are connected by the electrodes b and 2b to form one gate electrode as a whole, the gate electrode having a plurality of uneven portions with a smooth corner at the upper end portion Can be easily formed.

FIG. 4 is a sectional view showing the structure of a semiconductor device according to another embodiment of the present invention. Unlike the first embodiment, since the gate electrodes a and 2a are formed on the convex portions of the base 1 which originally have some irregularities, the height of the gate electrodes a and 2a is emphasized by the convex portions. Even if a polycrystalline silicon film for forming the gate electrodes a and 2a is deposited with the same film thickness as that of the conventional structure, the same effect as that of the first embodiment is obtained.

Further, in a memory IC having memory cell portions in which memory elements are regularly arranged in a matrix like a complete CMOS type SRAM, for example, irregularities of the base 1 appear at regular intervals. If the above-mentioned gate electrodes a and 2a are formed on such an underlayer 1 with the same film thickness as in the conventional example, the above-mentioned effective effects can be obtained simultaneously and uniformly in a large number of polycrystalline silicon MIS transistors. As a result, it is possible to realize a complete CMOS type SRAM in which the performance of an IC as a storage element assembly, particularly the performance of any storage element is uniform.

In this embodiment, the gate electrodes a and 2a are composed of two convex portions, but three or more convex portions may be provided depending on the desired length of the channel region 6. .

[0031]

As described above, according to the present invention, this gate electrode is one gate having a plurality of concavo-convex portions formed by connecting the first-layer gate electrode with the second-layer gate electrode. Since it is an electrode, the length of the channel region formed along the irregularities can be increased, which has the effect of suppressing the occurrence of punch-through, reducing the leak current, and improving the memory performance. There is an effect that a semiconductor device whose length can be controlled can be obtained.

Further, since the corner portion at the upper end of the gate electrode has a smooth shape, the gate leak current can be reduced and the memory performance can be improved.

Further, two first-layer gate electrodes are formed from the first polycrystalline silicon film thicker than the film thickness of the conventional gate electrode deposited on the underlayer, and the first gate electrode deposited so as to cover the first gate electrode. Since the second polycrystalline silicon film is anisotropically etched to form the second-layer gate electrode and one gate electrode is formed as a whole, the corners of the upper end portion are smooth. There is an effect that a plurality of uneven gate electrodes can be easily formed.

In addition, when the underlying layer originally has a certain degree of unevenness, the film thickness of the gate electrode is the same as the conventional one, and the same effect can be obtained, and further, the memory cells are characterized in that the memory elements are regularly arranged in a matrix. If the unevenness of the underlying substrate is formed, it is possible to secure the above-mentioned effective effects simultaneously and uniformly, and it is possible to realize an IC as a memory device aggregate having uniform performance of all memory devices. is there.

[Brief description of drawings]

FIG. 1 is a sectional view showing a structure of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a schematic cross sectional view showing the method for manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 3 is a schematic sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 4 is a sectional view showing the structure of another embodiment of the semiconductor device according to the present invention.

FIG. 5 is a sectional view showing a structure of a conventional semiconductor device.

FIG. 6 is a schematic cross-sectional view showing a conventional method for manufacturing a semiconductor device.

FIG. 7 is a schematic cross-sectional view showing a method for manufacturing a conventional semiconductor device.

[Explanation of symbols]

1 groundwork a, 2a Gate electrode b, 2b gate electrode 3 Gate insulation film 4 Source area 5 drain region 6 channel area 11 Polycrystalline silicon film 12 Resist film 13 Polycrystalline silicon film 14 Resist film

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[Procedure amendment]

[Submission date] November 19, 1991

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] 0002

[Correction method] Change

[Correction content]

[0002]

2. Description of the Related Art FIG. 5 is a sectional view showing the structure of a conventional semiconductor device, particularly a MIS type transistor portion formed of a polycrystalline silicon semiconductor, as shown in Japanese Patent Laid-Open No. 57-60868. Is a base for forming a thin film polycrystalline silicon MIS transistor, 2 is a gate electrode, 3 is a gate insulating film, 4 is a source region, 5 is a drain region, and 6 is a channel region. The gate electrode 2 is formed of a first polycrystalline silicon film of the first conductivity type, and the source region 4, the drain region 5 and the channel region 6 are formed of the same second polycrystalline silicon film, but the second polycrystalline silicon film is formed. After the polycrystalline silicon film is formed, only the source region 4 and the drain region 5 are made to have the same conductivity type to serve as the source region 4 and the drain region 5. The gate electrode 2 and the source region 4, the drain region 5, and the channel region 6 are electrically insulated by the gate insulating film 3. This thin film polycrystalline silicon MI
The S transistor is, for example, a P channel polycrystalline silicon M
Formed as an IS transistor, complete CMOS type SRA
When used in the load portion of the memory element M is a metal silicide film or the like is a compound of the polycrystalline silicon film and semiconductor silicon and the refractory metal conductivity type Ru Hi single crystal silicon semiconductor substrate as the base 1, Various electronic circuits are constructed by combining well-known techniques such as deposition and photolithography.
Before depositing the first polycrystalline silicon which forms the gate electrode 2, the entire surface is covered with an insulating film (not shown) except for a specific part, so that the gate electrode 2 is not separated from the underlying conductive film. It is structured so that it will not be connected where necessary.

[Procedure Amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0004

[Correction method] Change

[Correction content]

Next, using the resist film 8 as a mask, for example, RIE (Reactive Ion Etchin)
g) method, the first polycrystalline silicon film 7 is etched to form the gate electrode 2, the resist film 8 is removed, and then, for example, a low pressure CVD method is used to deposit an oxide film of a predetermined thickness on the entire surface. To form the gate insulating film 3 (FIG. 3B).

[Procedure 3]

[Document name to be amended] Statement

[Correction target item name] 0008

[Correction method] Change

[Correction content]

Further, as shown in FIG. 5, since the gate electrode 2 has a rectangular cross section, the gate electrode 2 and the drain region are
A strong electric field is likely to be generated between the regions 5 , and a leak current also flows between the gate electrode 2 and the drain region 5 through the gate insulating film 3 to deteriorate the performance as a memory and reduce the reliability of the gate insulating film 3. There was a problem.

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] 0009

[Correction method] Change

[Correction content]

The present invention has been made in order to solve the above-mentioned problems. Even if the element area is reduced, the source region and the drain region, and the gate electrode and the drain region are disposed between the source region and the drain region.
No performance degradation due to leakage current at 5, and an object thereof is to provide a semiconductor device and a manufacturing method thereof to obtain a channel region of a desired length.

[Procedure Amendment 5]

[Document name to be amended] Statement

[Correction target item name] 0018

[Correction method] Change

[Correction content]

[0018]

1 is a cross-sectional view showing the structure of a semiconductor device according to an embodiment of the present invention, in which 1 is a base forming a polycrystalline silicon MIS transistor, and a and 2a.
Is a gate electrode of the polycrystalline silicon MIS transistor, and is for providing a characteristic step in the gate electrode of the polycrystalline silicon MIS transistor according to the present invention. b and 2b are gate electrodes, which are also characteristic of the present invention, for forming the gate electrode so that the corners of the upper end thereof have a smooth shape. The gate electrodes b and 2b are electrically Is electrically connected to the gate electrodes a and 2a. 3 is a gate insulating film, 4 is a source region, 5 is a drain region, and 6 is a channel region. Gate electrode a,
Since 2a and the gate electrodes b and 2b are formed of a polycrystalline silicon film having the same conductivity type, they are conductive as described above. The source region 4, the drain region 5 and the channel region 6 are formed of the same polycrystalline silicon film, and the source region 4 is formed after the polycrystalline silicon film is formed.
Only the drain region 5 and the drain region 5 have the same conductivity type, so that the source region 4 and the drain region 5 are used. Further, the gate electrodes a and 2 a and the gate electrodes b and 2 b are electrically insulated from the source region 4, the drain region 5 and the channel region 6 via the gate insulating film 3. The base 1 is
This polycrystalline silicon MIS transistor is formed as, for example, a P-channel polycrystalline silicon MIS transistor,
When used as a load for the memory cell of the full CMOS type SRAM is deposited a metal silicide film such as a compound of the single crystal silicon semiconductor substrate Hi Ru conductivity type polycrystalline silicon film and semiconductor silicon and the refractory metal, Various electronic circuits are configured by combining the techniques such as photolithography, but before depositing the polycrystalline silicon forming the gate electrodes a and 2a and the gate electrodes b and 2b, except for a certain part The entire surface is covered with an insulating film (not shown) so that the gate electrodes a and 2a and the gate electrodes b and 2b are not connected to the conductive film of the base 1 at unnecessary points.

[Procedure correction 6]

[Document name to be amended] Statement

[Correction target item name] 0019

[Correction method] Change

[Correction content]

Next, the polycrystalline silicon MI according to the present invention is used.
The manufacturing method of the S transistor for 2 of stone Figure 3 (c) will be described. First, as described above, an electronic circuit is configured by combining a single crystal silicon semiconductor substrate, a polycrystalline silicon film, and a metal silicide film, and unnecessary portions are all formed on the base 1 covered with an insulating film. , A certain conductivity type polycrystalline silicon film is deposited with a film thickness X ₂ larger than that of a conventional gate electrode by using, for example, a low pressure CVD method, and the gate electrodes a and 2a are formed by using a photo-etching technique. (Fig. 2
(A)).

[Procedure Amendment 7]

[Document name to be amended] Statement

[Correction target item name] 0026

[Correction method] Change

[Correction content]

Further, the gate electrodes b and 2b are removed by the conventional structure because the corners of the upper end are smoothed by the anisotropic etching technique and do not reflect the shape of the underlying gate electrodes a and 2a. Dray couldn't
The strong electric field between the gate region 5 and the gate electrode is relaxed, and the gate leak current can be reduced.

[Procedure Amendment 9]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 2

[Correction method] Change

[Correction content]

[Fig. 2]

Claims (4)

[Claims] 1. A gate electrode formed on a base substrate,
In a semiconductor device including a thin film polycrystalline silicon MIS transistor having a channel region formed on the gate electrode via an insulating film, the gate electrode has a plurality of convex-shaped protrusions formed on the base substrate. A semiconductor device comprising a single gate electrode having a plurality of concavo-convex portions formed by connecting a first-layer gate electrode with a second-layer gate electrode. 2. A gate electrode formed on a base substrate,
In a semiconductor device including a thin film polycrystalline silicon MIS transistor having a channel region formed on the gate electrode via an insulating film, a corner portion of an upper end portion of the gate electrode is formed to have a smooth shape. A semiconductor device characterized by the above. 3. The semiconductor device according to claim 1, wherein the gate electrode is formed on a base substrate on which irregularities appear at regular intervals. 4. A step of etching a first polycrystalline silicon film deposited on a base substrate to form a plurality of convex first-layer gate electrodes, and the first-layer gate The second polycrystalline silicon film deposited so as to cover the electrodes is anisotropically etched to form a second-layer gate electrode having a plurality of convex shapes in which the shape of the corners of the upper end is smooth. And a step of depositing a third polycrystalline silicon film on an insulating film formed to cover the gate electrode of the second layer, and the second layer of the third polycrystalline silicon film. Forming a source region and a drain region in the third polycrystalline silicon film by ion implantation using a resist film formed so as to cover a portion corresponding to the upper part of the gate electrode of
And a step of forming a channel region directly below the resist film.