JPH0568892B2 - - Google Patents

Description

[Detailed description of the invention]

[Technical Field of the Invention] The present invention relates to a CR type oscillator, and particularly to one improved so that a stable oscillation signal can be obtained by keeping the oscillation frequency within a preset tolerance range. [Technical background of the invention and its problems] As is well known, a CR type oscillator performs an oscillation operation by switching the charge/discharge polarity of a CR time constant circuit made up of a resistor R and a capacitor C. One example is a three-stage inverter type shown in FIG. In other words, this three-stage inverter type CR oscillator connects the first to third inverters INV ₁ to INV ₃ in series, and connects the output end of the second inverter INV ₂ to the first inverter INV ₁ through a capacitor C. The output terminal of the third inverter INV 3 is connected to the input terminal of the first inverter INV ₁ via a resistor R, and the output terminal of the third inverter INV ₃ is connected to the input terminal of the first inverter INV ₁ through a resistor _R. by
The oscillation signal φ _S (oscillation frequency is _OSC ) is obtained by switching the charge/discharge polarity of the CR time constant circuit. Here, the operating characteristics of the three-stage inverter type CR oscillator will be described. Generally, the oscillation frequency _OSC is expressed by the following equation. _OSC = 1/K・CR ...(1) In this case, if K is ideally a constant,
Although a constant oscillation frequency can be obtained, in reality, K cannot be a constant because parameters such as power supply voltage and temperature vary. For example, if we consider a case in which an integrated circuit is configured under the above power supply voltage conditions, the power supply voltage is V _DD [V], and the inverter circuit threshold voltage is
When V _thc [V], K in equation (1) is: K = [l _o V _thc /V _DD +V _thc +l _o V _DD −V _thc /2V _DD −V _thc
]...(2) The above circuit threshold voltage V _thc is

[Purpose of the invention]

This invention was made in order to improve the above-mentioned problems, and it is possible to obtain an oscillation signal with a substantially stable oscillation frequency even when parameters such as power supply voltage and temperature fluctuate, as well as to eliminate malfunctions and in a short period of time. The purpose of this invention is to provide an extremely good CR type oscillator that can obtain a desired oscillation frequency. [Summary of the Invention] That is, in this invention, in order to achieve the above object, by selectively connecting a plurality of time constant elements to vary the time constant,
In order to keep the oscillation frequency within a preset allowable frequency range and to keep the oscillation frequency at the initial stage of oscillation within the allowable frequency range, the multiple time constant elements mentioned above are forcibly connected for a predetermined period of time when the power is turned on. /A CR-type oscillation circuit that performs disconnection control and can vary the oscillation frequency by selectively connecting multiple time constant elements to vary the time constant, and a reference frequency signal generating means that generates a reference frequency signal. , by comparing each frequency of the oscillation signal output from the CR type oscillation circuit and the reference frequency signal, it is determined whether the oscillation frequency of the oscillation signal is within a preset allowable frequency range, is above the allowable frequency, or is the allowable frequency. oscillation frequency determining means for determining whether the oscillation frequency is equal to or less than the allowable frequency; when the oscillating frequency determining means determines that the oscillation frequency is equal to or higher than the allowable frequency, a first control signal is generated; a control signal generating means for selectively connecting the plurality of time constant elements so that the oscillation frequency decreases in response to generation of the first control signal; selection control switching means for selectively controlling the selection and switching of the time constant elements so that the oscillation frequency increases;
and oscillation initial setting means for forcibly controlling the connection/disconnection of the time constant element of the CR type oscillation circuit for a predetermined period of time when the power is turned on to set the frequency of the oscillation signal within a preset allowable frequency range. be. [Embodiment of the Invention] Hereinafter, an embodiment of the present invention will be described in detail with reference to FIGS. 4 to 9. Figure 4 shows its basic configuration.
is a CR type oscillation circuit. This CR type oscillation circuit 11
has a plurality of time constant elements, and by selectively connecting the plurality of time constant elements to vary the time constant, the frequency of the oscillation output can be varied. . The oscillation signal φ _S output from the CR type oscillation circuit 11 is supplied to the oscillation frequency determination circuit 12 . The oscillation frequency determination circuit 12 receives a reference frequency signal φ _a output from a reference frequency signal generation circuit (not shown) together with the oscillation signal φ _S , and compares the frequencies of these two signals φ _S and φ _a . This determines whether the oscillation frequency _OSC of the oscillation signal φ _S is within a preset allowable frequency range, is above the allowable frequency, or below the allowable frequency, and generates and outputs a judgment signal according to each judgment result. It is. This determination signal is supplied to the control signal generation circuit 13. The control signal generation circuit 13 stops generating the control signal in response to the determination signal, that is, when it is determined that the oscillation frequency _OSC is within the permissible frequency range, and when it is determined that the oscillation frequency OSC is within the permissible frequency range, the oscillation frequency It generates a down control signal that lowers _{the OSC} , and when it is determined that the frequency is below the allowable frequency, it generates an up control signal that raises the oscillation frequency _OSC . This control signal is then supplied to the selection switching control circuit 14. When the control signal is a down control signal, this selection switching control circuit 14 controls the plurality of time constant elements of the CR type oscillation circuit 11 in a direction in which the oscillation frequency _OSC decreases in response to the generation of this down control signal. When the control signal is an up control signal, the plurality of time constant elements are controlled to change the oscillation frequency _OSC in response to the generation of this up control signal.
Control is performed so that the necessary connections are selected and connected sequentially in the direction in which the number increases. That is, the CR type oscillator configured as described above constantly compares the oscillation frequency _OSC of the oscillation signal φ _S output from the CR type oscillation circuit 11 with the frequency of the reference frequency signal φ _a , and based on the comparison result, the oscillation frequency It is determined whether the frequency is within the permissible frequency range, and based on the result of this determination, a down control signal or an up control signal is generated, and based on the generation of this control signal, the plurality of CR oscillation circuits 11 are activated. Lower the oscillation frequency _OSC by using the time constant element. Alternatively, selection switching control is performed sequentially in the increasing direction, thereby making it possible to always keep the oscillation frequency _OSC within the permissible frequency range and obtain a substantially stable oscillation signal φ _S. Here, the oscillation frequency determination means of the CR type oscillator will be explained with reference to FIG. First, the reference frequency signal φ _a for the oscillation signal φ _S shown in FIG. 5a is set to have a frequency sufficiently lower than the oscillation frequency _OSC of the oscillation signal φ _S as shown in FIG. 5 b. Then, from these two signals φ _S and φ _a , as shown in FIG. 5c, a certain fixed time frame F _2n
(m=1, 1, 2, ...), for example, by taking the AND of the oscillation signal φ _S and the reference frequency signal φ _a , l (l=1, 2, ...) corresponding to the oscillation signal φ _S is obtained.
3,...) pulse trains are generated. moreover,
Count this pulse train to obtain an arbitrary time frame F _2n
Convert l pulse trains into n-bit data, and combine this n-bit data with the desired oscillation frequency,
In other words, n corresponding to a frequency within the permissible frequency range
By comparing the oscillation frequency OSC with the bit data, it can be determined whether the oscillation frequency _OSC is within the permissible frequency range, above the permissible frequency, or below the permissible frequency. Therefore, any time frame F _2n+1
, a control signal is generated so as to keep the oscillation frequency _OSC within the allowable frequency range, and by selectively controlling the plurality of time constant elements of the CR type oscillation circuit 11 using this control signal, the oscillation frequency _OSC is kept within the allowable frequency range. It can be kept within this range and stabilized. Next, a specific circuit of a CR type oscillator according to the present invention using the three-stage inverter type CR oscillator is shown in FIG. 6, and its configuration will be explained. First, the CR type oscillator circuit 11 consists of six resistors R ₀ ~
A three-stage inverter type oscillator consisting of _R5 , capacitor C, and inverters _INV1 to _INV3 is connected to an inverter _INV6 for waveform shaping, and the oscillation signal _φS output from this CR type oscillation circuit 11 is an AND gate. Supplied to G ₁ and G ₂ . This AND gate G ₁ , G ₂ is the inverter INV ₇
The oscillation frequency determination circuit 12 is configured together with the 7-bit counter 15 and the AND gate G ₁ receives the reference frequency signal φ _a outputted from the reference frequency signal generation circuit (not shown) via the 1/8 frequency dividing circuit 16. Furthermore, the reference frequency signal φ _a is further supplied to the AND gate G ₂ via the inverter INV ₇ . In other words, and gate G ₁ is
The AND signals φ _S and φ _a of the oscillation signal φ _S and the reference frequency signal φ _a are generated and output to the clock input terminal CK of the 7-bit counter 15, and the AND gate G ₂
generates an AND signal φ _S , a of the oscillation signal φ _S and _{the inverted reference frequency signal φ a and} outputs it to the OR gate G ₃ . This OR gate _G3 has a 2-bit counter 17,
AND gate G ₄ ~ G ₆ , inverter INV ₈ , INV ₉
Together with this, the state setting circuit 18 is configured, and its output is connected to the clock input terminal of the 2-bit counter 17.
Supplied to CK. The output Q ₀ of this 2-bit counter 17 is supplied to AND gates G ₄ and G ₅ and also supplied to AND gate G ₆ via an inverter INV ₉ , and the output Q ₁ is supplied to AND gates G ₄ and G _{6 .}
It is also supplied to AND gate _G5 via inverter _INV8 . The output of the AND gate _G4 is then supplied to the OR gate _G3 . In other words, the state setting circuit 18 configured in this manner outputs the state setting signals _S , φ ₁ , and _S ·φ ₂ from the AND gates G ₅ and G ₆ , of which the state setting signal _S ·φ ₂ is It is supplied to the reset terminal R of the 7-bit counter 15. This 7-bit counter 15 outputs the AND signals φ S and φ _a according to the output of the state setting signals _S and _{φ 2} .
By _{counting the} pulse trains _of
~ _Q6 is the input terminal _D0 of the 4-bit latch circuit 19~
Supplied to _D3 . This 4-bit latch circuit 19 is connected to an inverter.
Together with INV ₁₀ to INV ₁₃ , AND gates G ₇ and G ₈ , and OR gates G ₉ to _{G 10} , this constitutes the control signal generation circuit 13, so that the above-mentioned state setting signal _S・φ ₁ is supplied to the clock input terminal CK. has been done,
According to the output of this state setting signal _S・_φ1 , the above 7
Upper 4 bits output of bit counter 15 _Q3 to _Q6
The values are held and output from output terminals _Q0 to _Q3 . Of these, output Q ₀ is supplied to AND gate G ₇ via inverter INV ₁₀ , and outputs Q ₁ and Q ₂ are supplied to AND gate G ₇ as well as inverter INV 10.
The output Q 3 is supplied to the OR gate G ₉ via INV ₁₁ and INV ₁₂ , and the output Q ₃ is supplied to the AND gates G ₇ and G ₈ via the inverter INV ₁₃ . The output of the OR gate _G9 is supplied to the AND gate _G8 , and the output of the AND gate _G7 is supplied to the OR gate _G10 . The OR gate _G10 is supplied with the state setting signal _φS · _φ2 , and its output is supplied to the clock input terminal CK of the 6-bit up-down counter 20. Further, the output of the AND gate G _S is supplied to the up/down control input terminal U/D of the counter 20 . This 6-bit up-down counter 20 is connected to an oscillation initial setting circuit 21 and an inverter INV ₁₄ to
INV ₁₉ and the resistance R ₀ of the CR type oscillation circuit 11
~ Switch circuits S ₀ each connected in parallel to R ₅
~ _S5 constitutes the selection switching control circuit 14, which counts the pulse train of the output of the OR gate _G10 in the up direction or down direction according to the output of the AND gate _G8 , and outputs the output terminals _Q0 to _Q5, respectively.
This outputs the counted value from the . This output
Q ₀ -Q ₅ are supplied to control input terminals of switch circuits S ₀ -S ₅ via inverters INV ₁₄ -INV ₁₉ , respectively, to control on/off of the switch circuits S ₀ -S ₅ . The oscillation initial setting circuit 21 is for setting the initial state of the counter 20 when the power is turned on, and is used to set the initial state of the counter 20 after the power is turned on so that the initial oscillation falls within the allowable input frequency range of the oscillation control system. Force inverter INV ₃ to INV ₁ for a specified time
Set the feedback resistance value to FIG. 7 shows a more detailed configuration example of the up-down counter 20 and the oscillation initial setting circuit 21 in FIG. 6. In the figure, the same components as in FIG. 6 are given the same reference numerals. That is, the 6-bit up-down counter 20 consists of six flip-flops FF ₀ to _{FF 5} connected in cascade.
The flip-flops FF ₀ to _{FF 5} are each supplied with an up-down control signal U/D and a clock signal CK. Outputs ₀ to ₅ of the flip-flops FF ₀ to FF ₅ are respectively supplied to control input terminals of switch circuits S ₀ to _{S 5} . 21 is a power-on clear circuit that works as an oscillation initial setting circuit, and this circuit 21 is connected to the power supply voltage V.
A resistor R _P is connected between the power supply terminal 22 to which is applied and a ground point, a capacitor C _P is connected in parallel to this resistor R _P , and the input terminal is connected to the power supply terminal 22 and the output terminal is connected to the flip-flop FF. The inverter INV ₂₀ is connected to the set input terminal S of FF ₅ and the reset input terminal R of FF ₄ . Next, the operation in the above configuration will be explained. First, in the initial stage of oscillation immediately after the power is turned on, the inverter is activated for a predetermined period of time determined by a CR time constant circuit consisting of a resistor R _P and a capacitor C _P.
The output of INV ₂₀ becomes "1" level, flip-flop FF ₅ is set, and FF ₄ is reset. now,
Assuming that _the flip _- flop is in the up mode, as _shown in the timing chart _of FIG.
It becomes L” level and the output of flip-flop _FF5
Only _Q5 becomes "H" level. Therefore, the switch circuits _S0 to _S4 are in the on state, _S5 is in the off state, and only the resistor _R5 functions as a time constant resistance value. Then, a time t when a predetermined period of time determined by a CR time constant circuit consisting of a capacitor C _P and a resistor R _P has elapsed.
At , forced resistance selection is canceled and oscillation is started. Such initial settings prevent the initial oscillation frequency from becoming extremely high immediately after power is turned on. On the other hand, in the down mode, as shown in FIG. 8b, the flip-flops FF ₀ to
Outputs Q ₀ to Q ₃ and Q ₅ of FF ₃ and FF ₅ are all at "H" level, and only output Q ₄ of flip-flop FF ₄ is at "L" level. Therefore, only the resistor _R4 does not function as a time constant resistor before time t. This prevents the initial frequency of oscillation from becoming extremely low. As described above, the frequency at the initial stage of oscillation falls within a predetermined range set in advance, and the desired oscillation frequency is obtained from this state, so there is no malfunction and the desired frequency can be obtained in a short time. Next, a time t when a predetermined period of time has elapsed since the power was turned on.
The subsequent operation will be explained. The CR type oscillator shown in FIG. 6 has an oscillation frequency _OSC of the oscillation signal _φS .
The set value is 20 [kHz], the frequency of the reference frequency signal φ _a is 1.6 [kHz], and the allowable frequency range is 19.2 [kHz].
Hz] to 22 [kHz], and here it is assumed that the oscillation signal φ _S is outputted at an oscillation frequency _OSC of 20+Δ [kHz] as shown in FIG. 9a. Further, the reference frequency signal φ _a is outputted at a frequency of 200 [Hz] as shown in FIG. 9b through the ⅛ frequency dividing circuit 16. In other words, in this CR type oscillator, the time frame F _2n (=F _2n+1 ) is set to 2.5 [mS], and the oscillation signal φ _S and the reference frequency signal φ _a from the 1/8 frequency divider circuit 16 The AND gate _G1 that receives the input generates the AND signal φ _S and φ _a as shown in FIG.
It will now be output to . That is, by counting the pulse train of the AND signals φ _S and φ _a in the time frame F _2n by the 7-bit counter 15, the oscillation frequency _OSC [kHz] of the oscillation signal φ _S is converted into 7-bit data. That is, the count value of this 7-bit counter 15 and the 7-bit data Q ₀ to _{Q 6}
is as shown in the following table depending on the oscillation frequency _OSC [kHz].

〔Effect of the invention〕

As detailed above, according to the present invention, an oscillation signal with a substantially stable oscillation frequency can be obtained even when parameters such as power supply voltage and temperature vary, and a desired oscillation frequency can be obtained in a short time without malfunction. Therefore, it is possible to provide an extremely good CR type oscillator.

[Brief explanation of the drawing]

1 to 3 are a circuit diagram and a characteristic diagram showing the configuration and characteristics of a conventional CR type oscillator, respectively. FIG. 4 is a block circuit diagram showing an embodiment of the CR type oscillator according to the present invention, and FIG. is a waveform diagram for explaining the frequency determination means in the above embodiment, FIG. 6 is a circuit diagram showing a CR type oscillator when the above embodiment is configured with a specific circuit, and FIG. 7 is a waveform diagram for explaining the frequency determination means in the above embodiment. A circuit diagram for explaining a detailed configuration example of an up-down counter and an oscillation initial setting circuit in the circuit, FIG. 8 is a waveform diagram for explaining the operation of the circuit shown in FIG. 7, and FIG. A waveform diagram showing the output waveforms of the main parts of the circuit shown in the figure, and FIGS. 10 and 11 are characteristic diagrams showing the measurement results of the oscillation frequency in the CR oscillator, respectively. 11...CR type oscillation circuit, 12...Oscillation frequency determination circuit, 13...Control signal generation circuit, 14...
Selection switching control circuit, 15...7 bit counter,
16...1/8 frequency divider circuit, 17...2-bit counter, 18...state setting circuit, 19...4-bit latch circuit, 20...6-bit up-down counter, 21...oscillation initial setting circuit, _φS ...Oscillation signal, φ _a ...Reference frequency signal.

Claims (1)

[Claims] 1. A CR-type oscillation circuit that can vary the oscillation frequency by selectively connecting a plurality of time constant elements to vary the time constant, and a reference frequency signal generator that generates a reference frequency signal. and determining whether the oscillation frequency of the oscillation signal is within a preset permissible frequency range or above the permissible frequency range by comparing each frequency of the oscillation signal output from the CR type oscillation circuit and the reference frequency signal. , or oscillation frequency determination means for determining whether the frequency is below the allowable frequency;
control signal generating means for generating a first control signal when the oscillation frequency is determined to be equal to or higher than the permissible frequency by the oscillation frequency determining means; and generating a second control signal when the oscillation frequency is determined to be equal to or lower than the permissible frequency; 1st
The plurality of time constant elements are selectively connected so that the oscillation frequency decreases in response to the generation of the second control signal, and the plurality of time constant elements are connected to the oscillation frequency in response to the generation of the second control signal. a selective switching control means that selectively connects the CR type oscillation circuit so that the frequency of the oscillation signal increases; A CR type oscillator characterized by comprising oscillation initial setting means for setting within a frequency range. 2. The selection switching control means for controlling the oscillation frequency has a preset or pre-reset function, and the oscillation initial setting means presets or pre-resets the oscillation frequency for a predetermined period of time in the initial stage of oscillation. As stated in scope 1
CR type oscillator.