JPH0567960A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To reduce the switching time by decreasing ground bounce noise in the logic semiconductor integrated circuit. CONSTITUTION:The integrated circuit is provided with a multi-stage voltage controlled pre-driver circuit 1, an internal logic circuit 30, a buffer MOSFET 10 and a load means 12. At first, a gate of the buffer MOSFET10 is driven by a pulse V1 whose voltage is lower than a power supply voltage and after an output voltage Vout changes, a higher voltage pulse V2 is fed to the gate of the buffer MOSFET10 through delay circuits 5,6.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit such as a semiconductor memory, a gate array, a standard logic, etc., which is used in an electronic computer, a communication device or the like and which requires particularly high speed operation.

[0002]

2. Description of the Related Art FIG. 2 shows a circuit diagram of a conventional semiconductor integrated circuit. In the IC chip 40, an internal logic unit 30 that receives input data, a control signal, and the like and performs processing, a large buffer MOSFET 10 that has a large current driving capability and that pulls down, and a subbuffer MOSFET 11 that has a relatively small size, A load means 12 for outputting a high level to a load, and a buffer MOSFET 10 and a sub-buffer MOSFET 1 that receive the output of the internal logic 30.
It is composed of a pre-driver circuit 20 for driving 1 and the like.

V _IN 1 to 3 are input signals, and V _OUT is an output voltage. A load capacitance 50 and a load resistor 51 are connected as an external load. The power supply terminals for V _CC and V _SS and the input / output terminals 61 to 64 are connected to the IC chip 40 by bonding wires.
And lead inductances 41 to 46 are equivalently present. The value L of these parasitic inductances is several to ten and several nH, and when the output changes from the “H” level to the “L” level (dt), a current change (di) causes noise to the ground line.
This noise is called ground bounce and is usually L · di.
It is represented by / dt.

Conventionally, the pull-down transistor is divided into a buffer MOSFET 10 having a large size and a sub-buffer MOSFET 11 having a relatively small size in order to successfully control the time change of the output current. Then, the sub-buffer MOSFET 11 is first turned on, and then the buffer MOSFET 10 is turned on with a delay by the delay circuit including the resistor 22 and the capacitor 23, so that di / dt is suppressed to be small and ground bounce is reduced.

[0005]

However, the conventional drive circuit cannot always sufficiently suppress the ground bounce. The reason is as follows. Generally, semiconductor integrated circuits employ TTL level input / output. The L level has an output current (I _OL ) of several tens mA and an output voltage (V _OL ) of 0.5 V or less. In order to realize this output level, the buffer MOSFET 10 has a large transistor size of several hundreds of μm or more, and is usually a CMO.
Since it is driven by the pre-driver circuit 20 constituted by the S inverter 21, if the power supply voltage V _CC is directly applied to the gate of the buffer MOSFET 10, it will be considerably overdriven. Attempting to achieve high-speed switching operation in such an overdrive state results in large ground bounce.

Further, conventionally, since two buffer MOSFETs 10 and sub-buffer MOSFETs 11 are used, two drive lines are required and the layout also requires a large area. Therefore, the present invention intends to realize a low ground bounce and a high-speed operation at the same time by applying an optimum pulse to the gate electrode while keeping one drive line to the buffer MOSFET 10.

[0007]

In order to suppress the ground bounce, it is necessary to reduce di / dt, but the extraction current i itself of the buffer MOSFET 10 must have a large value for high speed operation. Therefore, a pulse that rises at a high speed with a low gate voltage for constant current driving is first applied to perform switching. Then, after the ground bounce due to the switching at the output end is subsided, a high gate voltage that allows sufficient I _OL to flow is applied. That is, the multi-stage voltage control pre-driver circuit that can generate several pulses having different peak voltage values and different timings is configured.

[0008]

By the action] multistage voltage control pre-driver circuit, ground bounce for pulled out a current from the output end driven at a constant current as not to overdrive when switching low, DC specific granular buffer such as I _OL can be sufficiently driven The gate voltage of the MOSFET can be controlled.

[0009]

1 is a circuit diagram of a semiconductor integrated circuit according to the present invention. V ₁ and V ₂ are output voltages of the first and second step-down circuits 2 and 3 which generate a voltage lower than the power supply voltage V _CC ,
There is a relationship of V ₁ ≤V ₂ ≤V _CC . The output of the logic circuit 30 enters the CMOS inverter 4 and buffers the voltage V ₁ in the buffer M.
It is given to the gate of the OSFET 10. Further, the output of the CMOS inverter 4 is transmitted to the CMOS inverter 5 and delayed by the capacitor 6. The second step-down circuit 3 supplies the voltage V ₂ to the CMOS inverter 7. The output delayed by the CMOS inverter 7 is applied to the gate of the buffer MOSFET 10.

FIG. 3 is a circuit diagram of another semiconductor integrated circuit of the present invention. The first step-down circuit 2 of FIG. 1 is realized by an n-ch MOSFET 8 which is saturated in FIG. Further, set V ₂ = V _CC , omitting the second step-down circuit 3 in FIG.
The OS inverter 7 is also simplified to a p-ch MOSFET 9. 4A and 4B are timing charts of FIGS. 3 and 4. In FIG. 4A, the horizontal axis represents time, and the vertical axis represents the input signal voltage V _IN 1 and the output voltage V of the pre-driver 1.
_dr shows the output voltage V _OUT of the buffer MOSFET 10. FIG. 4B shows the current i of the buffer MOSFET 10 on the vertical axis. The logic circuit 30 receives the input signal V _IN 1.
Operates and its output rises when the output voltage V _dr of the pre-driver 1 is t ₁ . At this time, buffer MOSFET 1
The gate of 0 is driven by the stepped down voltage V ₁ , and electric charges are extracted from the output end by a constant current, and the output voltage V _OUT starts to drop. The time difference between the input voltage V _IN 1 and the output voltage V _OUT crossing 1.5 V is the propagation delay time td. Output voltage V
Time t after _OUT has changed from H to L and the waveform has settled down
It is driven by a voltage V ₂ (or V _CC ) higher than the voltage V ₁ at ₂ . As a result, a sufficient output current I _OL (Fig. 4
(See (b)) can be supplied. Here, the voltage pulse is shown in two stages, but it is more preferable to generate a voltage pulse with a larger number of stages and perform delicate gate voltage control in order to suppress ground bounce and perform high-speed switching.

[0011]

As described above, the present invention can realize high-speed switching operation and low ground bounce noise. Furthermore, since the wiring of the output driver is simple, it also has the effect of reducing the chip area.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of an integrated circuit of the present invention.

FIG. 2 is a circuit diagram of a conventional integrated circuit.

FIG. 3 is a circuit diagram showing another embodiment of the integrated circuit of the present invention.

FIG. 4 (a) is an input voltage V _IN in FIG. 1 and FIG.
2 is a timing chart of the output voltage V _dr and the output voltage V _OUT of 1 and the pre-driver. (B) is a timing chart of the current i of the buffer MOSFET in FIGS. 1 and 3.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Multi-stage voltage control type pre-driver circuit 2,3 1st and 2nd step-down circuit 4,5,7 CMOS inverter 10 Buffer MOSFET 12 Load means 30 Internal logic circuit 41-46 Lead inductance 50 Load capacity 51 Load resistance

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H04Q 3/52 A 9076-5K

Claims (1)

[Claims] 1. A multi-stage voltage control type pre-driver circuit 1 for receiving a single data signal and generating a plurality of pulses having a voltage value equal to or lower than a power supply voltage and having different timings, and the pre-driver circuit. A semiconductor integrated circuit comprising a buffer MOS transistor 10 having a gate electrode connected to an output, and a driver circuit having a load means 12 connected between one of electrodes other than the gate of the buffer MOS transistor 10 and a power supply voltage.