JPH0936727A - Signal output method, its circuit and semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a signal output technology excluding the effect of a switching noise. SOLUTION: A signal output circuit whose output voltage changes in response to a change in an input voltage is provided with a 1st signal output circuit [transistors(TRs) Q1a and Q1c ] receiving a 1st power supply for a transition period till a prescribed switching voltage is reached after an output voltage starts its transition and with a 2nd signal output circuit [transistors(TRs) Q1b and Q1d ] receiving a 2nd power supply in a steady-state after the end of the transition period. Another signal output circuit is selected before a switching noise is generated in a power path due to transition of an output current and then the voltage is maintained by a power supply free from switching noise.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to improvement of a signal output circuit constituting a final stage of signal output in a semiconductor integrated circuit such as a memory and an interface circuit.

In a semiconductor integrated circuit, an input signal is subjected to a predetermined process and output from a final stage signal output circuit. The signal output is connected to the output pin of the IC package by a bonding wire or the like from the silicon chip.
When the logic of the output signal is inverted and the output signal level transits, a transition current flows through the signal output circuits of these semiconductor integrated circuits. At this time, switching noise may occur in the output signal due to the inductance of the bonding wire and the output pin.

The switching noise can be reduced by improving the manufacturing method such as the wire connecting method.
Various improvements in circuit configurations have been studied.

[0004]

2. Description of the Related Art FIG. 8 shows an outline of a conventional signal output circuit in a semiconductor integrated circuit. The output stage of a semiconductor integrated circuit often constitutes an inverter circuit capable of supplying a predetermined electric power. In FIG. 8, transistors Q ₁₀ and Q ₁₁
Represents an inverter, and C is a wiring capacitance. When the input voltage IN changes, the output voltage OUT changes to a logic level opposite to the logic of the input voltage after a delay time corresponding to the switching speed of the transistor. L ₁₀ and L
₁₁ is a wire frame or a lead pin (output terminal) that connects between the package of the silicon chip and the semiconductor integrated circuit
Is an inductor generated by the presence of. In the presence of the inductance, in a digital IC in which the output level transits in a short time and a transition current flows rapidly, an induced electromotive force V _L = −L · di / dt (L is an inductance) is generated by the inductance.

FIG. 9 shows a configuration in which a plurality of output circuits C _{1 to} C _n are connected to one power supply terminal J ₀ . In such a circuit configuration, when the output voltage of the lead pins J _{1 to} J _n changes at one time, a large output current flows in the power supply wiring, so that the above-described inductance has a great influence.

Since the induced electromotive force due to these inductances is a counter electromotive force, a delay occurs in the transition of the output voltage.
Therefore, due to the influence of the delay element of the inductance L and the wiring capacitance component C, the output voltage during the transition period has a so-called ringing in which the voltage level oscillates immediately after the logic level changes (see FIG. 10, broken line). Ringing).
Ringing causes a voltage fluctuation at a power supply point in a circuit at a previous stage connected to the same power supply, and causes a malfunction as switching noise.

As a known technology of a signal output circuit for preventing switching noise, there is an invention described in, for example, Japanese Patent Laid-Open No. 4-253420. According to the invention, the inverter circuits are provided in parallel, one of the inverter circuits has a low ON resistance, and the other inverter circuit has a high ON resistance. The invention makes the resistivity different between when the first current relatively flows due to the transition of the logic state and in the steady state,
It was to reduce the effect of switching noise.

[0008]

However, in the conventional signal output circuit, although the switching noise is reduced due to the difference in the on-resistance of the transistors, the effect of the switching noise due to the transition current remains in the power supply, so that the switching is completed. The integrated circuit was not protected from noise.

That is, according to the above-mentioned conventional invention, even if switching noise such as ringing occurs, since the on-resistance of the transistor is increased, the effect of suppressing the flow of the output current is obtained, but it is supplied from the power supply. It cannot be denied that some switching noise is transmitted to the current.

Therefore, it is an object of the present invention to provide a signal output method and circuit that eliminate the influence of switching noise.

[0011]

According to a first aspect of the present invention, when power is supplied to a signal output circuit in which an output voltage changes in response to a change in input voltage, the output voltage changes from the time when the output voltage starts transitioning. Power is supplied from the first power supply in the transition period until the predetermined switching voltage is reached, and power is supplied from the second power supply in the steady state after the completion of the transition period.

The first power supply and the second power supply may be output from the same voltage supply source, and the induced electromotive force due to the inductance existing in the supply path of the first power supply causes It does not have to affect the supply route.

According to a second aspect of the present invention, in the signal output method according to the first aspect, the predetermined switching voltage is a voltage corresponding to the steady voltage in the steady state after the change of the output voltage is completed (for example, 100% or 90% of the steady voltage), and the transition period is a period from when the output signal starts the transition to when the voltage corresponding to the steady voltage is first reached.

According to a third aspect of the present invention, in a signal output circuit in which the output voltage changes in response to a change in the input voltage,
A first signal output circuit to which the first power supply is supplied in the transition period from when the output voltage starts to transition to when it reaches a predetermined switching voltage, and a second power supply in the steady state after the end of the transition period And a second signal output circuit.

According to a fourth aspect of the present invention, in the signal output circuit according to the third aspect, the predetermined switching voltage is a voltage corresponding to a steady voltage in a steady state after the change of the output voltage is finished, and the transition is made. The period is a period from when the output signal starts changing to when the voltage corresponding to the steady voltage is first reached.

According to a fifth aspect of the present invention, in the signal output circuit according to the third or fourth aspect, the first signal output circuit detects the transition period corresponding to the rise of the output voltage, and outputs the first signal. First switch means for connecting the output end of the output circuit to the first power supply, and a period corresponding to the transition period at the fall of the output voltage is detected, and the output end of the first signal output circuit is connected to a predetermined reference potential. The second signal output circuit detects that the transition period corresponding to the rise of the output voltage has ended, and sets the output terminal of the second signal output circuit to the second power supply. The third switch means is connected, and the fourth switch means is connected to detect the end of the transition period corresponding to the fall of the output voltage and connect the output end of the second signal output to the reference potential. It

According to a sixth aspect of the invention, in the signal output circuit according to the third to fifth aspects, the first power source and the second power source are provided.
A discharge circuit is provided which is interposed between the power supply and the first power supply and which becomes conductive when the difference between the supply voltage of the first power supply and the supply voltage of the second power supply becomes a predetermined level or more.

According to a seventh aspect of the present invention, in a semiconductor integrated circuit including the signal output circuit according to any of the third to sixth aspects in a final stage of signal processing, among the power supplies supplied to the signal output circuit. The second power supply is used as the power supply for the other circuits that form the preceding stage of the signal output circuit.

[0019]

According to the present invention, since the transition current flows through the signal output circuit during the transition period from the start of the change of the output voltage to the reaching of the predetermined switching voltage, the inductance existing in the output wiring or the power supply line is induced. Electricity is generated. Since the inductance forms a delay element together with the wiring capacitance, ringing occurs in the voltage at the supply point of the power supply due to the influence of the fluctuation of the current due to the delay element after the logic level is determined (FIG. 10).
See the waveform of the vibration indicated by the broken line).

Since power is supplied from the first power supply during the transition period, there is an influence of the inductance of the path of the first power supply. However, the power supply supplied to the signal output circuit is switched to the second power supply in a stage before the ringing occurs in the predetermined switching voltage, that is, the signal output voltage. The ringing generated in the first power supply is attenuated by the impedance of the path of the first power supply after being separated from the second power supply. On the other hand, since the second power supply serves only as a power supply source for pull-up (or pull-down) for maintaining the signal output after the transition period ends, switching noise does not occur. Even if the power supply in the previous stage of the signal output circuit is supplied from the second power supply, it is excluded from the influence of switching noise (see the waveform shown by the solid line in FIG. 10).

The first power supply and the second power supply may be output from the same voltage supply source, and the induced electromotive force due to the inductance existing in the supply path of the first power supply is the same as that of the second power supply. It does not have to affect the supply route.

In particular, according to the invention described in claim 2 or claim 4, the switching voltage is a voltage corresponding to the steady voltage in the steady state after the change of the output voltage is completed (for example, 100 of the steady voltage). % Or 90%), and the transition period is the period from when the output signal starts transition to when the voltage corresponding to the steady voltage is first reached, so that the power supply is switched before switching noise occurs.

According to the third aspect of the present invention, since the first power supply is supplied to the first signal output circuit, the output circuit is disconnected after switching the power supply, and switching noise is attenuated in the output circuit. Therefore, the second signal output circuit to which the second power is supplied has no effect.

According to the fifth aspect of the present invention, the first signal output circuit is supplied with the first power supply during the transition period detected by the first switch means at the rise of the output voltage, and the first signal output circuit rises. At the time of falling, the second switch means connects the second power source after the steady state. On the other hand, the second signal output circuit is connected to the second power supply by the third switch means or to the reference potential by the fourth switch means according to the logic of the steady state.

Therefore, the current in the transition period flows only in the first signal output circuit, and the second signal output circuit is separated from the switching noise generated in the first power supply. According to the sixth aspect of the present invention, in the discharge circuit, when the switching noise generated in the first power supply has a magnitude equal to or higher than a predetermined level such that the switching noise is not attenuated after the power supply is cut off, that is, a predetermined threshold value. When the amplitude value is above, the first power supply and the second power supply are connected. If both power supplies are connected, the impedance of the path will decrease.

Therefore, the current derived from the predetermined level of switching noise is attenuated. Since the period for energizing the second power source is very short, it has little influence on the circuit supplied with power from the second power source.

According to the invention described in claim 7, during the transition period, the first power supply is connected to the signal output circuit, and after the transition period ends, the switching noise is attenuated in the path of the first power supply.
After the transition period ends, the other integrated circuit in the previous stage continues to operate with the second power supply that is not affected by the switching noise.

[0028]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the apparatus of the present invention will be described with reference to the drawings. (I) First Embodiment FIG. 1 shows a block diagram of a signal output circuit of the first embodiment.

The transistors Q _1a and Q _1c form an inverter as a first signal output circuit. L ₁ and L
Reference numeral ₃ is an inductance existing in the path of the first signal output circuit.

The inverter INV ₁ , the delay (delay element) D ₂ , the NAND ₂ and the transistor Q _1a operate as a first switch means. The delay time of delay D ₂ is
This is the time corresponding to the transition period at the time of rising of the inverter that constitutes the first signal output circuit. NAND ₂ is at L level for a period corresponding to the time difference between the two inputs. Therefore,
The ON signal 1a becomes a signal for turning on the transistor Q _1a for a time corresponding to the rising period.

Inverter INV ₂ , delay D ₃ , NO
R ₁ and transistor Q _1c act as a second switch means. The delay time of the delay D _{3 is} the time corresponding to the transition period at the fall of the inverter that constitutes the first signal output circuit. NOR ₁ is at H level for a period corresponding to the time difference between the two inputs. Therefore, the ON signal 1c becomes a signal for turning on the transistor Q _1c for the time corresponding to the falling period.

The transistors Q _1b and Q _1d form an inverter as a second signal output circuit. L ₂ and L
Reference numeral ₄ is an inductance existing in the path of the second signal output circuit.

The delay D ₁ delays the input signal during the transition period at the time of rising of the inverter forming the second signal output circuit. NAND ₁ sets its output to L level only when both inputs are at H level. Therefore, the ON signal 1b
Is a signal for turning on the transistor Q _1b in the steady state of H level after the transition period.

The delay D ₄ delays the input signal during the transition period at the fall of the inverter forming the second signal output circuit. NOR ₂ sets the output to the H level only when both inputs are at the L level. Therefore, the ON signal 1d
Is a signal for turning on the transistor Q _1d in the L level steady state after the transition period is completed.

The characteristics of each transistor are the same.
And an inverter that constitutes the first signal output circuit, and a second signal
Signal output circuit has the same transition period as the inverter
If you have delay D₁And D_TwoAnd D_ThreeAnd D
_FourAnd the same delay time may be set. In addition,
Jista Q_1a-Q_1cAnd the transistor Q_1b-Q _1d
1 may be connected as shown in Fig. 1.
It does not need to be connected if the characteristics of the data are the same. First power supply
V_CC1And the second power supply V_CC2Supply the same voltage as each other
You.

The timing chart of FIG. 2 shows changes in each ON signal according to the configuration of the first embodiment. L
When the input voltage IN rises from the steady state of the level (period i), the ON signal 1a is turned on for a period corresponding to the rising period of the first signal output circuit, and the transition current is the first power supply V
It is supplied from _CC1 to the wiring capacitance C (period ii).

When the output voltage OUT reaches the H level steady state, the ON signal 1b is supplied, and the output terminal of the output circuit is the second terminal.
It is pulled up to the power supply V _CC2 (period iii). At this time, since the transition of the current is completed, switching noise is not mixed in the second power supply.

When the input voltage IN falls again, the ON signal 1 is output for a period corresponding to the rising period of the first signal output circuit.
c is turned on, and the transition current is discharged from the wiring capacitance C to the ground terminal (period iv).

The output voltage OUT is in the L level steady state.
Then, the ON signal 1d is supplied and the output end is pulled to the ground end.
(Period v). As described above, in the first embodiment,
Therefore, the transition current of the first signal output circuit is the inductance
L₁And L_ThreeSwitching noise
Occur. However, after the transition period ends, the second signal output
The voltage is held by the second power supply (or ground end) of the path and the current
Is not flowing, the second power source is the inductor existing in the path.
Tance L _TwoAnd L_FourNot affected by. Occurs on the first power supply
The switching noise generated gradually increases in the first signal output circuit.
Decay.(II) Second embodiment FIG. 2 shows a block diagram of the signal output circuit of the second embodiment.

In the signal output circuit 200 of the second embodiment, in the configuration of the signal output circuit 100 of the first embodiment, a block for pulling up the output terminals of the transistors Q _1a and Q _1b and transistors Q _1c and Q _1d. In this configuration, an inverter circuit is provided between the output terminal and the block for pulling down the output terminal.

The inverter circuit comprises transistors Q _2e1 and Q _2e2 and an inverter INV ₃ . The output voltage is taken out between the transistors Q _2e1 and Q _2e2 .

The transistors Q _{2a to} Q _2d correspond to the transistors Q _{1a to} Q _1d of the first embodiment, respectively. Other configurations are similar to those of the first embodiment. Therefore, the ON signals 2a to 2d of this embodiment correspond to the ON signals 1a to 1d described in the first embodiment, respectively.

FIG. 4 shows a timing chart according to the second embodiment. The operation of the second embodiment is basically the first
It operates in the same order as in the embodiment. However, transistor Q
_Since an inverter with _2e1 and Q _2e2 is inserted,
The ON resistance is increased as compared with the first embodiment, and the ON resistance of the transistor accelerates the attenuation of the ringing amplitude generated in the first power supply V _CC1 after the power supply is switched.

Therefore, according to the second embodiment, the first
While having the common technical idea of switching the power supply between the transition period and the steady state as in the embodiment, the ON resistance is further increased and the effect of switching noise is reduced. (III) Third Embodiment FIG. 5 shows a block diagram of a signal output circuit of the third embodiment.

The signal output circuit 300 of the present embodiment is constructed by including the discharging circuit 3 according to claim 6 between the first power supply and the second power supply used in each of the above-mentioned embodiments. Reference numeral 1 denotes an internal circuit, which means a circuit portion of the semiconductor integrated circuit other than the signal output circuit at the final stage. C ₁ -C
For example, the signal output circuit described in the above embodiment is applied to _n . The internal circuit 1 is assumed to be supplied with the second power supply V _CC2 via the lead pin Jb, for example.

Reference numeral 2 is an outer shape of the IC package, which is a lead pin Ja for supplying a first power source, a lead pin Jb for supplying a second power source, and a lead pin J to which output signals of the signal output circuits C _{1 to} C _n are connected. _{1 to} J _n .

FIG. 6 shows an example of a transistor circuit suitable for use in the discharge circuit 3. The circuit shown in FIG. 6 constitutes a limiter circuit equivalent to connecting diodes of opposite polarities by connecting the anodes and cathodes of the transistors Q ₁ and Q ₂ to each other.

In the above structure, each signal output circuit C ₁
-C _n performs the operation as a signal output circuit of each of the above embodiments. That is, during the output voltage transition period, power is supplied from the first power supply V _CC1 via the lead pin Ja, and after the output voltage transition period, power is supplied from the second power supply V _CC2 via the lead pin Jb.

However, as in this embodiment, when a plurality of signal output circuits are connected to the same power source and the output voltage transitions simultaneously, a large current flows from the power source at a time. When the value of the flowing current is large, the induced electromotive force of the opposite polarity due to the inductance of the path also becomes large, and the amplitude of switching noise also increases. When the amplitude of the switching noise is large, the switching noise is not sufficiently attenuated by the first signal output circuit, so the next transition period starts and the power supply of the signal output circuit is switched from the second power supply to the first power supply. Sometimes the effect of ringing is exerted on the output circuit.

Therefore, in the present embodiment, the switching noise is reduced by the discharging circuit 3 when the switching noise having a predetermined amplitude or more enters the power supply path. That is, since the discharge circuit 3 has a function of conducting when the difference between the first power supply voltage and the second power supply voltage becomes equal to or higher than a predetermined threshold value, both power supplies are short-circuited when the amplitude due to ringing is equal to or higher than this threshold value. Will be done. When both power supplies are short-circuited, the inductance component decreases and the switching noise decays faster.

According to the circuit as shown in FIG. 6, both power supplies are short-circuited when the voltage difference between both power supplies reaches the threshold voltage (gate-cathode voltage) of the n-type transistor. As described above, according to the third embodiment, the switching noise can be reduced more quickly when the switching noise is large. (IV) Fourth Embodiment In the fourth embodiment, the present invention is applied to a normal interface circuit such as a computer device.

FIG. 7 shows the configuration of the computer circuit of the fourth embodiment. As shown in FIG. 7, the computer circuit 400 of this embodiment is connected with interface circuits 5 and 6 in order to connect the CPU 4 and the memory 7. The interface circuit 5 is connected to the first power supply V _CC1 , and the interface circuit 6 is connected to the second power supply V _CC2 . The interface circuits 5 and 6 perform substantially the same circuit operation. However, the interface circuit 5 is supplied with power during the transition of the output voltage and outputs the output current. The interface circuit 6 is supplied with power when the output voltage is fixed and maintains the output voltage.

In the above structure, when a transition current flows in each power supply path due to the influence of the inductances L ₅ and L ₆ , switching noise is generated as in the signal output circuits of the above embodiments. Interface circuit 5 during the transition period
_Operates , and switching noise causes switching noise in the path of the first power supply V _CC1 . However, when the transition period ends, the interface circuit to be used is switched from the interface circuit 5 to the interface circuit 6. Since the interface circuit 6 maintains the output voltage without passing the transition current, the switching noise after the output is determined is not input to the memory 7, the wrong address is accessed, or the wrong data is not stored. . The switching noise generated in the path of the first power supply is attenuated inside the interface circuit 5.

As described above, according to the fourth embodiment, since the interface circuit is switched during the transition period and after the output is determined, it is possible to prevent malfunction of the computer equipment. (V) Other Modifications Various modifications are possible without being limited to the above embodiment of the present invention.

Not only the signal output circuit or the computer circuit, but also any digital circuit in which a switching noise may occur in the power supply voltage generated at the supply terminal of the power supply due to the influence of the inductance due to a sudden transition current flowing due to the transition of the output signal. Therefore, the present invention can be applied.

That is, two circuits that are substantially equal to each other are operated in parallel to separate the power supply for one and the power supply for the other. Then, one circuit may be operated during the transition period of the output voltage, and the operation may be switched to the other circuit at the same time as the end of the transition period.

Further, in each of the above embodiments, two power sources were used, but the power source may be common. However, the paths from the power supply source to the power supply terminal for each signal output circuit, etc. should be different, and the impedance of one path should not be the same as the impedance of the other path, so that the power supply should be radial. Wiring the power supply of If the power supply wiring is performed with such consideration, it is substantially equivalent to providing two power supplies.

[0058]

According to the present invention, since the switching is made to the second power supply in which the transition current does not flow before the ringing due to the switching noise occurs in the path of the first power supply, it is connected to the output voltage and the second power supply. Other circuits do not malfunction due to switching noise existing on the power supply line.

In particular, according to the second or fourth aspect of the invention, since the power source is switched in the vicinity of reaching the steady voltage, switching noise can be effectively eliminated. According to the invention of claim 6, when the discharge circuit generates switching noise having an amplitude equal to or larger than a predetermined threshold value, the first power supply and the second power supply are connected to each other. When a transition current flows in the circuit at one time, the damping of the switching noise itself can be accelerated.

According to the invention described in claim 7, since the other integrated circuit operates by the second power supply which is not affected by the switching noise, it is possible to prevent the malfunction due to the mixing of the switching noise in the power supply.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a signal output circuit of a first embodiment.

FIG. 2 is a timing chart for the signal output circuit of the first embodiment.

FIG. 3 is a configuration diagram of a signal output circuit of a second embodiment.

FIG. 4 is a timing chart of a signal output circuit according to a second embodiment.

FIG. 5 is a configuration diagram of a signal output circuit of a third embodiment.

FIG. 6 is a configuration example of a discharge circuit.

FIG. 7 is a configuration diagram of a computer circuit according to a fourth embodiment.

FIG. 8 is a first example of a conventional signal output circuit.

FIG. 9 is a second example of a conventional signal output circuit.

FIG. 10 is a diagram illustrating a state of an output voltage of a signal output circuit.

[Explanation of symbols]

1 ... internal circuit 2 ... IC package 3 ... discharging circuit Q ... transistor INV ... inverter NAND ... NAND gate NOR ... NOR gate C ... wiring capacitance C ₁ -C _n ... signal output circuit

Claims (7)

[Claims] 1. When supplying power to a signal output circuit in which an output voltage changes in response to a change in input voltage, a power supply in a transition period from the time when the output voltage starts transition to the time when a predetermined switching voltage is reached. Is supplied from the first power supply, and the power supply in the steady state after the transition period is finished is supplied from the second power supply. 2. The signal output method according to claim 1, wherein the predetermined switching voltage is a voltage corresponding to a steady voltage in a steady state after the change of the output voltage is completed, and the transition period is the A signal output method, comprising: a period from when an output signal starts transition to when a voltage corresponding to the steady voltage is first reached. 3. A signal output circuit in which an output voltage changes in response to a change in an input voltage, wherein a first power supply is supplied during a transition period from when the output voltage starts transition to when a predetermined switching voltage is reached. And a second signal output circuit to which a second power supply is supplied in a steady state after the transition period ends, the signal output circuit. 4. The signal output circuit according to claim 3, wherein the predetermined switching voltage is a voltage corresponding to a steady voltage in a steady state after the change of the output voltage is completed, and the transition period is the A signal output circuit, wherein a period from when the output signal starts changing to when the voltage corresponding to the steady voltage is first reached. 5. The signal output circuit according to claim 3, wherein the first signal output circuit detects the transition period corresponding to the rising time of the output voltage, and the first signal output circuit First switch means for connecting the output end to the first power supply, and a period corresponding to the transition period at the fall of the output voltage is detected, and the output end of the first signal output circuit is set to a predetermined reference potential. The second signal output circuit detects that the transition period corresponding to the rise of the output voltage has ended, and outputs the output terminal of the second signal output circuit. A third switch means connected to the second power supply, and a fourth switch which detects the end of a transition period corresponding to the fall of the output voltage and connects the output end of the second signal output to the reference potential. Means and Signal output circuit, characterized in that it is configured with. 6. The signal output circuit according to claim 3, wherein the signal output circuit is interposed between the first power supply and the second power supply, and is provided between the supply voltage of the first power supply and the second power supply. A signal output circuit comprising a discharge circuit which conducts when a difference from a supply voltage exceeds a predetermined level. 7. A semiconductor integrated circuit comprising the signal output circuit according to claim 3 in a final stage of signal processing, wherein a second power supply of the power supplies supplied to the signal output circuit is the signal output. A semiconductor integrated circuit characterized by being used as a power source for another circuit which constitutes a preceding stage of the circuit.