JPH0567921A - Oscillator circuit - Google Patents

Abstract

PURPOSE:To obtain the stable oscillating frequencies of two kinds or over with one circuit. CONSTITUTION:A tri-state inverter 50 whose operating state is controlled with a control signal S1 to a control terminal 60, an inverter 1, an NMOS transistor(TR) NF1 whose conduction state is controlled by the control signal S1 a feedback resistor R2 connecting in series with the TR NF1 and a feedback resistor R1 are connected in parallel. The feedback resistor R2 and the tri-state inverter 50 are inserted between an input terminal and an output terminal or disconnected from them by changing the level of the control signal S1 so as to change the circuit constant thereby varying the oscillating frequency.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an oscillator circuit, and more particularly to an oscillator circuit of a type using a crystal oscillator and a CMOS inverter.

[0002]

2. Description of the Related Art As shown in FIG. 3, a conventional oscillator circuit of this type has a feedback amplification inverter 1 and a feedback resistor R ₁ having one end connected to the input and the output thereof. .. Then, the capacitors C ₁ and C ₂ are inserted between the input terminal 2 and the ground terminal 3 and between the output terminal 4 and the ground terminal 3 depending on the transistor size of the inverter 1 and the circuit constant of the feedback resistor R ₁ . A crystal oscillator X is added between the input terminal 2 and the output terminal 4.

[0003]

In this conventional oscillation circuit, since the circuit constant is fixed, the optimum oscillation frequency is determined at the designing / manufacturing stage. Method of changing the frequency provided dividing circuit there is also, for example, must be 2 ₁₄ divided After that the 1 _k H _z from 10 MHz _z. in this case,
If the frequency dividing circuit is constituted by a toggle flip-flop binary counter, 14 bits are required, and 14 toggle flip-flops are required. And since 20 transistors are used per block, 1
280 transistors are required for 4 blocks. When the number of transistors required for frequency division increases in this way, it becomes impossible to design a frequency division circuit when the number of transistors is limited due to the area and power consumption.

[0004]

SUMMARY OF THE INVENTION An oscillator circuit of the present invention is an oscillator circuit of a type in which a crystal oscillator, an inverter for feedback amplification and a feedback resistor are provided in parallel between an input terminal and an output terminal. In the above, a circuit in which a series circuit including a resistor and an N-channel MOS field effect transistor and a three-state inverter are connected in parallel is provided between the input terminal and the output terminal, and the N-channel MOS field effect type transistor is provided. The conduction state of the transistor and the operating state of the three-state inverter are controlled by an external control signal. In one state of the control signal, the N-channel MOS field effect transistor is in the conduction state and the three-state inverter is Operates in the output mode, and in the other state of the control signal,
The N-channel MOS field effect transistor is turned off, and the three-state inverter operates so as to be in a high impedance state.

[0005]

BEST MODE FOR CARRYING OUT THE INVENTION Next, an optimum embodiment of the present invention will be described with reference to the drawings. FIG. 1A is a block diagram of an oscillator circuit according to an embodiment of the present invention. Referring to FIG. 1 (a),
In this oscillator circuit, one end of the feedback resistors R ₁ and R ₂ ,
The outputs of the inverter 1 and the three-state inverter 50 are connected to the output terminal 4. Then, the other end of the feedback resistor R ₁ , the drain of the NMOS transistor N _F1 , the inverter 1 and the three-state inverter 50.
And the input end of are connected to the input terminal 2. Feedback resistor R
The other end of ₂ is connected to the source of the NMOS transistor N _F1 . The control input terminal of the three-state inverter 50 and the gate of the NMOS transistor N _F1 are connected to the control terminal 60. Furthermore, the input terminal 2 and the ground terminal 3
Between the output terminal 4 and the ground terminal 3 and the capacitance C ₁
And C ₂ are inserted, and the crystal unit X is added between the input terminal 2 and the output terminal 4.

The operation of the oscillator circuit of this embodiment will be described below with reference to FIG. FIG. 1B is the same as FIG.
It is the circuit diagram which represented the block diagram of (a) at the transistor level. Now, in 1 (b), the resistance values of the feedback resistors R ₁ and R ₂ are set to 250 kΩ, the gate widths of the NMOS transistors N ₁ and N ₂ of the inverter 1 and the three-state inverter 50 are set to 150 μm, and the PMOS transistors P ₁ and P ₂ are set. The gate width is 300 μm.

Here, when the control signal S ₁ to the control terminal 60 is set to "H" level, the NMOS transistor N _F1 is turned on and the feedback resistor R ₂ and the input terminal 2 are conducted.
On the other hand, the three-state inverter 50 is in the output mode. In this case, since the inverter 1 and the three-state inverter 50 are connected in parallel, the gate width of the MOS transistor when two inverters are regarded as one is N
On the MOS transistor side, 150 × 2 = 300 (μ
m), 300 × 2 = 600 on the PMOS transistor side
(Μm). Similarly, since the feedback resistors R ₁ and R ₂ are connected in parallel, the total feedback resistor R is 1 / R =
From (1/250) + (1/250), R = 125kΩ
Becomes

On the contrary, when the control signal S _{1 is set} to "L" level, the NMOS transistor N _F1 is turned off and the feedback resistor R ₂ and the input terminal 2 are cut off. On the other hand, the three-state inverter 50 has a high impedance. Therefore, in this case, the MOS of the inverter as a whole
Since the gate width of the transistor is only that of the MOS transistor of the inverter 1, 150 × 1 = 150 (μm) on the NMOS transistor side and 300 × 1 = 300 (μm) on the PMOS transistor side. The feedback resistance R as a whole at this time is R = R ₁ = 250 kΩ.

That is, when the control signal S ₁ is at "H" level, the oscillation circuit of this embodiment serves as a high frequency oscillation circuit because the feedback resistance is small and the gain of the inverter is high, and the control signal S ₁ is "L". At the "" level, the feedback resistance is large and the gain of the inverter is low, so the oscillation circuit is for low frequency. Thereby, two kinds of frequencies can be obtained without preparing two oscillation circuits.

Although the above description has been made with reference to an oscillation circuit that can obtain two types of oscillation frequencies, the present invention is not limited to this. For example, as shown in FIG. 2, a feedback resistor R ₃ and NM are added to the circuit shown in FIG.
A series circuit including the OS transistor N _F2 and a three-state inverter 51 connected in parallel to the OS transistor N _F2 are provided, and the conduction state of the NMOS transistor N _F2 and the operating state of the three-state inverter 51 are input to the control terminal 61. By controlling with the control signal S ₂ according to the above, three kinds of oscillation frequencies can be obtained. From this, it is clear that three or more kinds of oscillation frequencies can be stably obtained without providing a special circuit with the same configuration.

[0011]

As described above, in the oscillator circuit of the present invention, the circuit constant can be easily changed by switching the feedback resistance of the crystal oscillator circuit and the gate width of the inverter by changing the level of the control signal. it can. As a result, the present invention has an effect that different oscillation frequencies can be stably obtained with one circuit without providing a special circuit such as a frequency dividing circuit.

[Brief description of drawings]

FIG. 1A is a block diagram of an oscillator circuit according to an embodiment of the present invention. Diagram (b) is a diagram showing the block diagram shown in diagram (a) at the transistor level.

FIG. 2 is another block diagram of the oscillator circuit of the present invention.

FIG. 3 is a block diagram of an example of a conventional oscillator circuit.

[Explanation of symbols]

 1 Inverter 2 Input terminal 3 Grounding terminal 4 Output terminal 50,51 Three-state inverter 60,61 Control terminal

Claims (1)

[Claims] 1. An oscillator circuit of a type in which a crystal oscillator, an inverter for feedback amplification, and a feedback resistor are provided in parallel between an input terminal and an output terminal, and between the input terminal and the output terminal. , Resistance and N channel MO
A circuit in which a series circuit including an S field effect transistor and a three-state inverter are connected in parallel is provided, and a conduction state of the N-channel MOS field effect transistor and an operating state of the three-state inverter are externally provided. Of the control signal, the N-channel MOS field effect transistor is turned on in one state of the control signal, and the three-state inverter is operated in the output mode. In the state, the N-channel MOS field effect transistor operates in a cutoff state, and the three-state inverter operates in a high impedance state.