JPH0567737A - Semiconductor device having input protective circuit and manufacturing method thereof - Google Patents

Abstract

PURPOSE:To considerably enhance breakdown strength against a surge voltage in an input protective circuit itself when the input protection circuit in a semiconductor device having a BiCM0S structure is made. CONSTITUTION:On the semiconductor substrate surface formed with a p<+> embedded layer 2, an epitaxial layer for constructing a BiCM0S is formed. A plurality of n well/p well regions are formed in this layer, and in one well 3 thereof, input protective circuits 10, 20 are provided. Under the well in which this input protective circuit is formed, the p<+> embedded layer 2 is not formed, and namely the well comprising the epitaxial layer is directly formed on the substrate. An n<+> diffusion layer is formed on the well 3 surface to be an input terminal of the input protective circuit, and the well 3 is connected to a power source voltage terminal (Vcc, Vss). When the p<+> embedded layer 2 is formed, impurities are introduced based on a mask pattern corresponding to a region provided with the input protective circuit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor technology and a technology particularly effective when applied to a semiconductor device having an input protection circuit. For example, a Bi-CMOS in which a bipolar transistor and a CMOS FET are formed on the same substrate. TECHNICAL FIELD The present invention relates to a technique useful for forming an input protection circuit in a semiconductor device.

[0002]

2. Description of the Related Art In a semiconductor device in which BiCMOS is formed, an n + type buried layer and / or p + is formed on a semiconductor substrate.
A type buried layer is formed, an epitaxial layer is grown on these buried layers, an n well region and / or a p well region is formed in this epitaxial layer, and devices such as a bipolar transistor and a CMOS transistor are formed in these regions. Is formed. In forming the n + buried layer and / or the p + buried layer on the semiconductor substrate, the buried layer is formed by selectively introducing n-type impurities or p-type impurities into the surface of the semiconductor substrate by self-alignment. Was there.

By the way, conventionally, in semiconductor devices, an input protection circuit is formed in an element region where an input signal is input from the outside (input pad 32) through an aluminum wiring 30 (for example, a special feature). Wishhei 1-065841
issue). This conventional input protection circuit, as shown in FIG.
p well region 1 formed on the upper surface of the p + buried layer 102
An input portion to which an input signal from the input pad 32 is input is formed by the n + diffusion layer 104. Then, in order to form an input protection circuit, an n-channel MOS 110 is formed in which the n + diffusion layer 104 is used as a source electrode and the drain electrode (n + diffusion layer) 105 / gate electrode 106 is grounded. + Diffusion layer 10
4 as a collector electrode and an emitter electrode (n + diffusion layer) 1
A bipolar transistor 120 is formed, 21 of which is connected to the constant voltage power supply Vcc.

Of these, the bipolar transistor 120
Is an n + diffusion layer 104 formed in the p-well 103,
The n-well 122, the p-well 103, the n-well 124 and the n + diffusion layer 121 are included. In the input protection circuit of the semiconductor device configured as described above, the above n +
When an excessive surge voltage is applied to the diffusion layer 104, the n-channel MOS 110 or the bipolar transistor 120 becomes O.
Then, the surge voltage is discharged to the ground side or the constant power supply voltage side.

[0005]

However, the present inventors have clarified that the input protection circuit of the semiconductor device having the above-mentioned structure has the following problems.
That is, the conventional input protection circuit having the above-mentioned configuration originally has a CMO.
Which has been applied to a semiconductor device having an S structure,
A semiconductor device having an iCMOS structure cannot sufficiently achieve its function. That is, the well region cannot be deeply formed in order to form a bipolar transistor having excellent characteristics (this well region is formed in the epitaxial layer). Therefore, in the semiconductor device having the BiCMOS structure, the interface for dispersing the surge voltage (the n well 122 that joins with the input section 104a and the p well 10)
3) cannot be ensured sufficiently. Therefore, when a surge voltage is applied, the n well 122 and the p well 103
The density of the discharge current flowing through the interface with and becomes high. In particular, since the well region is shallow, the current easily flows in the vertical direction of the semiconductor device, and the n + well (p + buried layer) is in contact with the n well 122, so that the n channel MOS and / or the bipolar of the input protection circuit is formed. Discharge through the transistor is not sufficiently performed, and a discharge current concentrates on this interface, and junction breakdown easily occurs.

The present invention has been made in view of the above circumstances, and in making an input protection circuit for a semiconductor device having a BiCMOS formed therein, the withstand voltage of the input protection circuit itself against surge voltage is significantly improved, and It is an object of the present invention to provide a semiconductor device in which electrostatic breakdown due to the above does not occur. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0007]

The typical ones of the inventions disclosed in the present application will be outlined below. That is, in the semiconductor device of the present invention, a plurality of buried layers are formed on the surface of the substrate, an n well region and / or a p well region are formed on the plurality of buried layers, and these n well regions and / or p wells are formed. CMO in the area
In a region where an S transistor and / or a bipolar transistor is formed and an input protection circuit is further formed, a buried region is not formed and a well region formed of an epitaxial layer is formed directly on the substrate, and the well region surface is formed. A semiconductor region of a conductivity type different from this is formed, an input terminal is connected to this semiconductor region, and a power supply voltage terminal is connected to the well region.

[0008]

The buried layer is not formed in the region where the input protection circuit of the semiconductor device in which the BiCMOS is formed is formed, and the well region formed of the epitaxial layer is formed directly on the substrate. The well region has a conductivity type different from that of the well region. Since the semiconductor region to which the input terminal is connected is formed and the power supply voltage terminal is connected to the well region, the discharge current concentrates on the lower side of the well region even when a surge voltage is applied to the input terminal. There is nothing to do.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the accompanying drawings. 1 is a plan view showing an input protection circuit portion of a semiconductor device according to the present invention, FIG. 2 is a sectional view of the semiconductor device taken along line II-II of FIG. 1, and FIG. 3 is an equivalent circuit of the input protection circuit. It is a circuit diagram showing. This semiconductor device is p-
A plurality of p + buried layers and n + buried layers are formed on the type semiconductor substrate 1 (only the p + buried layer 2 is shown in FIGS. 1 and 2), and an epitaxial layer ( N-layers) are grown. Then, a p-type impurity is introduced into this epitaxial layer to form a p-well region, an n-well is formed in the other regions, and a bipolar transistor or a CMOS is formed in each of these well regions.
As described above, the layer (well) in which the bipolar transistor and the CMOS are formed is formed of an epitaxial layer in order to achieve a bipolar transistor having excellent characteristics by reducing the depth of these regions.

By the way, the p + buried layer 2 shown in FIGS. 1 and 2 is connected through a contact hole 31 to an aluminum wiring 30 for inputting an input signal from the outside of the semiconductor device through an input pad 32. An n + diffusion layer 4 is formed. On the other hand, the n + diffusion layer 4 is used for elements (such as the internal circuit 33 in FIG. 3) formed in other element regions of the semiconductor device,
It also functions as an output unit that supplies an input signal from the aluminum wiring 30. Furthermore, the n + diffusion layer 4 serves as the drain region of the n-channel MOS 10 forming a part of the input protection circuit. The n + diffusion layer 4 also functions as the emitter of the bipolar device 20 which is part of the protection circuit.

In the n-channel MOS 10, the drain region is formed by the n + diffusion layer 4 and the source region is formed by the n + diffusion layer 5. Further, the right end portion 4b of the n + diffusion layer 4 forming the drain region in the drawing is formed vertically long,
The n + diffusion layer 5 is formed so as to face the vertically long n + diffusion layer 4b.
Are vertically elongated to form the drain region of the n-channel MOS 10. These two n + diffusion layers 4b,
The region sandwiched by 5 becomes a p-layer (p well 3), on which the gate electrode 6 is arranged via a thin silicon oxide film (gate oxide film). In the n-channel MOS 10 thus formed, the gate electrode 6 and the source region (n + diffusion layer) 5 are both grounded (Vss) to form an input protection circuit (see FIG. 3).

Further, a bipolar transistor (bipolar transistor) formed on the left side of the n + diffusion layer 4 in the figure.
20 is formed by a well 22 formed below the n + diffusion layer 4 so as to surround the input portion 4a and an n well 24 formed adjacent to the well 22 via the p well 3. Of these, the power supply voltage (Vc
An n + diffusion layer 21 to which c) is applied is formed.

N of the input protection circuit configured as described above
Channel MOS 10 and bipolar transistor 20
Is usually formed on the p + buried layer 2 on the semiconductor substrate 1. However, in the semiconductor device according to the present invention, the input protection circuit is provided in order to increase the withstand voltage against surge voltage such as static electricity of the input protection circuit. Near the element region where the
The p + buried layer 2 in the middle two-dot chain line) is removed by using a mask pattern or the like during its formation (this forming method will be described later).

In this way, the input protection circuit is formed by p
+ The reason for removing a part of the buried layer 2 in advance is as follows. That is, as in the conventional semiconductor device (see FIG. 9), the p + buried layer (buried layer 1
02) is formed, the input portion (1 in FIG. 7) of the input protection circuit is formed.
04a) and its adjacent n-well (122 in FIG. 7).
And the resistance value of the boundary surface between the p + buried layer (102 in FIG. 7) on the lower side of the n well (122) is different from that of the other junction surface (for example, the n well (122) and the p well (103)). surface)
It will be lower than. Further, in the semiconductor device having the BiCMOS structure, the well region is formed by epitaxial growth, so the depth of the element region is shallow, and therefore the discharge current at the time of surge voltage is concentrated on this junction surface.
The discharge through the n-channel MOS and / or the bipolar transistor of the input protection circuit is not sufficiently performed, and the junction breakdown voltage in this portion is lowered. Therefore, in the semiconductor device shown in this embodiment, the region in which the input protection circuit is formed (at least the n well 22 in contact with the input portion 4a) is p
The surface of the semiconductor substrate 1 on which the n well 22 is located is covered with a mask pattern so that the n well 22 is not in contact with the p + buried layer 2 so as not to contact the + buried layer 2. did. By forming the input protection circuit in this way, the surge voltage applied to the input portion 4a is applied to all p-regions (p-well 3, p-semiconductor substrate 1) which are bonded to the surge voltage through the n-well 22. ), The discharge current is discharged through the n-channel MOS 10 and / or the bipolar transistor 20.

In the input protection circuit thus formed, when a positive surge voltage is applied to the input portion 4a (n + diffusion layer), the bipolar transistor 20 is turned on, and the positive discharge current is mainly generated. Power supply voltage Vc via transistor 20
It is discharged to the c side. On the contrary, when a negative surge voltage is applied, the discharge current generated at that time is grounded (power source voltage V through the n-channel MOS 10 and bipolar transistor 20).
ss) side. A part of the current flows through the n-well 22 to the p-region (p-well 3, p-semiconductor substrate 1) in contact therewith (see FIG. 3).

FIGS. 4 to 8 show the shape shown in FIGS. 1 and 2 on the surface of the semiconductor substrate 1 in the manufacturing process of the semiconductor device of the present invention (the shape in which the p + buried layer below the n well 22 is removed). FIG. 3 is a cross-sectional view of the semiconductor device showing steps up to the formation of p + buried layer 2 and n + buried layers 8 and 9 (not shown in FIGS. 1 and 2) adjacent thereto.

In forming the p + buried layer 2 and the n + buried layer having the above-described shapes, first, the silicon nitride film (Si 3 N 4) 41 is formed in a region other than the regions corresponding to the n + buried layers 8 and 9 of the semiconductor substrate 1. Are formed (FIG. 4). Ion implantation of n-type impurities is performed on this to obtain n + buried layers 8 and 9 (FIG. 5). Next, surface oxidation of the semiconductor substrate 1 (formation of the silicon oxide film 43) is performed (FIG. 6). Further, after removing the silicon nitride film 41, a resist (p-type isolation mask) 44 is formed in a region corresponding to the input portion 4a (see FIG. 1) of the above-mentioned input protection circuit, and p is used as a mask. Ion implantation of type impurities is performed to form p + buried layers 2 and 2 (FIG. 7). Next, the resist 44 and the silicon oxide film 43 are removed to obtain the semiconductor device having the structure shown in FIG.

As described above in detail, in the input protection circuit of this embodiment, in the p + buried layer 2 in which the input protection circuit is formed, the lower side of the input protection circuit (particularly the input portion 4a and the n well contacting the same) Since the p + buried layer on the lower side of 22 is removed, the n well region forming a part of the input protection circuit (bipolar transistor 20) is a p + layer (p +).
The flow path of the discharge current when a surge voltage is generated is not concentrated in one place without contact with the buried layer), and the discharge through the n-channel MOS 10 and the bipolar transistor 20 can be efficiently performed. Withstand voltage is improved. The input protection circuit having such a configuration is effective when applied to a so-called BiCMOS transistor in which a CMOS transistor and / or a bipolar transistor are formed together.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, p
The region where the + buried layer is not formed is not limited to the region shown in the figure, and the point is that it is a region of the same conductivity type as the input part (n well 22).
However, when it comes into contact with a region of opposite conductivity type, that region may not be a high-concentration impurity region. Further, although the input protection circuit is formed in the p + buried layer 2 in this embodiment, the present invention is not limited to this, and it may be formed in the n + buried layer (8, 9 in FIG. 6). In this case, the conductivity type of each region formed in the semiconductor device is the opposite conductivity type to that of the above-described embodiment.

In the above description, the invention made by the present inventor is the field of application which is the background of the invention, BiC.
Although the semiconductor device in which the MOS is formed has been described, the present invention can be applied to all semiconductor devices having a structure in which the element region must be thin.

[0021]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, the electrostatic withstand voltage of the input protection circuit formed in the semiconductor device having the BiCMOS structure is
The electrostatic withstand voltage is as high as that of the input protection circuit used in the structure.

[Brief description of drawings]

FIG. 1 is a plan view showing an input protection circuit portion of a semiconductor device according to the present invention.

FIG. 2 is a cross-sectional view of the semiconductor device taken along the line II-II of FIG.

FIG. 3 is a circuit diagram showing an equivalent circuit of an input protection circuit.

FIG. 4 is a cross-sectional view showing a state where a silicon nitride film is applied to a region other than a region corresponding to the n + buried layer of the semiconductor substrate in the manufacturing process of the semiconductor device of the present invention.

5 is a cross-sectional view showing a state in which an n + buried layer is formed by performing ion implantation on the semiconductor substrate 1 shown in FIG.

FIG. 6 is a cross-sectional view showing a state where the semiconductor substrate 1 shown in FIG. 5 is subjected to surface oxidation.

7 is a cross-sectional view showing a state in which the silicon nitride film of the semiconductor device shown in FIG. 6 is removed, a resist 44 is applied, and ion implantation is performed to form a p + buried layer.

FIG. 8 is a cross-sectional view of a semiconductor device showing a state where an n + buried layer and a p + buried layer are selectively formed on the surface of a semiconductor substrate.

FIG. 9 is a cross-sectional view of a semiconductor device having a conventional input protection circuit formed therein.

[Explanation of reference numerals] 2 p + buried layer 3 p well 4 n + diffusion layer 10 n channel MOS 20 bipolar transistor 22 n well

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Tatsuyuki Ota 2326 Imai, Ome City, Tokyo, Hitachi, Ltd. Device Development Center (72) Inventor Kazuyuki Miyazawa 2326 Imai, Ome City, Tokyo Hitachi, Ltd. Device Development In the center

Claims (3)

[Claims] 1. A plurality of buried layers are formed on a surface of a semiconductor substrate, and an n-well region and / or a plurality of buried layers are formed on the plurality of buried layers.
Alternatively, in a semiconductor device in which p-well regions are formed and CMOS transistors and / or bipolar transistors are formed in these n-well regions / or p-well regions,
In the region where the input protection circuit is formed, a buried layer is not formed and a well region formed of an epitaxial layer is formed directly on the substrate, and a semiconductor region of a conductivity type different from this is formed on the well region surface. An input terminal is connected to the semiconductor region, and a power supply voltage terminal is connected to the well region. 2. The semiconductor device according to claim 1, wherein the input protection circuit includes a MOS transistor and a bipolar transistor. 3. A plurality of n + -type impurity buried layers and / or p + -type impurity buried layers are formed on a surface of a semiconductor substrate, and an epitaxial layer is grown on the plurality of buried layers.
In the method of manufacturing a semiconductor device, which comprises forming an n-well region and / or a p-well region in the epitaxial layer and forming a CMOS transistor and / or a bipolar transistor in the n-well region and / or the p-well region, When forming the impurity-embedded layer and / or the p + -type impurity-embedded layer, a mask pattern is formed on the surface of the semiconductor substrate corresponding to the region where the input protection circuit is provided, and the mask pattern is used to p-type the semiconductor substrate. A method of manufacturing a semiconductor device, wherein a + type impurity and / or an n + type impurity is introduced to form a buried layer only in a portion other than an input protection circuit forming region.