JPH0566990A - Memory access control method - Google Patents

Abstract

PURPOSE:To provide the memory access control method for realizing a memory device which is light, thin and compact and enables high-speed access as well. CONSTITUTION:In the case of reading a DRAM, a DRAM controller reads the first four-bit data from the DRAM based on an instruction from a CPU by supplying RAS, CAS and A [R(m) and C(n)] so as to read data in a page mode cycle (S13) and these four-bit data are latch-outputted to the CPU by the DRAM controller (S14). Next, the second four-bit data are read by supplying A [C(p)] to the DRAM (S15) and latch-outputted to the CPU (S16).

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory access control method for a circuit using, for example, a DRAM.

[0002]

2. Description of the Related Art Conventionally, for example, in a memory circuit of a personal word processor or a personal computer,
It is generally often used to write and read data using a DRAM having a small capacity of about 256 kword × 4 bits (1 Mbit). In such a memory circuit, generally, a DRAM controller controls the DRAM based on an instruction from the CPU, and a CP
Data supplied from U or the like can be written or read.

FIG. 6 shows functional blocks of a DRAM access control circuit according to a conventional example.

This DRAM access control circuit is a CPU
1, a DRAM controller 2, and DRAMs 3 and 4.

This conventional example is a D-capacity of, for example, 256 kword × 4 bit (1 Mbit), which is currently in widespread use.
The purpose is to write or read 8-bit data supplied from the CPU 1 under the control operation of the DRAM controller 2 by using two RAMs. That is, since the DRAM itself fetches data with 4 bits for one address, 8-bit data supplied from the CPU 1 is divided into 4 bits, and the DRAM 3 and
4 are stored separately.

The CPU 1 supplies the DRAM controller 2 with a data write control signal (MEMWR), a data read control signal (MEMRD) and a clock (CLK).
Further, the address signal ADDR is supplied by 20 bits (A0 to A19). The data is transferred in 8 bits (D0 to D7). The CPU 1 writes data of, for example, 100 kword × 4 bits into the DRAMs 3 and 4, respectively. In addition, CPU1 is from the DRAM controller 2
When READY is supplied, for example, when it is a logic 0, it waits, and when it is a logic 1, it takes in data.

The DRAMs 3 and 4 are, for example, 256 kw
d × 4 bit (1 Mbit) memory, DRAM
The controller 2 supplies RAS (row address strobe signal), CAS (column address strobe signal), WE (write control signal), OE (output control signal), and address signals (A0 to A8). Further, the DRAMs 3 and 4 are D
Data (I / O 0-
Give and receive I / O 3). In this conventional example, as described above, the DRAMs 3 and 4 are each 100 kw.
Ord × 4 bit data is stored.

The DRAM controller 2 operates on the basis of control signals and data supplied from the CPU 1 to the DRAM 3,
4 is written in and data read from the DRAMs 3 and 4 is supplied to the CPU 1.

FIG. 7 shows a timing chart at the time of reading shown in FIG. The control operation of the DRAM controller 2 at the time of reading data will be described with reference to this timing chart.

In FIG. 7, 8-bit data is supplied from the CPU 1 and divided into 4 bits each, and the DRAM 3,
In the state of being stored in 4, when reading, based on the MEMRD from the CPU 1, the DRAM controller 2
During one bus cycle of CPU1, WE is kept at high level, RAS is changed from high level to low level (FIG. 7 (a)), and row (ROW) address signals (A0 to A8) are supplied to DRAMs 3 and 4 at that time. ((C) of FIG. 7). Next, the CAS is changed from the high level to the low level (FIG. 7 (b)), and at that time, the column (COLOUMN) address signals (A0 to A8) are sent to the DRAM.
It is supplied to 3 and 4 (FIG. 7 (c)). Since the row address signal and the column address signal are supplied to the DRAMs 3 and 4, D
The RAM controller 2 is an OE for the DRAMs 3 and 4.
Is changed from high level to low level (FIG. 7 (g)).
In this state, the DRAMs 3 and 4 can read out data from the designated addresses by 4 bits (FIGS. 7D and 7E). Each 4-bit data thus read is supplied to the DRAM controller 2. The supplied data is 8-bit data (D0 ~ D7)
1 (FIG. 7 (f)). At this time, READY is changed from low level to high level to capture data (FIG. 7 (i)). The CPU 1 takes in the data supplied at the rising edge of the clock (FIG. 7 (j)).

[0011]

However, in the above-mentioned conventional memory access control method, the small capacity of 256 kbit × 4 bit (1 M
Two bit) DRAMs are used to read or write 8-bit data from the CPU.
The amount of data stored in RAM3, 4 is 100 for each DRAM.
Even if it is kword × 4 bits, it is necessary to use two of them, and improvement has been required in order to realize a light, thin, short and small memory device. For example, an 8-bit × 256 kword (2 Mbit) DRA in which one address can be written in 8 bits
If there is M, in the case of FIG. 5, it can be realized with one DRAM, but DR of 8 bits × 256 kword (2 Mbits)
AM is not popular. Also 8bit × 256kwo
When an rd (2 Mbit) DRAM is adopted, a large memory capacity of 8 bits × 256 kwords is stored in order to store the small capacity (800 kbit = 100 kword × 4 bit × 2) data as described above.
The DRAM of (2 Mbit) is selected, and the usage rate of the memory is reduced.

In the configuration shown in FIG. 5, when the data supplied from the CPU is composed of 16 bits,
There is a problem that the hardware scale becomes larger and larger because four 256kword × 4bit DRAMs are required.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a memory access control method for realizing a memory device which is light, thin, short, and small and which can be accessed at high speed. That is.

[0014]

In order to achieve the above object, the present invention performs control so that input data is written in a memory or data stored in a memory is read in a page mode cycle. The memory access control method has been improved by the following characteristic means and methods.

That is, the data bit number A of one address of the input data is the data bit number B of one address of the memory.
If N is a natural number, then a separation unit that divides input data whose one bit is A bits into B bit data units and outputs it, and N pieces of data input from the memory in B bit data units are In the case of writing the data into the memory by including a synthesizing unit for outputting as A-bit data, N B-bit data in B-bit data units output from the dividing unit are stored in the memory during one page mode cycle. When writing to and reading data from memory,
From the memory, in units of B-bit data, N B-bit data are read from the memory during the one-page mode cycle, and the synthesizing means outputs 1 corresponding to one address.
It is characterized in that a plurality of A-bit read data are output.

[0016]

According to the present invention, the number of bits of the input data A
Is N times the number of bits B of one address of the memory, the page mode cycle function of the memory is used for writing or reading data. The bit input data D0 to D7 is divided into two and divided into 4-bit data units (D
0 to D3: lower data and D4 to D7: upper data),
During the one-page mode cycle, it is possible to sequentially write two 4-bit data of lower data and upper data. When reading the data written in the memory, for example, the first 4-bit data (lower data) is read during the one-page mode cycle, and then the second 4-bit data (upper data) is read. Read
Two pieces of read data can be combined and output as one piece of 8-bit data.

Since data can be written or read in this way, a small number of memories can be effectively used, which contributes to the lightness, thinness, shortness of hardware, and a page mode cycle. Since it is used, the access speed can be higher than that of normal data read or write.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A preferred embodiment of the memory access control method of the present invention will be described with reference to the drawings.

This embodiment uses one DRAM 6 of a small capacity, for example, 256 kword × 4 bits, which can access data in a page mode cycle, and uses the control operation of the DRAM controller 5 to control the CP.
The purpose is to write or read 8-bit data supplied from U1. That is, the DRAM itself fetches 4-bit data for one address, but 8-bit data supplied from the CPU 1 is stored or read in the DRAM 6 in 4-bit page mode cycles.

FIG. 1 is a read control operation flowchart of this memory access control method, and FIG. 2 is a write control operation flowchart. The description of FIGS. 1 and 2 will be made in detail after the functional blocks of the memory access control circuit of FIG. 3 are shown.

FIG. 3 shows functional blocks of a memory access control circuit to which the memory access control method according to FIGS. 1 and 2 is applied.

This memory access control circuit is, for example, C
It is composed of a PU 1, a DRAM controller 5, and a DRAM 6.

The CPU 1 supplies the DRAM controller 5 with a data write control signal (MEMWR), a data read control signal (MEMRD), and a clock (CLK).
Further, the address signal ADDR is supplied by 20 bits (A0 to A19). The data is transferred in 8 bits (D0 to D7). The CPU 1 stores in the DRAM 6, for example, 200 kword × 4b
The data of it shall be written. Further, the CPU 1
When READY is supplied from the RAM 2, for example, when it is a logic 0, it stands by, and when it is a logic 1, it fetches data.

The DRAM 6 is, for example, 1 Mbit (256 kword ×
It is a memory that can write or read data in a page mode cycle of about 4 bits. An example of such a DRAM is μPD424256LA manufactured by NEC Corporation. The DRAM controller 5 also supplies RAS (row address strobe signal), CAS (column address strobe signal), WE (write control signal), OE (output control signal), and address signals (A0 to A8). Furthermore, the DRAM 6 is a DRA
Data (I / O 0 to I / O 3) is exchanged with the M controller 5. In this embodiment, as described above,
The DRAM 6 stores 200 kword × 4 bit data.

The DRAM controller 5 writes data to the DRAM 6 in a page mode cycle based on a control signal and data supplied from the CPU 1 and also D
The data read from the RAM 6 in the page mode cycle is controlled to be supplied to the CPU 1. A memory access control method for writing and reading by the DRAM controller 5 is shown in FIGS.

Next, the operation at the time of reading data will be described with reference to the control operation flowchart at the time of reading in FIG. 1 and the operation timing chart at the time of reading in FIG.

The DRAM controller 5 is supplied with MEMRD, CLK, and ADDR from the CPU 1 (see FIG. 1).
S10). Next, the DRAM controller 5 makes READY inactive (changes from high level to low level) and supplies it to the CPU 1 (FIG. 1S1).
1), (FIG. 4 (i)). When READY is inactivated, the CPU 1 goes into a standby state. The DRAM controller 5 makes the OE active (changes from a high level to a low level and enables output, that is, an active state) and supplies it to the DRAM 6 (S1 in FIG. 1).
2).

Next, the DRAM controller 5 is a DRAM
In order to read the data from 6 in the page mode cycle, RAS is first changed from high level to low level (that is, active state) (FIG. 4 (a)), and at the same time, the row address A (R (m)) is supplied. (FIG. 4C), then CAS is changed from the high level to the low level (that is, in the active state) (FIG. 4B), and at the same time, the column address A (C (n)) is supplied to the DRAM 6 ( Figure 4
(C)), FIG. 1S13).

In this state, the DRAM 6 has the address A (R
(M) and C (n)) output the first data (FIG. 4 (d)), and the DRAM controller 5
Bit output data (I / O 0 to I / O 3) is taken in and output data (DO 0 to DO) for the CPU 1 is fetched.
3: LSB is output as the lower data) while OE is active (FIG. 4E) (FIG. 1S14).

Next, the DRAM controller 5 changes the CAS from the low level to the high level (that is, the non-active state) while keeping the RAS at the low level, and then changes it to the low level (that is, the active state) again. (FIG. 4B), the column address A (C
(P)) is supplied to the DRAM 6 (FIG. 4C), and FIG.
S15). In this state, RAS is the first address A
Since the low level is held from (R (m), C (n)), D is set at the second address A (R (m), C (p)).
The RAM 6 reads data (FIG. 4 (d)).

During the one-page mode cycle, RAS is
Continue low level. The 4-bit data (I / O 0 to I / O 3) read here is supplied to the DRAM controller 5 and output data DO 4 to DO 7 (upper data) while the OE is active with respect to the CPU 1.
Is output as a latch (FIG. 4 (f)) (S16 in FIG. 1).
Here, since DO 0 to DO 3 have already been latched and output in S14 described above, therefore, 8-bit data is stored in the CPU.
1 can be supplied. In this state, the DRAM controller 5
Makes READY active (changes from low level to high level) to the CPU 1 (FIG. 4 (i)) (S17 in FIG. 1) to output data DO 0 to
The DO 7 can be taken in by the CPU 1. Next, the DRAM controller 5 determines whether to read the next data based on the command from the CPU 1 (FIG. 1S).
18). If a data read command is supplied from the CPU 1, the operations of S10 to S17 of FIG. 1 are performed again.

In this way, the DRAM 6 is set in units of 4 bits.
The data written to the DRAM controller 5
Controls the page mode cycle function so that the data read out twice is latched and output, and when 8-bit data is collected, the CPU is loaded.

Next, the data write operation will be described with reference to the write operation control flow chart of FIG. 2 and the write operation timing chart of FIG.

The DRAM controller 5 receives MEMWR, CLK, and ADDR from the CPU 1 (FIG. 2S).
19). Next, the DRAM controller 5 makes READY inactive (changes from high level to low level) and supplies it to the CPU 1 (S20 in FIG. 2).
(FIG. 5 (i)). Next, the DRAM controller 5
WE active (write command) is supplied to AM6 (FIG. 5 (h)) (FIG. 2S21). Next, the DRAM controller 5 uses the RAS, CAS and address A (R (m), C
(N)) is supplied to the DRAM 6 (FIGS. 5A and 5B).
(C)) (FIG. 2S22).

The DRAM 6 is set to 1 when the RAS changes from the high level to the low level (that is, becomes active).
The page mode cycle starts and the address A (R
(M)) is taken in, and when CAS changes from a high level to a low level (that is, an active state), an address A (C (n)) is taken in. The one-page mode cycle is continued until RAS changes from the low level (active state) to the high level (non-active state).

When the address A (C (n)) is fetched into the DRAM 6, the DRAM controller 5 then causes the CPU
Receive data D0 to D7 from 1 (FIGS. 5 (e) and (f))
(FIG. 2 S23) Next, the DRAM controller 5
The D0 to D3 are supplied to the I / O0 to I / O3 of the AM6 and written to the address A (R (m), C (n)) (FIG. 5 (d)) (FIG. 2S24). Next, in order to write the data D4 to D7 in the p column of the same row m, the DRAM controller 5 once sets the CAS to the high level, changes it to the low level again, and supplies it to the DRAM 6 (FIG. 5B).
The address A (C (p)) is supplied to the DRAM 6 (see FIG. 5).
(C)) (FIG. 2S25).

Next, of the data D0 to D7 already supplied from the CPU 1, the remaining data D4 to D7 of the write in S24 are supplied to I / O0 to I / O3 of the DRAM 6 (see FIG. )), The address A (R of the DRAM 6
Data D4 to D7 are written in (m) and C (p) (S26 in FIG. 2). In this way, when the data D0 to D7 are written in two times, RAS, CAS, and WE are changed from low level to high level, and the data writing during the one-page mode cycle is completed. Next, the DRAM controller 5 activates READY (changes from the low level to the high level) to the CPU 1 so that the data can be taken in (S27 in FIG. 2). Next, it is judged whether or not the data writing is continued (S2 in FIG. 2).
8) If it is continued, the processes of S19 to S27 of FIG. 2 are executed again.

As described above, using the page mode cycle function, one address of 8-bit data supplied from the CPU 1 is used, and one DRAM 6 of 256 kword × 4 bit capacity in which one address is composed of 4 bits is used. Then, the data can be converted into 200 kword × 4 bit data and written.

As described above, according to this embodiment, the DR of 256 kword × 4 bit (1 Mbit)
According to the conventional example using AM, two are required, but 1
Data can be written or read individually.
Further, since the page mode cycle is used for the access, the access can be performed at a higher speed as compared with the normal read or write. Therefore, it is possible to realize a lighter, thinner, shorter, and smaller memory device as compared with the conventional example, and it is possible to improve the usage rate of the DRAM.

In the above embodiment, 8-bit data for one address is supplied from the CPU, and the 8-bit data is written in 4-bit data unit in order to write this into the DRAM in which 1 address is composed of 4 bits. Although the data is divided and the two divided 4-bit data is written during the one-page mode cycle, the number of bits of data supplied from the CPU is N (natural number) of the number of bits of one address of the DRAM. ) If applicable, it can be applied using page mode cycles. For example, if the data from the CPU is 16-bit data, a DRAM having a 4-bit configuration for one address is used to divide the data into 4-bit data units in units of 4-bit data.
It can be written and stored once. In addition, the stored data is read four times in sequence during the one-page mode cycle, and the read data is combined to obtain 1
The 16-bit data can be provided to the CPU as 16-bit data.

The number of bits of one address of DRAM is not limited to 4 bits.

In the above embodiments, the low level is the active state and the high level is the non-active state, but the present invention is not limited to this state.

In the above embodiment, the input data and the instruction are supplied from the CPU, but the present invention is not limited to this. Although output data and control signals are also supplied to the CPU, the present invention is not limited to this.

[0044]

As described above, according to the present invention, a small number of memories can be effectively used.
It is possible to contribute to the lightness, thinness, shortness and smallness of the hardware, and since the page mode cycle function is used, the access speed can be higher than that of normal data read or write.

[Brief description of drawings]

FIG. 1 is a read control operation flowchart of a memory access control method according to this embodiment.

FIG. 2 is a write control operation flowchart of a memory access control method according to this embodiment.

FIG. 3 is a functional block diagram of a memory access control circuit according to FIGS. 1 and 2.

FIG. 4 is a memory access control timing chart at the time of reading according to FIG.

FIG. 5 is a memory access control timing chart at the time of writing according to FIG.

FIG. 6 is a functional block of a memory access control circuit according to a conventional example.

7 is a memory access control timing chart at the time of reading according to FIG.

[Explanation of symbols]

 1 CPU 5 DRAM controller 6 DRAM

Claims (1)

[Claims] 1. A memory access control method for controlling input data to be written in a memory or reading data stored in a memory in a page mode cycle, wherein the number A of data bits of one address of input data is , When the number of data bits B of one address of the memory is N (natural number) times, a separation means for dividing input data of 1 bit of A bit into B bit data units and outputting it, and from the memory in B bit data units. When the data is written to the memory by including a combining unit that outputs N pieces of input data into one piece of A bit data and outputs the N pieces of B bit data in B bit data units output from the dividing section. When writing data to the memory during the 1-page mode cycle and reading data from the memory, Memory access control, wherein N pieces of B-bit data are read from the memory during one page mode cycle, and one piece of A-bit read data is output corresponding to one address by the combining means. Method.