JPH0566729B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a semiconductor device having a wiring structure in which a wiring route network can be configured to have an arbitrary impedance ratio.

(Background of the Invention) In a semiconductor integrated circuit, the length of wiring connecting circuit elements naturally varies in length, creating a plurality of wiring route networks with different impedances.

FIGS. 1a and 1b are diagrams respectively showing two wiring route networks having different wiring lengths and their equivalent circuits. This is the simplest example, but the wire length from point A to point B is greater than the wire length from point A to point B.
Since AC is longer, a difference Rb<Rc also occurs between the respective wiring resistances Rb and Rc as seen from point A. Assuming that current I ₀ flows from points B and C toward point A in such a wiring route network, a potential difference equivalent to I ₀ (R _c - R _b ) will occur between points B and C. I will do it. In analog circuits, this potential difference disturbs the balance of the differential amplifier circuit, significantly degrades the circuit function by causing malfunctions, generation of shock-on noise, and deterioration of distortion rate.

As described above, in analog semiconductor integrated circuits, there are often cases where the difference in impedance due to the length of the wiring cannot be ignored. In order to equalize the impedance of two wiring route networks with different wiring lengths, it is possible to make the wiring width of the longer wiring wider and the shorter wiring narrower, but this poses a new problem in terms of mass production technology. to be born.

FIG. 2 shows a conventional wiring structure diagram of two wiring route networks with different wiring widths, each of which corresponds to the one shown in FIG. In this wiring structure, the line width of the wiring length is made thin and the line width of the wiring length is made thick. However, in this wiring structure, if other circuit wirings 1, 2, and 3 exist in the vicinity, wiring portion lengths 4, 5, and 6 that are less than the specified width are created, as shown by the dotted lines, respectively.
It will have a complex pattern.

From the viewpoint of mass production technology of semiconductor devices, it is essentially not desirable to have wiring route networks having various line widths laid out on one semiconductor substrate surface. This is because wires with narrow line widths are more affected by etching accuracy and patterning accuracy than thick wires. In other words, if you try to simultaneously form, for example, a thin line with a line width of 7 to 8 μm and a thick line with a line width of about 20 μm on one semiconductor substrate, both of the two lines will overlap with the line on the mask due to variations in etching and patterning. The line width is deviated from the line width. However, the ratio of the deviation width to the wiring width on the mask has a much larger value for a thin wiring with a line width of 7 to 8 μm than for a thick wiring with a line width of 20 μm. This tendency is further accelerated when the field oxide film has a step difference. Therefore, the wiring structure shown in FIG. 2, in which the wiring impedances are mutually corrected by varying the wiring widths, is undesirable because it causes large variations in the wiring impedance matching when mass-producing semiconductor devices. In a normal analog semiconductor integrated circuit,
As mentioned above, in addition to impedance matching between two wiring path networks, which originates from the offset problem of differential amplifiers, it is necessary to configure multiple wiring path networks with different wiring lengths with arbitrary impedance ratios. Therefore, it is strongly desired to realize a mass-produced wiring structure that is not affected by variations in etching and patterning.

(Object of the Invention) An object of the present invention is to provide a semiconductor device having a mass-produced wiring structure that can configure a plurality of wiring route networks having different wiring lengths to have an arbitrary impedance ratio.

(Structure of the Invention) In the semiconductor device of the present invention, at least one of the wiring route networks having a long wiring length on a field insulating film has a plurality of wirings whose line widths are equal to those of other wiring route networks having a short wiring length. It is formed by connecting two wiring paths in parallel.

(Effects of the Invention) According to the present invention, a wiring path network with a long wiring length on a field insulating film is formed including a parallel circuit consisting of a plurality of wiring paths. On the other hand, it is possible to freely set the impedance to be equal or to set the impedance to a specified ratio. In addition, each of the wiring paths connected in parallel is set to have the same line width as that of the other short wiring route network as a reference, so the wiring width on the mask due to etching and patterning accuracy is It can be formed by making the deviation ratios equal. Therefore, it is possible to dramatically improve the mass production yield of semiconductor devices. The present invention will be described in detail below with reference to the drawings.

(Explanation of Embodiment) FIG. 3 is a wiring structure diagram showing an embodiment of the wiring path network in the semiconductor device of the present invention.
Contains two wiring path networks. In this embodiment, the wiring route network with a long wiring length is formed by parallel connection of three wiring paths whose line widths are equal to the route wiring width W of the wiring route network with a short wiring length, and the impedance is equal to that of the short wiring length. is set to have . Therefore, the impedances seen from point A to points B and C are equal, and no offset voltage as in FIG. 1a is caused by the wiring. In addition, since the line widths of the wiring that form the two wiring route networks are all the same, they are uniformly affected by variations in etching and patterning, making it possible to mass-produce while maintaining an almost exactly 1:1 impedance ratio between the two. It is. Of course, the number of wiring paths connected in parallel can be arbitrarily selected.

Further, FIGS. 4, 5, 6, and 7 are wiring structure diagrams showing other embodiments of the wiring route network according to the present invention. FIG. 4 shows a wiring structure in which the impedances of points B, C, and D as seen from point A are set equal under the presence of wiring that does not require impedance matching, and FIG. 4 shows a wiring structure in which the wiring structure of FIG. 4 cannot be used because the wiring of another circuit is wired nearby. In this way, instead of making the entire route wiring width equal, only a portion thereof may be formed as a parallel connection line. Further, FIG. 6 shows an example in which the wiring route network having a short wiring length is intentionally detoured to lengthen the wiring length instead of extending straight as shown by the dotted line. In this way, it is possible to select the wiring structure with the most appropriate line width by considering the wiring lengths of both wiring route networks. This wiring structure is effective when the impedance ratio between the two is arbitrarily set. In addition, FIG. 7 shows the dummy wiring 10,
11 or other circuit wiring 12, 13 and 14
This shows a wiring structure in which the wires are placed along the vicinity, and the influence on impedance fluctuations due to variations in etching and patterning can be further reduced.

As explained in detail above, the semiconductor device of the present invention reduces the effects of etching and patterning accuracy, and can be mass-produced by setting the wiring impedance to an arbitrary ratio. It can be very effective in

[Brief explanation of the drawing]

Figures 1a and b are diagrams showing two wiring route networks with different wiring lengths and their equivalent circuits, respectively; Figure 2 is a conventional wiring structure diagram of two wiring route networks with different wiring widths; FIG. 3 is a wiring structure diagram showing one embodiment of the wiring path network in the semiconductor device of the present invention, and FIGS. 4, 5, 6, and 7 show one example of the wiring path network in the present invention. FIG. ,,,... Wiring length of wiring route network,
R _b , R _c ... Wiring resistance, I ₀ ... Circuit current, 1, 2,
3, 7, 8, 9, 12, 13, 14...Other circuit wiring, W...Reference wiring width, 10, 11...Dummy wiring.

Claims (1)

[Scope of Claims] 1. In a semiconductor device having a first wiring path with a short wiring length and a second wiring path with a long wiring length connected in series to the first wiring path, the second wiring path 1. A semiconductor device comprising: a plurality of interconnects having a line width equal to that of the first interconnect path connected in parallel, and impedance matched with the first interconnect path. 2. Claim 1, which comprises a wiring path in which parallel-connected wirings are arranged at equal intervals, and dummy wiring or other circuit wiring path is provided outside the wiring path at intervals equal to the spacing between the wirings. 1. Semiconductor device described in Section 1.