JPH056455A - Pulse noise eliminating circuit - Google Patents

Abstract

PURPOSE:To eliminate the noise of a void, a spot, or the like by selecting one data line by the majority logic of parallel signals to set a maximum noise width in accordance with the size of a bar code different in size. CONSTITUTION:A shift register 1 which takes one-dimensional serial digital data as the input and outputs the result of shift operation in parallel synchronously with a reference clock and a multibit output digital memory 2 which has address lines connected to respective parallel outputs of the shift register 1 to constitute a majority logic gate are provided. A circuit consists of a data selector 3 which selects one data line from outputs of the digital memory 2 and a data latch 4 where the memory output of one data line selected by the data selector 3 is held synchronously with the reference clock.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pulse noise removing circuit suitable for use in a bar code reader.

[0002]

2. Description of the Related Art In recent years, bar codes have been used for inventory management for most of commercial products. This bar code is made up of a combination of thin lines, thick lines, and the number of lines, and is printed or attached to the surface of a product or the like. This bar code is generally read using a bar code scanner using infrared rays. In a register used in a retail store such as a supermarket, a stationary bar code reader is often used, but an accurate reading is required because money is dealt with a customer. In this type of barcode reader, due to the stains and scratches on the barcode, black on a white background called "void" or "spot",
Or white noise is mixed in on a black background. If you scan the barcode data containing such noise with a scanner,
There is a risk that the reading rate will decrease or that the data will be misread. Therefore,
In order to remove this noise, it is possible to provide a noise removing means.

As a means for this, for example, a configuration using majority logic has been proposed. This method is a shift register that shifts input one-dimensional serial digital data in synchronization with a reference clock and outputs a signal in parallel, and a majority logic that inputs the parallel output of the shift register through an address line. A data memory having a gate structure and a data latch that holds the output of the digital memory in synchronization with the reference clock are provided.

[0004]

However, in the above-mentioned prior art, since the number of inputs of the majority decision is fixed, the size of the noise width that can be removed is determined. In addition, the allowable range of the size of the barcode symbol output from the scanner is 0.8 to 2.828 times the standard value,
The bar width further changes from 1.0 to 1.414 times depending on the angle between the bar direction and the scanning locus of the scanner, and the bar code image data output from the scanner is 1 after all.
Module width (the narrowest bar width) is 0.8 to the standard value
It exists up to 2.0 times. Ideally, the size of the noise width that can be removed should also change according to the size of each image data, but at present, this problem has not been solved.

Therefore, an object of the present invention is to provide a pulse code capable of setting the maximum noise width for bar codes of various sizes and removing noises such as voids and spots. It is to provide a noise removing circuit.

[0006]

In order to achieve the above object, the present invention provides a shift register which receives one-dimensional serial digital data as input and outputs in parallel the result of a shift operation in synchronization with a reference clock. A multi-bit output digital memory in which an address line is connected to each of the parallel outputs of the shift register to form a majority logic gate; and a data selector that selects one data line from the outputs of the digital memory, A data latch for holding the memory output of one data line selected by the data selector in synchronization with the reference clock is provided.

[0007]

According to the above means, a 1-bit shift operation is performed inside the shift register each time image data containing noise is captured, and the parallel output is programmed by the result of the majority logic in various input numbers L. The pulse noise in the image data is removed by being applied to the address line of the digital memory which is the M-input majority logic gate. Therefore, pulse noises such as voids and spots can be appropriately removed from the input signal according to the size of the barcode label, and reading accuracy can be improved and erroneous reading can be reduced.

[0008]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing an embodiment of a pulse noise removing circuit according to the present invention. Address lines 1 to M of a digital memory (ROM: read only memory) 2 are connected to a shift register (SIPO-SR) 1 that receives one-dimensional serial digital data and outputs a parallel output signal. .. The digital memory 2 is provided with multi-bit memory outputs, and a data selector (DS) 3 for selecting one bit data from these is connected. A data latch (LAT) 4 for holding the memory output of the selected data line in synchronization with the reference clock is connected to the digital memory 2.

Next, the operation of the embodiment having the above configuration will be described with reference to the timing chart of FIG. In the figure, N is pulse noise, S is the original signal without noise,
RC indicates a character bit reading clock, and S + N indicates actual image data mixed with pulse noise. Further, "1010" is a part of the character bit string, and the length of the waveform for one bit of the character bit is one module.

Actual image data (S + N) from the bar code scanner is fetched into the serial input / parallel output type shift register 1 in synchronization with the reference clock CLK. Every time the image data (S + N) is fetched, a 1-bit shift operation is performed inside the shift register 1. The M (odd) parallel outputs of the shift register 1 are connected to the address lines of the digital memory 2 which constitutes the M-input majority logic gate, and remove the pulse noise in the image data. The number of inputs M is set to 2/3 or less of the number of clocks per module.

In the digital memory 2, when the image data passes through this gate, it is possible to remove even noise pulses having a maximum (M-1) / 2 clock width. That is, in the digital memory 2, if the noise component is 2 bits or less in the majority logic of 5 bits, for example, "00011" becomes "0" by the majority logic and the noise is removed. Although briefly described here for convenience of description, inside the memory of the actual digital memory 2, the result of the majority logic in various input numbers L is programmed by the contents of the address portion shown in FIG. The results are simultaneously output in parallel to the data section. Therefore, on the hardware, M data lines are connected to the memory, and the number of majority logic inputs L
Can be changed (odd) up to M, so (L-1) / 2
It is possible to remove noise pulses having a clock width of. Furthermore, according to the 1-module width data recognized by the decoder in real time by the data selector 3,
One of J is immediately selected by the SEL signal.
The selected result is held in the data latch 4 in synchronization with the reference clock CLK, and its output is pulse noise N
Becomes the bar code image data S '.

FIG. 4 is an explanatory view showing a noise pulse elimination situation when the pulse noise N exists apart from the level change point of the original signal S. As is clear from FIG. 4, (L-
It can be seen that the noise pulse of 1) / 2 is completely removed.

FIG. 5 is an explanatory diagram showing a noise pulse elimination situation when the pulse noise N is near the level change point of the original signal S. In this case, a square wave including an error is generated only in the time of the noise width, but the noise itself can be removed. Therefore, the character bit string signal of the bar code is passed through the pulse noise removing circuit of FIG. (RC) can be correctly transmitted to the decoder. In the above description, the application to the bar code decoder is described as an example, but the present invention is not limited to this and can be applied to all digital data including pulse noise.

[0014]

As described above, according to the present invention, a one-dimensional serial digital data is input, a shift register for outputting a result of a shift operation in synchronization with a reference clock and a parallel output of the shift register. A multi-bit output digital memory in which an address line is connected to each output to form a majority logic gate, a data selector that selects one data line from the outputs of the digital memory, and a data selector that is selected by the data selector Since a data latch that holds the memory output of one data line in synchronization with the reference clock is provided, pulse noise such as voids and spots can be removed from the input signal, which improves reading accuracy. It is possible to reduce erroneous reading.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a pulse noise removing circuit according to the present invention.

FIG. 2 is a timing chart showing the operation of the embodiment of the present invention.

FIG. 3 is an explanatory diagram showing a process of majority logic in a digital memory.

FIG. 4 is an explanatory diagram showing a noise pulse removal situation when pulse noise N exists apart from a level change point of an original signal S.

FIG. 5 is an explanatory diagram showing a noise pulse elimination situation when the pulse noise N is near the level change point of the original signal S.

[Explanation of symbols]

 1 shift register 2 digital memory 3 data selector 4 data latch CLK reference clock

Claims (1)

Claim: What is claimed is: 1. A shift register that receives one-dimensional serial digital data as an input and outputs a result of performing a shift operation in synchronization with a reference clock, and a parallel output of the shift register. A multi-bit output digital memory that is connected to an address line to form a majority logic gate; a data selector that selects one data line from the output of the digital memory; and one data selector that is selected by the data selector. And a data latch that holds a memory output of a data line in synchronization with a reference clock.