JPH0564146A - Digital video signal recording and reproducing device - Google Patents

Abstract

PURPOSE:To reduce the scale of the circuit for recording and reproduction when a digital video signal is recorded/reproduced to/from a magnetic tape wound onto a circumferential face of a rotary drum at an angular range of 180 deg. or over with a magnetic head. CONSTITUTION:Four channels of magnetic heads in total eight heads are fitted to a rotary drum while being opposite to each other at an interval of 180 deg. and a magnetic tape is wound onto a circumferential face of a rotary drum at an angular range of 270 deg.. A circuit 44 applies time division multiplex to 2-channel data to form 4 signals. The signal is subject to digital recording processing in circuit blocks 53A-53D and 8-channel recording data whose phase is coincident with a recording phase by a magnetic head are generated from an output side FIFO memory.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital video signal recording and reproducing apparatus, and more particularly to a digital VTR using a rotary head and a magnetic tape.

[0002]

2. Description of the Related Art In a conventional analog VTR, a pair of magnetic heads are attached to a rotating drum at angular intervals of 180 °, and a magnetic tape is wound around the drum's peripheral surface in a range of about 180 °. The magnetic tape is fed at a constant speed, the magnetic head alternately scans the magnetic tape, and video signals are recorded as diagonal tracks. In this way, since the tape winding angle is about 180 °, the periods in which the magnetic head scans the tape do not overlap in terms of time, and therefore one system of recording / reproducing circuit may be provided.
The circuit scale does not increase.

Recently, in a digital VTR which records and reproduces a video signal in the form of a digital signal, since the data amount of the digital video signal is large, a plurality of tracks are generally formed by one scan of the magnetic head. A multi-channel method that forms simultaneously is adopted. Regarding the digital VTR, a case where the tape winding angle is 180 ° and a case where the tape winding angle is 270 ° are compared and examined. As an example, assume a case where data of 600 Mbps is recorded by a magnetic head of 8 channels in total, which is opposed to 4 channels. Each parameter in this case can be calculated as follows.

As described above, the drum diameter can be reduced by increasing the winding angle. As a result, not only can the device be made smaller and lighter, but it is also possible to reduce spacing loss and tape damage due to a decrease in relative speed. However, the reduction of the centrifugal force facilitates the mounting of the movable head. Further, since the recording rate is lowered, the efficiency of the rotary transformer and the magnetic head is increased, which is advantageous in high density recording. A conventional digital VTR having a winding angle of 270 ° will be described. FIG. 5 shows a circuit configuration for recording. The luminance signal Y and the color difference signals PB and PR which are components of the color video signal are converted into digital signals by the A / D converters 1, 2 and 3. A / D
The sampling clock CK1 supplied to the converter 1 is
For example, the frequency Fs is 37.5 MHz, and the frequency of the sampling clock supplied to the A / D converters 2 and 3 is one half thereof. Therefore, the A / D converter 2
The data amount of the digital color difference signals from and 3 is half that of the luminance signal. The sampling rate of the data obtained by summing the digital data from the A / D converters 1, 2, 3 is 2Fs.

The output signals of the A / D converters 1, 2, 3 are supplied to the head interleave circuit 4. As shown in FIG. 6, eight magnetic heads 14A to 14H are attached to a drum 13 rotating at 150 Hz (five times the frame frequency). The magnetic tape 1 is diagonally attached to the peripheral surface of the drum 13.
5 is wound at a winding angle θ (for example, θ = 270 °). The magnetic heads 14A, 14B, 14C and 14D are arranged close to each other, and four tracks are simultaneously formed on the magnetic tape 15 by these four magnetic heads. Four magnetic heads 14E to 14H are attached to the drum 13 in close proximity to the magnetic heads 14A to 14D at an angular interval of 180 °. Magnetic heads 14E-14
By H, four tracks are simultaneously formed on the magnetic tape 15. The magnetic tape 15 is fed at a constant speed by a tape feeding mechanism (not shown).

The head interleave circuit 4 in FIG.
In order to form the data to be recorded by each magnetic head, the digital component signal is divided into signals of 8 channels A to H. In FIG. 7, as indicated by S1, the output signal of the head interleave circuit 4 is parallel 8
This is channel data, and the sampling frequency of each channel is (2Fs / 8 = 1 / 4Fs). The channel A signal is supplied to the outer code encoder 5. As a countermeasure against errors that occur during the recording and reproducing processes, data is error-correction coded by both the outer code and the inner code. More specifically, the outer code is encoded in the vertical direction of the matrix array of a predetermined amount of data, and the inner code is encoded for each sync block in the horizontal direction.

The output data of the encoder 5 is supplied to the shuffling circuit 6. The shuffling circuit 6 performs shuffling for rearranging the data of one channel in one field in an order different from the original order, and is configured by a memory. The shuffling prevents a burst of errors from causing data that is temporally continuous to be aggregated into an error and enables good error correction. A write clock CKW and a read clock CKR are supplied to the shuffling circuit 6, and desired shuffling is performed by address control of the memory. At the same time, the frequency of the clock CKW is set to 1 / 4Fs and the frequency of the clock CKR is set to 1 / 3Fs. As a result, the output data of the shuffling circuit 6 is time-axis compressed to 3/4 of its input data. Further, the reading of data from the shuffling circuit 6 coincides with the phase in which the magnetic head of the corresponding channel A records data on the magnetic tape.

The output signal of the shuffling circuit 6 is supplied to the ID addition circuit 7, and the ID signal for control is added. I
The output signal of the D addition circuit 7 is supplied to the inner code encoder 8 to encode the inner code. The output signal of the inner code encoder 8 is supplied to the sync addition circuit 9. The recording data is divided by sync blocks, and the video data in the sync blocks, the parity of the error correction code, and the ID signal are encoded by the inner code. Recording data having a sync block structure is generated from the sync addition circuit 9, and this recording data is supplied to the channel encoder 10. The channel encoder 10 performs channel coding to reduce the DC component. The output signal of the channel encoder 10 is supplied to the parallel / serial conversion circuit 11. Serial recording data is supplied from the parallel / serial conversion circuit 11. Although not shown, this recording data is supplied to the magnetic head 14A via a recording amplifier.

As shown in the broken-line blocks 12B to 12H, the circuit configurations related to the channel A from the outer code encoder 5 to the parallel / serial conversion circuit 11 are the other B to H.
Are provided for each channel. The recording data from the blocks 12B to 12H is the magnetic head 14B.
To 14H are respectively supplied via a recording amplifier. The time axis compression is performed by the shuffling circuit 6 and the shuffling circuits in the circuit blocks 12B to 12H, and the reading of data from the memory coincides with the recording phase of the corresponding magnetic head. Therefore, the shuffling circuit 6
And the data S2 in FIG. 7 is generated at the outputs of the respective shuffling circuits of the circuit blocks 12B, 12C, 12D, and the circuit blocks 12E, 12F, 12G,
The output of each shuffling circuit of 12H is shown in FIG.
Inside data S3 is generated.

In FIG. 7, T is a cycle T of one rotation of the drum 13 (= 1/150 seconds), and the winding angle θ is 2
Since the magnetic heads 14A to 14D are scanning the magnetic tape 15, since the magnetic heads 14A to 14D are set at 70 °, the channels A to
The recording data of D is recorded as four tracks, and then the recording data of channels E to H is four tracks during a period in which the magnetic heads 14E to 14H are scanning the magnetic tape 15 with a delay of 1 / 2T. To be recorded.

A conventional reproducing circuit for reproducing the data recorded as described above will be described with reference to FIG. Channel A by magnetic heads 14A-14H
Although not shown, the reproduced data of ~ H are supplied to the channel code decoder through the reproducing amplifier. The reproduced data of channel A from the channel code decoder is PLL2.
1 is supplied. The PLL 21 extracts the clock required for the processing of the reproduction circuit from the reproduction data. The output signal of the PLL 21 is supplied to the serial / parallel conversion circuit 22. series/
The output signal of the parallel conversion circuit 22 is TBC (time base compensator)
23, and the time-axis fluctuation component in the reproduction data is removed.

The output signal of the TBC 23 is the inner code decoder 2
4 and the error is corrected by the inner code. The output signal of the decoder 24 is supplied to the deshuffling circuit 25. The deshuffling circuit 25 is composed of a memory and is supplied with a write clock CKW and a read clock CKR. The frequency of the clock CKW is 1 / 3Fs, which is equal to the reproduction data and the clock rate, and the frequency of the clock CKR is 1 / 4Fs.
By the address control, the deshuffling circuit 25
The shuffling at the time of recording is restored to the original array. At the same time, a time axis expansion process is performed according to the clock frequency ratio. Further, by controlling the read phase of channels A to D, 8-channel parallel data is formed.

The output signal of the deshuffling circuit 25 is supplied to the outer code decoder 26, where the error correction processing by the outer code is performed. The output signal of the outer code decoder 26 is a head deinterleave error correction circuit 28.
Is supplied to. In this circuit 28, 8-channel data is decomposed into a luminance signal and two color difference signals, and an error that cannot be corrected by the inner code and the outer code is corrected. D / A converters 29, 30 and 31 are connected to the circuit 28, a digital luminance signal is converted into an analog luminance signal Y by the D / A converter 29, and a digital color difference is obtained by the D / A converters 30 and 31. The signals are converted into analog color difference signals PB and PR, respectively.

The same configuration as the reproduction circuit from the PLL 21 to the outer code decoder 26 for the channel A described above is provided for each of the other channels B to H, as indicated by the broken blocks 27B to 27H in FIG. At the output of the serial / parallel conversion circuit 22 and the serial / parallel conversion circuit in the circuit blocks 27B to 27H, the reproduction data indicated by S4 in FIG. 9 is generated. This reproduction data S4 corresponds to the reproduction phase of the magnetic head. Also, the outer code decoder 2
At the output of 6 and the output of the outer code decoder in the circuit blocks 27B to 27H, 8-channel parallel reproduction data of channels A to H as shown by S5 in FIG. 9 is generated.

[0015]

DISCLOSURE OF THE INVENTION The digital VT described above.
In R, the winding angle θ of the magnetic tape 15 is 270 °, which is larger than 180 °. In a digital VTR,
When the recording wavelength is constant and the number of drum rotations and the number of recording heads are specified, the diameter of the drum 13 can be reduced or the track length can be increased by increasing θ by more than 180 °. Can be lowered.
However, an interval in which the scanning of the magnetic heads overlaps occurs, and as a result, as shown in FIG. 5 or 8, it is necessary to provide in parallel a number of signal processing systems equal to the number of magnetic heads (channels). And the recording circuit,
There is a problem that the circuit scale of the reproducing circuit becomes large.

Therefore, an object of the present invention is to provide a recording / reproducing apparatus for a digital video signal in which the scale of the recording circuit and the reproducing circuit can be reduced even when the tape winding angle is large.

[0017]

SUMMARY OF THE INVENTION The present invention relates to a magnetic tape wound on a peripheral surface of a rotary drum by N magnetic heads attached to the rotary drum in an angular range in which scanning of the magnetic head overlaps. In a recording device for recording a digital video signal, a circuit (44) for distributing the input digital video signal to a number of channels smaller than the number N of heads, and an encoder (45, 48) including a digital recording processing circuit (53A to 53D) including the digital recording processing circuit (53A to 53D), the number being equal to the number of heads N, so as to match each recording phase of the magnetic head, Read out from there,
Memory circuit for outputting N recording signals (51A,
51E) is a recording device for a digital video signal.

Further, according to the present invention, a digital video signal is produced by a magnetic tape wound around the peripheral surface of the rotary drum by N magnetic heads mounted on the rotary drum in an angular range where the scanning of the magnetic head overlaps. In a reproducing device for reproducing, reproduction data of a magnetic head is respectively supplied, and the reproduction data is time-compressed so as to remove temporal fluctuation of the reproduction data and remove temporal overlap of the reproduction data. TBC for
(7) and the output data of the TBC (63) are combined to form reproduced data of a number smaller than the number of heads N (7)
2A to 72D) and the combining circuits (72A to 72D), respectively, and decoders (64, 6) for error correction codes.
6) including a digital reproduction signal processing circuit (73A to 73)
D) is a reproducing apparatus for a digital video signal.

[0019]

According to the present invention, the recording video signal is distributed to the number of channels smaller than the number of heads, the number of digital recording processing circuits equal to the number of channels is provided, and the number of channels equal to the number of heads is provided on the output side of the recording processing circuit. Form recording data. Therefore, the number of digital recording processing circuits can be reduced, and the circuit scale can be reduced as compared with the case where a recording processing circuit having the same number of channels as the number of heads is provided.

Further, according to the present invention, reproduction data from a plurality of magnetic heads are respectively supplied to the TBC, and the TBC removes the fluctuation of the time axis and also eliminates the temporal overlap of the reproduction data. .. Therefore, it is possible to combine the reproduction data of channels smaller than the number of magnetic heads, and it is possible to perform reproduction processing such as error correction after the combination. Therefore, the circuit scale can be reduced as compared with the case where a reproduction processing circuit having the same number of channels as the number of heads is provided.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. In this embodiment, as in FIG.
Eight magnetic heads are attached to a drum rotating at 0 Hz, four magnetic heads are provided in proximity to each other, and an angular interval of 180 ° is provided between them. The magnetic tape has θ (= 270 °) on the peripheral surface of the drum.
It is wrapped around the range.

FIG. 1 shows the configuration of the recording circuit of this embodiment. By the A / D converters 1, 2, and 3, the luminance signal Y,
The color difference signals PB and PR are converted into digital signals. The frequency of the sampling clock CK1 is Fs (for example, 37.5 MHz), and the frequency of CK2 is 1 / 2F.
s. The digital component signal is supplied to the head interleave circuit 44. The head interleave circuit 44 generates four time division multiplexed signals (clock rate is 1/2 Fs). One is A and E
Is a time-division multiplexed signal in which samples (or several samples) recorded as channels are alternately included. Others are time division multiplexed signals for B and F channels, C
And time-division multiplexed signals of G channels and time-division multiplexed signals of D and H channels. The time-division multiplexed channels correspond to pairs of magnetic heads facing each other at an angular interval of 180 °. S11 in FIG. 2 indicates four time division multiplexed signals generated from the head interleave circuit 44. Although the video data is continuously input, FIG. 2 shows the processing of only the video data supplied in the cycle T for simplicity.

The time division multiplexed signals of the A and E channels are passed through the outer code encoder 45 to the shuffling circuit 4.
6 is supplied. In order to correct an error that occurs during the recording and reproducing process, an error correction code using both an outer code and an inner code is used. Shuffling circuit 46
In order to disperse the burst error, the shuffling for rearranging the order of data within one field is performed. The shuffling circuit 46 is composed of a memory, and the write clock CKW and the read clock CKR are supplied to the shuffling circuit 46. These clocks C
The frequencies of KW and CKR are equal to 1/2 Fs. Further, in the shuffling circuit 46, the signals time-division-multiplexed on a sample-by-sample basis are transmitted to the channel A during the first half of the period T.
Is converted into a signal S12 in which there is data recorded as and the data recorded as channel E exists in the latter half thereof.

An ID adding circuit 47 adds an ID signal for control to the output signal of the shuffling circuit 46. The output signal of the ID adding circuit 47 is the inner code encoder 4
8 and the inner code is encoded. The output signal of the inner code encoder 48 is supplied to the sync adding circuit 49, and a sync signal is added to each sync block. The data of the structure of the sync block from the sync adding circuit 49 is supplied to the channel encoder 50, and the channel encoding process is performed.

The output signal of the channel encoder 50 is F
It is supplied to the IFO memories 51A and 51E. The FIFO memories 51A and 51E include parallel / serial conversion circuits 52A,
52E are respectively connected. The parallel / serial conversion circuit 52A generates recording data for the magnetic head of channel A, and the parallel / serial conversion circuit 52E generates recording data for the magnetic head of channel E. The frequency of the write clock W for the FIFO memories 52A and 52E is 1/2 Fs, and the frequency of the read clock R thereof is 1/3 Fs. Also, FI
The data of the channel A in the first half of the cycle T is written in the FO memory 51A, and the data of the channel E in the second half of the cycle T is written in the FIFO memory 51E. Therefore, with the FIFO memories 52A and 52E,
The time axis expansion is performed, and the data existing in the 1 / 2T section is expanded to the data existing in the 3 / 4T section.

As indicated by a broken line in FIG. 1, circuit blocks 53B, 53C, 53 similar to the circuit configuration 53A from the outer code encoder 45 to the channel encoder 50 described above.
D is also provided for the other three output signals from the head interleave circuit 44. Further, for these circuit blocks, circuit blocks 54B, 54F, 54C, 54G, 54D, 54H similar to the serial connection 54A, 54E of the FIFO memory and the parallel / serial conversion circuit are provided.
, Respectively, and respective recording data of channels B to H are generated from each circuit block. The recording data is supplied to eight magnetic heads via recording amplifiers, respectively, although not shown.

As shown in FIG. 2, circuit blocks 53A ...
From each shuffling circuit 53D, a signal S12 including data in which two channels are distributed in the first half and the second half of the cycle T of one rotation of the magnetic head is read out. Then, from the respective FIFO memories in the circuit blocks 54A, 54B, 54C and 54D, the recording data S of the channels A, B, C and D, which are expanded in the time axis and exist in the section of 3 / 4T.
13 is read. The section of this recording data S13 is
The magnetic heads of channels A to D coincide with the recording phase of scanning the magnetic tape, and the data of these channels are simultaneously recorded on the magnetic tape as four tracks.

Similarly, the data of the channels existing in the latter half of the cycle T are also included in the circuit blocks 54E, 54F, 54G,
Channels E, F, G, and H that have been expanded in the time axis by the respective FIFO memories in 54H and exist in the section of 3 / 4T
The recording data of is generated. This recorded data section is
The magnetic heads of channels E to H coincide with the recording phase of scanning the magnetic tape, and the data of these channels are simultaneously recorded on the magnetic tape as four tracks. As can be understood from FIG. 1, in the recording processing circuit, the paths (53A to 53D) from the outer code encoder 45 to the channel encoder 50 are 4 channels in parallel, and 8
The circuit scale can be made smaller than the conventional configuration in which the channel circuit system is provided in parallel. The connection point of the FIFO memory is preferably after the inner code encoder 48,
The configuration is not limited to that shown in FIG.

Next, with reference to FIGS. 3 and 4, the reproducing circuit of this embodiment will be described. Although not shown, reproduced data of channels A to H from each of the eight magnetic heads is supplied to a channel code decoder via a reproducing amplifier. The reproduced data of channel A from the channel code decoder is supplied to the PLL 61. The PLL 61 extracts the clock necessary for the processing of the reproduction circuit from the reproduction data. The output signal of the PLL 61 is transmitted through the serial / parallel conversion circuit 62 to the TBC (time axis compensator) 6
3 is supplied.

The TBC 63 is composed of a memory, in which data is written with a clock having a frequency of 1/3 Fs which is synchronized with reproduced data, and data is read with a stable clock of 1/2 Fs. As a result, the time-axis variation in the reproduced data is removed. At the same time, in the TBC 63, the time axis of the data is compressed to 2/3 according to the frequency ratio of the clock. Therefore, 3 in the cycle T of one rotation of the magnetic head
The reproduction data of channel A existing in the / 4T section is compressed to the length of the 1 / 2T section. Furthermore, TB
The timing of reading data from C63 is delayed by T time with respect to the input data. The output signal of the TBC 63 is supplied to the switching circuit 72A.

The above-mentioned PLL 61 and serial / parallel conversion circuit 6
The circuit configuration 67A including 2 and the TBC 63 is also provided for the reproduction data of the other channels B to H, respectively, as indicated by the broken lines 67B to 67H in FIG. The reproduction data of the channel E from the TBC in the circuit block 67E is supplied to the switching circuit 72A. The switching circuit 72B includes a circuit block 67.
Playback data for channels B and F from B and 67F are provided. The switching circuit 72C includes channels C and G from the circuit blocks 67C and 67G.
Playback data is supplied. The switching circuit 72D is supplied with reproduction data of channels D and H from the circuit blocks 67D and 67H. These switching circuits 72A to 72D are for alternately selecting the reproduction data of the two channels input thereto and generating the reproduction data of one channel.

The reproduced data in which the channels A and E generated in the switching circuit 72A are located in the first half and the second half of the cycle T, respectively, are supplied to the inner code decoder 64 and subjected to error correction by the inner code. The output signal of the decoder 64 is supplied to the deshuffling circuit 65. The deshuffling circuit 65 is composed of a memory, and has a write clock CKW and a read clock CKR.
And are supplied. The frequency of the clocks CKW and CKR is 1/2 Fs. By the address control, the deshuffling circuit 65 performs a process of returning the shuffling at the time of recording to the original array. Along with this, the data of the two channels A and E form time division multiplexed data in which they are alternately located in sample units.

The output signal of the deshuffling circuit 65 is supplied to the outer code decoder 66, where the error correction processing by the outer code is performed. The output signal A / E of the outer code decoder 66 is supplied to the head deinterleave error correction circuit 68. In this circuit 68, 4-channel time division multiplexed data is decomposed into a luminance signal and two color difference signals, and an error that cannot be corrected by the inner code and the outer code is corrected. D / A converters 69, 70 and 71 are connected to the circuit 68, the digital luminance signal is converted to an analog luminance signal Y by the D / A converter 69, and the digital color difference is converted by the D / A converters 70, 71. The signals are converted into analog color difference signals PB and PR, respectively.

In FIG. 3, the circuit block 7 indicated by a broken line.
3B, 73C and 73D are the inner code decoder 64,
It has the same circuit configuration as the circuit configuration 73A including the deshuffling circuit 65 and the outer code decoder 66, and is connected to the switching circuits 72B, 72C, and 72D, respectively. From the circuit block 73B, a time division multiplexed signal B / F in which the reproduced data of the channels B and F are alternately located in sample units is generated, and the circuit blocks 73C and 73D are generated.
Similarly, time-division multiplexed signals C / G and D / H are generated respectively. These time division multiplexed signals are supplied to the head interleave error correction circuit 68, and the luminance signal and the color difference signal are generated from this circuit 68 as described above.

In the reproduction circuit described above, reproduction data S14 in FIG. 4 is generated at the output of each serial / parallel conversion circuit of the circuit blocks 67A to 67H. In this case,
At the respective outputs of the switching circuits 72A to 72D, as shown in FIG. 4, reproduction data in which the reproduction data of the two channels are respectively located in the first half and the second half of the cycle of T is generated. Further, the circuit blocks 73A to 7
At the output of each 3D outer code decoder, a time division multiplex signal in which two channels are alternately positioned in sample units is generated. The magnetic head reproduces the data even after being shown in FIG. 4, but FIG. 4 shows only the processing of the video data reproduced by one rotation of the drum for the sake of simplicity.

In the reproducing circuit of this embodiment, it is sufficient to provide a processing circuit for four channels on the output side of the switching circuits 72A to 72D, which is a circuit scale as compared with the case where a processing circuit for eight channels is required. Can be greatly reduced.

[0037]

According to the present invention, the magnetic tape is wound over the peripheral surface of the rotary drum over 180 ° for the purpose of reducing the diameter of the drum, lowering the relative speed, etc., and as a result, the magnetic head is scanned. There is a temporal overlap in the periods. However, according to the present invention, by using the time axis conversion processing, it is sufficient to provide the recording circuit or the reproducing circuit in a number smaller than the number of magnetic heads, and the scale of these circuits can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing a circuit configuration for recording according to an embodiment of the present invention.

FIG. 2 is a timing chart used for explaining an operation during recording.

FIG. 3 is a block diagram showing a circuit configuration for reproduction according to an embodiment of the present invention.

FIG. 4 is a timing chart used to explain an operation during reproduction.

FIG. 5 is a block diagram showing a circuit configuration for recording of a conventional digital VTR.

FIG. 6 is a schematic diagram showing a head arrangement of a digital VTR.

FIG. 7 is a timing chart used for explaining an operation during recording of a conventional VTR.

FIG. 8 is a block diagram showing a circuit configuration for reproducing a conventional digital VTR.

FIG. 9 is a timing chart used to explain an operation during reproduction of a conventional VTR.

[Explanation of symbols]

 44 head interleave circuit 46 shuffling circuit 51A, 51E FIFO memory 63 TBC 72A to 72D switching circuit 65 deshuffling circuit

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H04N 5/92 C 8324-5C

Claims (2)

[Claims] 1. A digital video signal is recorded on a magnetic tape wound around a peripheral surface of the rotating drum in an angular range where scanning of the magnetic head overlaps by N magnetic heads attached to the rotating drum. In the recording apparatus, a means for distributing the input digital video signal to a number of channels smaller than the number of heads N, a digital recording processing means connected to each of the channels and including an error correction code encoder, and the digital recording The number of heads is equal to the number of heads N and is read from the magnetic heads so as to match the respective recording phases of the magnetic heads.
An apparatus for recording a digital video signal, comprising a memory means for outputting individual recording signals. 2. A digital video signal is reproduced from N magnetic heads mounted on a rotary drum from a magnetic tape wound around the peripheral surface of the rotary drum in an angular range in which scanning of the magnetic head overlaps. In the reproducing apparatus for reproducing the reproduction data, the reproduction data of the magnetic head is supplied, and the reproduction data is time-axis adjusted so as to remove the time-axis fluctuation of the reproduction data and remove the temporal overlap of the reproduction data. The memory means for compression is combined with the output data of the memory means, and the head number N
An apparatus for reproducing a digital video signal comprising a means for forming a smaller number of reproduction data and a digital reproduction signal processing means including a decoder for an error correction code, each of which is combined with the synthesizing means.