JPH0563755A - Signal transmitter - Google Patents

Abstract

PURPOSE:To change the length of transmission data and to make the data transmission efficient by identifying number of bytes of the transmission data based on bits of a transmission data frame to receive data by number of bytes. CONSTITUTION:A data reception circuit 15a and a clock signal reception circuit 15c compare inputted reception data and a clock signal with a reference voltage respectively and respective output signals are fed to a header detection circuit via filters 15b, 15d. When a header frame is detected, the detection circuit outputs an L level detection signal and the signal is ORed with communication data outputted from a shift register 11 and a header detection signal is sent to a control section from a transmission data output circuit 15e. The control section receives the signal to detect a data length bit and the data length is written in a byte number counter. Thus, the length of the sent data is changed and the data transmission is made efficient.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is suitable for use in an air conditioner for an automobile such as a separate type auto air conditioner mounted on an automobile in which a control unit and an operation display unit are separated. The present invention relates to a signal transmission device that transmits a signal to and from a display unit.

[0002]

2. Description of the Related Art A conventional separation type automatic air conditioner mounted on an automobile and its signal transmission system are shown in FIGS.
It will be explained based on. FIG. 19 shows a separate type automatic air conditioner
It is a whole block diagram of 00. In this figure, a microcomputer is built in the auto amplifier section 101, and a sensor circuit 102 including an outside air temperature sensor, an inside air sensor, a water temperature sensor, a solar radiation sensor, a duct sensor, etc. is connected to an input port. There is. A control panel unit 103 is connected to the input / output port of the auto amplifier unit 101. An actuator circuit 104 is connected to the output port of the auto amplifier unit 101. A driven part 105 such as an air mix door is further connected to the drive part of the actuator circuit 104.

FIG. 20 is a diagram showing a connection relationship between the auto amplifier section 101 and the control panel section 103. In this figure, the display section 103a is connected to the auto amplifier section 101 by four indicator control signal lines 107 and the like. The display unit 103a displays a temperature or the like.
The air conditioner switch unit 103b has “AUTO” and “H”
It is a switch group including nine panel switches such as "I" and "DOWN", and is automatically operated by three air conditioner switch output signal lines 108a, 108b, 108c and three air conditioner switch input signal lines 109a, 109b, 109c. It is connected to the amplifier unit 101. The illumination lamp 103c is a light source that illuminates the air conditioner switch unit 103b.

FIG. 21 is a block diagram showing details of the display section 103a, and FIG. 22 is a timing chart showing display data SI transferred from the auto amplifier section 101 to the display section 103a. In FIG. 21, a 21-bit shift register 110 includes 21 stages of flip-flops S0 and S.
1, S2 ... S20. This 21
The display data SI is serially transferred from the auto amplifier unit 101 to the bit shift register 110 at the rising timing of the shift clock SCK shown in FIG.
The display buffer register 111 is composed of 21 stages of flip-flops P0, P1, ... P20.
The display data SI stored in the 21-bit shift register 110 is transferred in parallel to the display buffer register 111 at the timing when the latch signal LH of the “H” level shown in FIG. 22 is supplied. As a result, the display data in the display buffer register 111 is updated. The AND gate 112 includes registers S0, S1, S2 ... S20 of the display buffer register 111.
It is a gate for supplying the display data stored in (1) to a fluorescent display tube driver (not shown). The dimming signal BI is input to one input terminal of the AND gate 112. When the pulse width of the dimming signal BI shown in FIG. 22 is changed, the brightness of the fluorescent display tube is adjusted accordingly.

FIG. 23 is a waveform diagram showing a transmission / reception signal between the auto amplifier unit 101 and the air conditioner switch unit 103b. (A) shows the air conditioner switch input signal lines 109a, 10
The signals are constantly output from the auto amplifier unit 101 to the air conditioner switch unit 103b via 9b and 109c, and the signals A, B, and C have a phase difference of 1/3 cycle with each other. (B) is the air conditioner switch output signal lines 108a, 10
A signal D is a signal output from the air conditioner switch unit 103b to the auto amplifier unit 101 via 8b and 108c, and a signal D is supplied to the auto amplifier unit 10 via the air conditioner switch output signal line 108a when the "AUTO" switch is turned on.
This is a signal output to 1. The signal E is the air conditioner switch output signal line 108b when the "HI" switch is turned on.
Is a signal output to the auto amplifier unit 101 via. The signal F is a signal output to the auto amplifier unit 101 via the air conditioner switch output signal line 108c when the "DOWN" switch is turned on. As described above, the auto-amplifier section 101 and the control panel section 103 of the separate type auto air conditioner are connected by a large number of signal lines, and functions by transmitting and receiving signals via these signal lines.

[0006]

As described above, the signal transmission between the auto amplifier section and the control panel section of the conventional separation type auto air conditioner is performed by four indicator control signal lines 107 between the auto amplifier section and the display section. In addition, a total of 10 signal lines of 6 input / output signal lines of the air conditioner switch between the auto amplifier part and the air conditioner switch part are required, which causes a problem of increasing the number of signal lines. Moreover, since the system is not designed to check the error of the transmitted signal, there is a problem that communication reliability is low.

The present invention has been made by paying attention to the above-mentioned problems, and it is possible to reduce the number of signal lines and to establish a system in which an error check of a transmitted signal is performed, thereby improving communication reliability. By using a one-chip microcomputer that improves the performance and has a built-in clock synchronous serial interface,
An object of the present invention is to obtain a signal transmission device that can be handled only by software without using dedicated hardware, and that does not impose a burden on software and can change the length of data.

[0008]

A signal transmission apparatus according to the invention of claim 1 is a signal transmission apparatus for serially transmitting an NRZ signal sequence from a transmission circuit to a reception circuit in synchronism with a clock signal. A header frame in which a signal sequence includes a predetermined number of "H" level bits and a predetermined number of "L" level bits, a plurality of data frames including a predetermined number of data bits and one parity bit, and the data. A parity frame composed of a parity bit string that performs parity check of the same-order bits of the frame, and a bit provided in a part of the data frame that indicates the number of bytes of the transmission data, and the transmission data of the transmission data based on the bit. Data processing means for identifying the number of bytes, receiving the data by the number of bytes, and then performing reception end processing It is equipped with and.

According to a second aspect of the present invention, in the signal transmission device, the transmission circuit and the reception circuit are composed of a one-chip microcomputer in which a clock synchronous serial interface is built in, and the header frame is a 15-bit number. It is a header frame composed of the above'H 'level bits and 1'L' level bits, and the above data frame is a data frame composed of 7 bits of data bits and 1 bit of odd parity vertical parity bits. , The parity frame is a horizontal parity frame composed of a parity bit string for performing parity check of the same-order bits of the data frame, and a bit provided at the head of the data frame indicating the number of bytes of transmission data, and the bit. Based on the bytes of the transmitted data A data processing means for identifying the number, performing horizontal parity check after receiving data by the number of bytes, and further performing data latch.

[0010]

In the signal transmission device according to the present invention, the length of data to be transmitted can be changed, and a one-chip microcomputer having a built-in clock synchronous serial interface is used. Serial without hardware
The load on the software during data transfer is reduced, and since the NRZ signal train from the transmission circuit is serially transmitted to the reception circuit in synchronism with the clock signal, the number of signal lines can be reduced and further transmission is possible. Since the signal is subjected to horizontal parity check and vertical parity check, the reliability of communication is improved. Further, since the vertical parity check is an odd parity, it is possible to easily find a state in which the transmission data becomes all "1" and all "0" due to a hardware failure.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A case in which an embodiment of the signal transmission device of the present invention is used in a vehicle air conditioner such as a separate type auto air conditioner mounted on a vehicle will be described below with reference to FIGS. .. FIG. 1 shows a signal transmission device 1 of this embodiment.
3 is a block diagram showing the configuration of FIG. The communication system in this signal transmission device 1 is a half-duplex, clock-synchronous polling system, and the transmission code format used is the NRZ format. The control unit 2 is composed of a one-chip microcomputer having a built-in clock synchronous serial interface. The input port of the control unit 2 is connected to an outside air temperature sensor circuit, an inside air sensor circuit, a water temperature sensor circuit, a solar radiation sensor circuit, a duct sensor circuit, etc., which are not shown. An actuator circuit (not shown) is connected to the output port of the control unit 2.
The driven part of the actuator circuit is further connected to a driven part such as an air mix door. On the other hand, the control unit 2 has a serial data clock output terminal SCK.
A serial data transmission terminal TX and a serial data reception terminal PX are provided. The terminal machine 3 is composed of a one-chip microcomputer having a clock-synchronous serial interface built therein, and is installed in a control panel section provided in a driver's seat. This terminal 3 has a serial data clock receiving terminal SCK
Is connected to the serial data clock output terminal SCK of the control unit 2 via the communication bus BL1. Further, the serial data receiving terminal RX is connected to the serial data transmitting terminal TX of the control unit 2 via the communication bus BL2. Further, the serial data transmission terminal TX is connected to the serial data reception terminal RX of the control unit 2 via the communication bus BL3. The terminal 3 also has VDD
Address setting terminals A0 and A1 that are pulled up are provided. Address setting switches S0 and S1 are connected between the address setting terminals A0 and A1 which are pulled up to VDD and the ground, respectively. Terminal 3
Further, a display unit and a switch group on the control panel unit are connected to the. The terminal 4 is composed of a one-chip microcomputer having a built-in clock synchronous serial interface, and is installed in a control panel section provided in the rear seat.
Serial data clock receiving terminal SC of this terminal 4
K is connected to the serial data clock output terminal SCK of the control unit 2 via the communication bus BL1. Further, the serial data receiving terminal RX is connected to the serial data transmitting terminal TX of the control unit 2 via the communication bus BL2. Further, the serial data transmission terminal TX is connected to the serial data reception terminal RX of the control unit 2 via the communication bus BL3. The terminal 4 also has VDD
Address setting terminals A0 and A1 that are pulled up are provided. Address setting switches S00 and S11 are connected between the address setting terminals A0 and A1 which are pulled up to VDD and the ground, respectively. The terminal unit 4 is also connected to a display unit on the control panel unit and a switch group such as panel switches and rotary switches.

FIG. 2 is a functional block diagram of the terminal. The switch group MSW on the control panel unit is connected to the switch matrix control terminals MA0 to MA4 and the switch matrix input terminals SW0 to SW3, and the rotary switch group RSW is connected to the rotary switch input terminals RS0 to RS5. Here, the switch group MSW is an air conditioner switch for selecting and operating "AUTO", "HI", "DOWN", and the like. The rotary switch group RSW is a switch for temperature selection. The SW matrix circuit 5 inputs the SW matrix signal from the SW matrix input terminals SW0 to SW3, performs double collation on the SW matrix signal to eliminate chattering in the switch unit, and then decodes the SW matrix signal to obtain the switch matrix circuit 5 The corresponding SW data latch (not shown) provided in the above is inverted.

An input circuit for the switch group MSW is shown in FIG. In this figure, the input circuit 5a of the SW matrix input terminal SW0 is composed of a Schmitt trigger inverter, and the digital filter DF
1 to the SW matrix circuit 5.
The input circuit 5b of the SW matrix input terminal SW1 is composed of a Schmitt trigger inverter and similarly connected to the SW matrix circuit 5 via the digital filter DF1. SW matrix input terminal S
The same applies to the input circuits 5c and 5d for W2 and SW3, which are composed of Schmitt trigger inverters and are connected to the switch matrix circuit 5 via the digital filter DF1.
It is connected to the.

Returning to FIG. 2, the timing generation circuit 6 outputs the switch matrix timing signals SWT, VFT (fluorescent display tube) drive signal VDS, the output dimming signal OCS, and the SW matrix control terminals MA0 to MA4.
The SW matrix control signal shown in FIG. 4 is output to the switch group MSW via. The header detection circuit 7 is a circuit that detects a header of received data and outputs a header detection signal HDS. The error check circuit 8 is a circuit that performs address check of received data, vertical parity check, and addition of vertical parity at the time of transmission. The horizontal parity check circuit 9 performs horizontal parity check of received data and addition of horizontal parity of transmitted data. The transmission data selector circuit 10 selects data at the time of transmission for each frame and shifts the communication shift register circuit 1 described below.
It is a circuit to send to 1. The double matching circuit 10a performs double matching on the rotary switch input signal input from the rotary switch group RSW and removes chattering at the rotary switch.

An input circuit for the rotary switch group RSW is shown in FIG. In this figure, rotary switch input terminals RS0, RS1, RS2, RS3, RS4
RS5 input circuits 10b, 10c, 10d, 10e, 1
0f and 10g are composed of Schmitt trigger inverters, and the outputs of these input circuits are added to the double collation circuit 10a. Returning to FIG. 2, the shift register circuit for communication 1
Reference numeral 1 is a 7-bit shift register that performs parallel / serial conversion during transmission and serial / parallel conversion during reception. Here, a circuit configuration around the communication shift register circuit 11 in the terminals 3 and 4 is shown in FIG. In the figure, 15a is a serial data receiving circuit including a comparator, 15b is a digital filter, 15c is a communication clock signal receiving circuit, 15d is a digital filter,
Reference numeral 5e is a transmission data output circuit for transmitting data to the control unit 2, and an AND gate for inputting transmission data from the shift register 11 and a transmission enable signal (H level at the start of transmission) from the timing generation circuit 2 (12). An AND gate for inputting the inverted signal of the transmission enable signal and the header detection signal from the header detection circuit 7 (L level at header detection, H level at error occurrence or reception end)
And an OR gate for inputting two AND gate outputs, and a MOSFET. Serial data receiving circuit 1
5a and the communication clock signal reception circuit 15c compare the reception data input from the serial data reception terminal RX and the communication clock signal SCK input from the serial data clock input terminal SCK with a reference voltage, respectively, to perform waveform shaping. To do. The waveform-shaped received data and the communication clock signal SCK are digital filters 15b, 1
Noise removal processing is performed by 5d and the noise is supplied to the header detection circuit 7. When a header frame is detected,
The header detection circuit 7 outputs the header frame detection signal HDS of'L 'level. "L" indicating that the logical sum operation processing is performed between the header frame detection signal HDS and the transmission data output from the communication shift register 11 and the header frame is detected from the transmission data output circuit 15e to the communication bus BL3. A level header detection signal is output and sent to the control unit 2. Further, when a reception error such as an address error or a parity error is detected, the serial data transmission terminal TX immediately becomes high impedance, a reception error signal is sent to the control unit 2, and when the reception is normally completed, FIG. Frame 28
~ After the frame 32 is transmitted, the impedance becomes high impedance and the normal reception completion signal is sent to the control unit 2. When there are a plurality of terminals, the header detection signal is sent from all the terminals to the control unit 2 immediately after the header frame is output from the control unit 2. Since the terminal causes an address error, the serial data transmission terminal T of the terminal other than the designated address
All Xs immediately become high impedance, and a header detection signal indicating that the header frame has been detected is output only from the serial data transmission terminal TX of the designated terminal and is sent to the control unit 2. As shown in FIG. 7, when the header frame of the data sent from the control circuit is detected, the header detection signal sent from the serial data transmission terminal TX becomes'L 'level at the 2nd bit, and the address of the received data is shown. When an error or parity error is detected, it immediately becomes'H 'level. Therefore, the control unit 2 monitors the change of the header detection signal output from the communication bus BL3 from the'H 'level to the'L' level and the change of the'L 'level to the'H' level. It is possible to grasp the reception status of. The transmission data such as the header detection signal output from the serial data transmission terminal TX described above is output to the communication bus BL3 in synchronization with the fall of the communication clock signal SCK as shown in FIG. To be done.

Returning to FIG. 2, the timing generation circuit 12 is
Each timing signal related to the communication function is generated. The reception data latch circuit 13 is a circuit for temporarily latching reception data until the end of the horizontal parity check. VFT
The driver circuit 14 is a drive circuit for a fluorescent display tube (not shown) provided on the control panel section. The clock generation circuit 16 is a circuit that generates a reference clock signal. The display data latch circuit 17 is a circuit that latches display data based on an input latch signal.

FIG. 8 is a diagram showing a communication format of transmission / reception data between the control unit 2 and the terminals 3 and 4. In this figure, 18 is a header frame composed of 15-bit or more continuous "H" level and 1-bit "L" level pulse train, and 19 to 27 are frames composed of 8 bits. 19a is an address bit consisting of 2 bits, 19b
Is a data length bit consisting of 5 bits, and the number of bytes of data transmitted from the control unit to the terminal is written in a binary code. This writing is controlled. 19
c is a 1-bit vertical parity bit. 20a is a data bit consisting of 7 bits of the frame 20, and 20b is a vertical parity bit. 21a is 7 of the frame 21
A data bit composed of a bit and 21b is a vertical parity bit. Reference numeral 22a is a 7-bit data bit of the frame 22, and 22b is a vertical parity bit. Two
3a is a data bit consisting of 7 bits of the frame 23,
23b is a vertical parity bit. 24 a is a data bit consisting of 7 bits of the frame 24, and 24 b is a vertical parity bit. 25a is 7 bits of the frame 25
Data bit, and 25b is a vertical parity bit. 26a is a data bit consisting of 7 bits of the frame 26, and 26b is a vertical parity bit. 27a
Is a horizontal parity frame composed of 7 bits, and 27 b is a vertical parity bit of the frame 27. 18-
Each frame up to 27 is a frame of received data transmitted from the control unit 2 and received by the terminal 3 or the terminal 4. 28 to 32 each represent one frame, which is transmission data sent from the terminal 3 or 4 to the control unit 2. 28a is an address bit composed of 2 bits, and is a bit for identifying from which terminal device the data is transmitted. 28b is a data length bit consisting of 5 bits, and the number of bytes of data transmitted from the terminal to the control unit 2 is written in a binary code. This writing is done by the terminal. 29a, 30a, 31a
Is a data bit indicating push-down information or rotation information of the switch group MSW and the rotary switch group RSW, 28
Reference numerals c, 29b, 30b, 31b and 32b are vertical parity bits.

FIG. 9 is a diagram showing allocation of received data from frame 19 to frame 27 in the received data latch circuit 13. In this embodiment, the number of bytes of data is written in a binary code from L0 to L4. In this case, since the data transmitted is 7 bytes from D1 to D7, "11100" is written.

FIG. 10 is a diagram showing allocation of transmission data composed of the frames 28 to 32 transmitted to the control unit 2. The number of bytes of data is written in a binary code from L0 to L4. In this case, the data to be transmitted is 3 bytes from D1 to D3.
1000 "is written.

FIG. 11 is a timing chart showing the timing of inputting serial data in the terminals 3 and 4. In this figure, sampling of the data supplied to the serial data receiving terminal RX is performed in synchronization with the rising of the communication clock signal SCK supplied to the serial data clock input terminal SCK, and is taken into the terminal.

FIG. 12 is a timing chart showing the timing of the transmission data transmitted from the terminals 3 and 4.
In this figure, the data transmitted from the serial data transmission terminal TX is the serial data clock input terminal SC.
This is performed in synchronization with the fall of the communication clock signal SCK supplied to K.

FIG. 13 is a diagram showing an error detection method of received data in the terminals 3 and 4. In this figure, 5
1 is the vertical parity bit of frame 19 shown in FIG.
Similarly, 2 is the vertical parity bit of frame 20, 53 is the vertical parity bit of frame 21, and 53 is the frame 2
1 vertical parity bit, 54 vertical parity bit of frame 22, 55 vertical parity bit of frame 23, 56 vertical parity bit of frame 24, 57 vertical parity bit of frame 25, 58 vertical parity bit of frame 25
6 is a vertical parity bit, and 59 is a vertical parity bit of the frame 27. Reference numeral 60 is a horizontal parity frame of the frame 27 shown in FIG. In this error detection method of received data, both the vertical parity and the horizontal parity are odd parity checks, and the address error, the vertical parity error, and the horizontal parity error are detected. In this case, 51
Each vertical parity bit VPm of ˜59 (VP0 to VP8) is obtained based on the following arithmetic expression.

[0023]

[Equation 1]

On the other hand, the horizontal parity bits HPm of 60 (HP0 to HP6) are calculated based on the following arithmetic expressions.

[0025]

[Equation 2]

FIG. 14 is a diagram showing an error detection method for the transmitted data in the control unit 2. In this figure, 61 is a vertical parity bit of the frame 28 shown in FIG. 8, 62 is a vertical parity bit of the frame 29, 63 is a vertical parity bit of the frame 30, and 6 is a vertical parity bit of the frame 30.
Reference numeral 4 is a vertical parity bit of the frame 31, and 65 is a vertical parity bit of the frame 32. 66 is a horizontal parity frame of the frame 32 shown in FIG. In this error detection method, both vertical parity and horizontal parity are odd parity checks, and address errors, vertical parity errors, and horizontal parity errors are detected. in this case,
The vertical parity bits VPm of each of 61 to 65 (VP0 to VP4) are obtained based on the following arithmetic expression.

[0027]

[Equation 3]

On the other hand, each horizontal parity bit HPm of 66 (HP0 to HP6) is obtained based on the following arithmetic expression.

[0029]

[Equation 4]

FIG. 15 is a timing chart at the time of detecting a pressed switch by performing a double collation based on the SW matrix signal in the switch matrix circuit 5.

FIG. 16 is a timing chart when performing double matching on the rotary switch input signal.

Next, with reference to FIGS. 17 and 18, the operation of the signal transmission device 1 in this embodiment will be described.
FIG. 17 is a flowchart for explaining the operation of the controller 2, and FIG. 18 is a flowchart for explaining the operation of the terminal. When the power is turned on in the signal transmission device 1, the control unit 2 and the terminals 3 and 4 are operated as shown in FIGS.
The operation is started according to the flowchart shown in FIG.
First, in step ST1, the control unit 2 initializes the transfer clock and the transfer clock rate internally. In the subsequent step ST2, the transmission data shown in FIG. 8 is created. That is, the data bits 20a, 21a, 22a, 23a, 24a, 25a of FIG.
26a, address bits 19a of the destination address,
Data length bit 19b setting, vertical parity bit 19
c, 20b, 21b, 22b, 23b, 24b, 25
b, 26b, 27b, horizontal parity frame 27a shown in frame 27, and so on. Step ST3
Then, the data created in step ST2 is transmitted to the terminal. In the subsequent step ST41, the header detection signal, the data length bit, the data frame, the normal reception completion signal, etc. sent from the terminal are ready to be received.
On the other hand, when the terminal detects the header frame sent from the control unit 2 in step ST11 of FIG. 18, the terminal proceeds to step ST12 and outputs a header detection signal indicating that the header frame is detected from the terminal to the control unit 2. To do. The control unit 2 detects the head detection signal and knows that the terminal has started reception. Step S
At T13, the address designated by the address bit 19a is the address setting switch S0, S1 shown in FIG.
Alternatively, in S00 and S11, it is determined in the terminal whether or not the address matches the address previously set for itself. If the addresses match, the process proceeds to step ST141,
The data length shown in 19b of FIG. 8 is written in the byte number counter BC, and the data is received. The received data is stored in the received data latch circuit 13 (see FIG. 2) with the allocation shown in FIG. In the process of receiving this data, steps ST142 and ST14
By "3", "-1" is subtracted from the byte number counter value for each communication clock signal. On the other hand, step ST13
When it is determined that the addresses do not match in step ST15, as an address error, the serial data transmission terminal TX is set to high impedance to turn off the header detection signal, and the process returns to step ST11 to wait for header frame detection. .. Step ST16
Then, the horizontal parity check and the vertical parity check are performed on the received data by using the data frame sent next as the horizontal parity frame. This parity check

[Equation 1],

It is performed on the basis of the calculation shown in Equation 2. If no error is detected in the horizontal parity check and vertical parity check, the process proceeds to step ST17 and the display data is updated. In step ST18, the terminal device transmits data (frames 28 to 32 in FIG. 8) to the control unit 2. On the other hand, the control unit 2 receives the data sent from the terminal, detects the data length bit, and writes the data length in the byte number counter BC. In this case, since the number of bytes of the data sent is 3, "11000" is written. Continue, Step ST42, Step ST
At 43, "-1" is subtracted from the byte number counter value for each communication clock. The data latch circuit of the control unit 2 latches the received data as shown in FIG. In step ST5, the received data is subjected to horizontal parity check, vertical parity check, and the like.
This parity check

[Equation 3],

It is performed on the basis of the calculation shown in Equation 4. If no error is detected in the horizontal parity check and vertical parity check, the process proceeds to step ST6, validates the received data, and returns to step ST2. On the other hand, if an error is detected in step ST5, the process proceeds to step ST7, the received data is invalidated and discarded, and the process returns to step ST2. On the other hand, in the terminal, the process proceeds to step ST19 and the normal reception completion signal is sent to the control unit 2. The control unit 2 knows that the reception is normally completed by the normal reception completion signal sent from the terminal. On the other hand, if a parity error is detected in step ST16 of the terminal, the process proceeds to step ST20. In step ST20, the terminal sends a reception error signal to the control unit 2 and returns to step ST11. Based on the reception error signal sent from the terminal, the control unit 2 knows that a reception error has occurred, and accordingly retransmits the data to the same terminal. When the header frame of the data sent from the control unit 2 is detected during the transmission of the data to the control unit 2, the terminals 3 and 4 immediately stop the transmission and start the reception.

[0033]

As described above, according to the inventions of claims 1 and 2, since the length of data to be transmitted can be changed, the number of bytes is appropriate for a doctor having a small amount of information to be transmitted. Signal can be transmitted, the time required for communication can be shortened, and data can be transmitted efficiently. In addition, since a one-chip microcomputer with a built-in clock-synchronous serial interface is used, it is economical without the need to use dedicated hardware, and the NRZ signal string is synchronized with the clock signal to serially receive a circuit. Since the number of signal lines is small, the horizontal parity check and the vertical parity check are performed on the transmitted signal, so that the communication reliability is improved. Further, since the vertical parity check is an odd parity, it is possible to easily find a state in which the transmission data becomes all "1" and all "0" due to a hardware failure. Furthermore, since a one-chip microcomputer with a built-in clock-synchronous serial interface is used, the load on the software for serial data transfer is reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a signal transmission device according to an embodiment of the present invention.

FIG. 2 is a functional block diagram of a terminal in the signal transmission device according to the embodiment of the present invention.

FIG. 3 is an electric circuit diagram showing an input circuit for a switch group MSW.

FIG. 4 is a waveform diagram showing a SW matrix control signal.

FIG. 5 is an electric circuit diagram showing a configuration of an input circuit for a rotary switch group RSW.

FIG. 6 is an electric circuit diagram showing a circuit configuration around a communication shift register circuit.

FIG. 7 is a timing chart for explaining the output of the transmission data output circuit.

FIG. 8 is a diagram showing a communication format of transmission / reception data between a control unit and a terminal.

FIG. 9 is a diagram showing allocation of reception data latched in a reception data latch circuit.

FIG. 10 is a diagram showing allocation of transmission data transmitted to a control unit.

FIG. 11 is a timing chart showing a timing at which received data is sampled.

FIG. 12 is a timing chart showing the timing of data transmission.

FIG. 13 is a diagram illustrating an error detection method of received data in a terminal.

FIG. 14 is a diagram showing an error detection method for transmitted data in a control unit.

FIG. 15 is a timing chart at the time of double-checking and detecting a pressed switch in the switch matrix circuit.

FIG. 16 is a timing chart when performing a double collation on a rotary switch input signal.

FIG. 17 is a flowchart for explaining the operation of the control unit.

FIG. 18 is a flowchart illustrating an operation of the terminal.

FIG. 19 is an overall block diagram of a conventional separation type automatic air conditioner.

FIG. 20 is a diagram showing a connection relationship between an auto amplifier section and a control panel section.

FIG. 21 is a block diagram showing details of a display unit.

FIG. 22 is a timing chart showing display data transferred from the auto amplifier section to the display section.

FIG. 23 is a waveform diagram showing a transmission / reception signal between the auto amplifier unit and the air conditioner switch unit.

[Explanation of symbols]

1 Signal Transmission Device 2 Control Unit 3 Terminal Device 4 Terminal Device 5 SW Matrix Circuit 6 Timing Generation Circuit 7 Header Detection Circuit 8 Error Check Circuit 9 Horizontal Parity Check Circuit 10 Transmission Data Selector Circuit 11 Communication Shift Register Circuit 12 Timing Generation Circuit 13 Reception data latch circuit 14 VFT driver circuit 15a Serial data reception circuit 15b Digital filter 15c Communication clock signal reception circuit 15d Digital filter 15e Transmission data output circuit 16 Clock generation circuit 17 Display data latch circuit 18 Header frame 19-27 Terminal receives Received data frame 19a Address bit 19b Data length bit 20a, 22a, 23a, 24a, 25a, 26a Data bit 19c, 20b, 21b, 2 2b, 23b, 24b, 2
5b, 26b, 27b Vertical parity bit 27a Horizontal parity bit 28 to 32 Frame of transmission data transmitted from terminal 28a Address bit 28b Data length bit 29a, 30a, 31a Data bit 28c, 29b, 30b, 31b, 32b Vertical parity bit 32a Horizontal parity bit BL1 communication bus BL2 communication bus S0 address setting switch S1 address setting switch S11 address setting switch S00 address setting switch

Claims (2)

[Claims] 1. A signal transmission device for serially transmitting an NRZ signal sequence from a transmission circuit to a reception circuit in synchronization with a clock signal, wherein the NRZ signal sequence has a predetermined number of'H 'level bits and a predetermined number of bits. A header frame made up of'L 'level bits, a plurality of data frames made up of a predetermined number of data bits and 1 parity bit, and a parity frame made up of a parity bit string for performing a parity check of the same-order bits of the data frame. And a bit provided in a part of the data frame that indicates the number of bytes of the transmission data, and the number of bytes of the transmission data is identified based on the bit, and reception is completed after receiving the data by the number of bytes. A signal transmission device comprising: a data processing unit that performs processing. 2. The transmission circuit and the reception circuit are composed of a one-chip microcomputer in which a clock synchronous serial interface is built in, and the header frame is made up of 15 or more'H 'level bits and 1 bit. It is a header frame consisting of'L 'level bits, the data frame is a data frame consisting of 7 bits of data bits and 1 parity vertical parity bit of odd parity, and the parity frame is the same as the data frame. It is a horizontal parity frame consisting of a parity bit string that performs a parity check of the order bits, and further identifies the bit provided at the beginning of the data frame indicating the number of bytes of transmission data and the number of bytes of transmission data based on the bit. , Receive data for the number of bytes Horizontal parity check is performed, further the signal transmission apparatus according to claim 1, characterized by comprising a data processing means for performing data latch after.