JPH0563577A - Delta sigma modulator - Google Patents

Abstract

PURPOSE:To obtain a high dynamic range even at a low oversampling by increasing a degree order of delta sigma modulation. CONSTITUTION:Five integration devices 1-5 are connected in cascade and each output is subjected to weight sum by multipliers 6-9 and adders 10-13 and the result is inputted to a local quantizer 14. Each of coefficients are selected as 1, 0.5, 0.125, 0.03125, 0.00390625 for weight sum and a local quantizer 14 outputs 61 binary output. The output of the local quantizer 14 is extracted as sigma delta modulator output and delayed by one clock at a delay circuit 15 and the result is given to a subtractor 16, which takes a difference with an input and the result is inputted to a 1st stage integration device.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a .DELTA..SIGMA. Modulator, and more particularly to high-order .DELTA..SIGMA.

[0002]

2. Description of the Related Art With the progress of digital signal processing technology in recent years, the ΔΣ modulator is used for A / D and D / A converters, and the importance thereof is increasing. The ΔΣ modulation is to obtain a high dynamic range with a small number of bits by using oversampling to drive low-frequency quantization noise to a high frequency.

A conventional ΔΣ modulator is shown in FIG. 3 and will be described (for example, Radio Technology Magazine February 1989 issue). The integrators 1 to 4 are connected in cascade, and the integrators 2 to 4 are connected.
Are weighted by multipliers 100 to 102, respectively, and then added by adders 10 to 12. Here, the coefficients A, B, C in the multipliers 100 to 102 are
Is A = 0.5, B = 0.125, C = 0.01562
It is 5. The weighted addition results of the integrators 1 to 4 obtained from the adder 10 are requantized by the local quantizer 14. The local quantizer 14 outputs 1 when the input value is 0 or more, and outputs -1 when the input value is less than 0. Local quantizer 14
Delay the output of 1 clock by the delay circuit 15,
A subtracter 16 is used to subtract from the input and the result is given to the integrator 1.

When constructed in this manner and operated with 64 times oversampling, a maximum dynamic range of 94.3 dB can be obtained.

[0005]

However, although the fourth-order ΔΣ modulation can be performed with the above configuration,
When it is desired to obtain higher performance, for example, when the order of ΔΣ modulation is set to the fifth order, it is difficult to obtain a higher performance even if the order can be increased. there were.

In view of the above problems, it is an object of the present invention to provide a ΔΣ modulator having more excellent performance by using five integrators and appropriately weighting the output of each integrator. It is what

[0007]

In order to achieve this object, a ΔΣ modulator of the present invention comprises a first integrator for integrating an input signal and a second integrator for integrating an output of the first integrator. An integrator, a third integrator that integrates the output of the second integrator, a fourth integrator that integrates the output of the third integrator, and an output of the fourth integrator A fifth integrator, a first multiplier that multiplies the output of the second integrator by a coefficient A, and a second multiplier that multiplies the output of the third integrator by a coefficient B, A third multiplier that multiplies the output of the fourth integrator by a coefficient C, a fourth multiplier that multiplies the output of the fifth integrator by a coefficient D, and an output of the first integrator And an output of the first to fourth multipliers, an adder, a local quantizer for quantizing the output of the adder, and the station. A delay circuit for delaying the output of the partial quantizer by one clock; and a subtractor for taking the difference between the input signal and the output of the delay circuit. The output of the subtractor is input to the first integrator. , The value of the coefficient A is 0.5, the value of the coefficient B is 0.125, and the value of the coefficient C is 0.03.
125, the value of the coefficient D is 0.00390625,
The output of the local quantizer is taken out as a ΔΣ modulation output.

[0008]

As described above, since five integrators are used and the output of each integrator is multiplied by an appropriate coefficient and added, and the addition result is quantized, a stable fifth-order ΔΣ is obtained.
Modulation can be performed, and a larger dynamic range can be obtained in the low frequency range.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a ΔΣ modulator according to the present invention. In this figure, components having the same functions as those in FIG. 3 are designated by the same reference numerals, and detailed description thereof will be omitted. In the present embodiment, an integrator 5, a multiplier 9, and an adder 13 are newly added to perform fifth-order ΔΣ modulation. Coefficients A multiplied by the multipliers 6 to 9,
B, C, and D are A = 0.5 and B = 0.125 (1 /
8), C = 0.03125 (1/32), D = 0.00
390625 (1/256), which is actually
The multiplier 6 shifts the input right by 1 bit, the multiplier 7 shifts the input right by 3 bits, the multiplier 8 shifts the input right by 5 bits, and the multiplier 9 shifts the right right by 8 bits and outputs the result. It is carried out.

The sums of the outputs of the integrator 1 and the multipliers 6 to 9 are obtained by the adders 10 to 13 and given to the local quantizer 14. The local quantizer 14 outputs +1 if the input value ≧ 0, and outputs −1 if the input value <0. This value is given to the subtractor 16 via the delay circuit 15, and the difference with the input is taken and given to the first-stage integrator 1.

Since the transfer function H (z) of the integrator is as shown in (Equation 1), by configuring in this way, as shown in (Equation 2) between the input X and the output Y. Relationship is established.

[0013]

[Equation 1]

[0014]

[Equation 2]

As shown in (Equation 2), by constructing as shown in FIG. 1 and setting the values of the coefficients A, B, C, and D of the multipliers 6 to 9 as described above, the fifth-order ΔΣ Modulation can be performed. When this ΔΣ modulator is used with 64 times oversampling, a maximum dynamic range of 109 dB can be obtained. Figure 2 shows the output spectrum when a 0.5 fs, 0 dB sine wave is input.

In the above embodiments, the integrators 3 to 3 are connected.
I did not mention the overflow of No. 5, but in order to prevent overflow, I added a limiter to integrators 3-5,
It goes without saying that overflow may be prevented. At this time, the value of the limiter is the multiplier 7-
The output of 9 may be set to 1 or less. That is, the limiter range is ± 8 for the integrator 3 and ± 32 for the integrator 4.
In the integrator 5, it may be ± 256.

[0017]

As described above, according to the present invention, stable fifth-order ΔΣ modulation can be performed, a larger dynamic range can be obtained in the low frequency range, and when used with 64 times oversampling, a dynamic range of 109 dB is obtained. It has an excellent effect of being obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a ΔΣ modulator according to an embodiment of the present invention.

FIG. 2 is an output spectrum diagram when a 0.5 fs, 0 dB sine wave is input to the ΔΣ modulator shown in FIG. 1.

FIG. 3 is a block diagram showing a configuration of a conventional ΔΣ modulator.

[Explanation of symbols]

 1-5 integrator 6-9 multiplier 10-13 adder 14 local quantizer 15 delay circuit 16 subtractor

Claims (3)

[Claims] 1. A first integrator for integrating an input signal, a second integrator for integrating an output of the first integrator, and a third integrator for integrating an output of the second integrator. , A fourth integrator that integrates the output of the third integrator, a fifth integrator that integrates the output of the fourth integrator, and a constant A to the output of the second integrator. A second multiplier that multiplies the output of the third integrator by a constant B, and a third multiplier that multiplies the output of the fourth integrator by a constant C. And a fourth multiplier that multiplies the output of the fifth integrator by a constant D, and an addition unit that sums the output of the first integrator and the outputs of the first to fourth multipliers. A local quantizer for quantizing the output of the adding means; a delay circuit for delaying the output of the local quantizer by one clock; A subtractor that takes the difference between the input signal and the output of the delay circuit, the output of the subtractor is input to the first integrator, the value of the constant A is 0.5, and the value of the constant B is The value of 0.125, the value of the constant C is 0.03125, the value of the constant D is 0.0
0390625, and the output of the local quantizer is taken out as a ΔΣ modulation output. 2. The ΔΣ modulator according to claim 1, wherein the output of the local quantizer has two gradations. 3. The ΔΣ modulator according to claim 1, wherein the third to fifth integrators have a limiter function so that the value of each integrator does not exceed a certain value.