JP2002314425A - Delta-sigma modulating apparatus and method, and digital signal processing apparatus and method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a delta-sigma modulating apparatus and method that suppresses distortion depending on the input signal and generates a 1-bit digital signal obtained by applying delta-sigma modulating only to a desired signal component. SOLUTION: An integrator 2 applies integration processing to a signal B on the basis of an input signal, that is the signal B obtained by adding a feedback input D being a negatively fed back 1-bit signal from a 1-bit quantizer 3, to the input signal A. The 1-bit quantizer 3 varies a threshold level Th at random with respect to n [time] within a range of ±Δq to quantize an output C of the integrator and outputs a 1-bit signal E.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an analog input signal or a multi-bit digital input signal.
Ii) A delta-sigma modulation device and method for performing a modulation process to generate a 1-bit digital signal, and a digital signal processing device and method.

[0002]

2. Description of the Related Art A high-speed 1-bit audio signal modulated by .DELTA..SIGMA. Is a data format used in conventional digital audio (for example, a sampling frequency of 44.times.).
As compared with 1 kHz and a data word length of 16 bits, a very high sampling frequency and a short data word length (for example, the sampling frequency is 64 times the frequency of 44.1 kHz and the data word length is 1 bit), and the transmission is wide. It features a possible frequency band. Further, even with a 1-bit signal by ΔΣ modulation, a high dynamic range can be secured in an audio band that is low with respect to an oversampling frequency of 64 times. By utilizing this feature, it can be applied to high-quality sound recorders and data transmission.

[0003] The Δ 自 体 modulator itself is not a particularly new technology, and its circuit configuration is suitable for integration into an IC, and the accuracy of AD conversion can be obtained relatively easily. Circuit.

[0004] The ΔΣ modulated signal can be returned to an analog audio signal by passing through a simple analog low-pass filter.

A general configuration of this ΔΣ modulator comprises a combination of an arbitrary number of integrators, one quantizer, and a feedback system of the output of the quantizer. Since a quantizer is included, when an equivalent circuit is evaluated by a transfer function or the like, it is general to perform analysis by approximately replacing a quantizer.

FIG. 20 shows a first conventional example of a ΔΣ modulator. This first conventional example is composed of a combination of one integrator 7, one 1-bit quantizer 8, and a feedback system of its quantized output. More specifically, an adder 6 to which an input signal G is supplied to a positive input terminal and a feedback output to be described later is supplied to a negative input terminal, an integrator 7 for performing an integration process on the added output of the adder 6, A 1-bit quantizer 8 for quantizing the integrated output of the unit 7 into a 1-bit digital signal every sample period. The quantized output H of the 1-bit quantizer 8 is fed back as a negative sign to the adder 6,
It is added to (and consequently subtracted from) the input signal G. The 1-bit quantizer 8 outputs a 1-bit digital signal H to the outside as a quantized output. The integrator 7 is an adder 7a
And a delay unit 7b.

Here, the 1-bit quantizer 8 quantizes the input signal X (n) with reference to a threshold value (threshold) Th which is invariant with respect to time and is always 0 as shown in FIG. Processing is performed to generate a 1-bit output signal Y (n). That is, the 1-bit quantizer 8 determines a binary level between 0 and less than 0 with respect to the input signal X (n) at 0, and performs a quantization process.

[0008]

However, FIG.
The ΔΣ modulator shown in FIG. 2 has one integrator 7 and one FIG.
1 is a combination of a non-linear 1-bit quantizer 8 and a feedback system of the output of the quantizer. Therefore, when an attempt is made to generate a high-speed 1-bit audio signal of a desired frequency signal, Distortion depending on the input signal occurs inside the ΔΣ modulator.

FIG. 22 shows a Δ１ modulator having a fifth-order local feedback loop including the above-mentioned conventional ΔΣ modulator and having a frequency of 1;
4 shows a spectrum distribution (FFT analysis result) of a 1-bit audio signal (64 fs) generated when a KHz sine wave signal is input. Frequency 2,3,4,6KH
It can be seen that harmonic noise occurs near z. This harmonic noise is distortion depending on the input signal.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has a delta-sigma modulation apparatus and method for suppressing a distortion depending on an input signal and generating a 1-bit digital signal in which only a desired signal component is ΔΣ-modulated. The purpose is to provide.

Further, the present invention has been made in view of the above-mentioned circumstances, and suppresses distortion dependent on an input signal peculiar to ΔΣ modulation without deteriorating sound quality by giving frequency characteristics to random noise. It is an object of the present invention to provide a digital signal processing device and a digital signal processing method.

[0012]

According to the present invention, there is provided a delta-sigma modulation apparatus for performing a delta-sigma modulation process on an input signal and outputting a 1-bit digital signal. , An operation means for differentiating the input signal and a 1-bit digital signal as a feedback signal, an integration means for integrating the difference signal in the operation means, and a quantization processing for the integration output of the integration means for 1 A quantizing unit that outputs a bit digital signal; and a feedback loop that returns a quantized output of the quantizing unit to the arithmetic unit as the feedback signal, and a threshold level referred to in a quantization process in the quantizing unit. Is variably controlled relative to the time axis.

In order to solve the above-mentioned problems, the present invention provides a delta-sigma modulation method for performing a delta-sigma modulation process on an input signal and outputting a 1-bit digital signal. An operation step of differentiating a 1-bit digital signal that is a feedback signal;
An integration step of integrating the difference signal in the calculation step; a quantization step of performing a quantization process on the integration output of the integration step to output a 1-bit digital signal; And a feedback step of returning to the operation step as a signal, wherein a threshold level referred to in the quantization processing in the quantization step is variably controlled with respect to a time axis.

According to another aspect of the present invention, there is provided a digital signal processing apparatus, comprising: a calculating means for calculating a difference between a feedback signal and an input signal; an integrating means for integrating an output signal of the calculating means; Noise generating means for generating the noise, an adding means for adding random noise output from the noise generating means to an integrated output of the integrating means, a quantizing means for quantizing the added output from the adding means by 1 bit, And a feedback loop means for feeding back the 1-bit digital signal output from the quantization means as the feedback signal to the arithmetic means.

In order to solve the above-mentioned problems, a digital signal processing method according to the present invention comprises: a calculating step of calculating a difference between a feedback signal and an input signal; an integrating step of integrating an output signal of the calculating step; A noise generating step of generating, an adding step of adding random noise output from the noise generating step to the integrated output of the integrating step, and a quantization step of quantizing the added output from the adding step by 1 bit. A feedback step of returning a 1-bit digital signal output from the quantization step to the arithmetic step as the feedback signal.

According to another aspect of the present invention, there is provided a digital signal processing apparatus, comprising: a calculating means for calculating a difference between a feedback signal and an input signal; an integrating means for integrating a difference signal from the calculating means; Noise generating means for generating noise, filter means for extracting a high-frequency component of a noise signal output from the noise generating means, gain adjusting means for performing gain adjustment on an output from the filter means, and the gain An adding unit that adds a noise signal composed of a high-frequency component gain-adjusted by the adjusting unit and an output signal from the integrating unit; a quantizing unit that quantizes the added output from the adding unit by 1 bit; Feedback loop means for feeding back the 1-bit digital signal output from the quantization means as the feedback signal.

In order to solve the above-mentioned problems, a digital signal processing method according to the present invention comprises: a calculating step of calculating a difference between a feedback signal and an input signal; an integrating step of integrating a difference signal in the calculating step; A noise generating step of generating noise; a filtering step of extracting a high-frequency component of a noise signal output from the noise generating step; a gain adjusting step of performing gain adjustment on an output from the filtering step; An adding step of adding a noise signal composed of a high-frequency component whose gain has been adjusted in the adjusting step and an output signal from the integrating step; a quantization step of quantizing the added output from the adding step by 1 bit; And a feedback step of feeding back the 1-bit digital signal output from the quantization step as the feedback signal.

According to another aspect of the present invention, there is provided a digital signal processing apparatus, comprising: an arithmetic unit for calculating a difference between a feedback signal and an input signal; an integrating unit for integrating a difference signal from the arithmetic unit; Noise generating means for generating a 1-bit digital signal, phase modulation means for phase-modulating a random 1-bit digital signal output from the noise generating means, and gain adjustment for the output from the phase modulation means. Gain adjusting means, adding means for adding a noise signal composed of a high-frequency component gain-adjusted by the gain adjusting means and an output signal from the integrating means, and a quantum for quantizing the output from the adding means by 1 bit. And a feedback loop means for feeding back the 1-bit digital signal output from the quantization means as the feedback signal.

In order to solve the above-mentioned problems, a digital signal processing method according to the present invention comprises: a calculating step of calculating a difference between a feedback signal and an input signal; an integrating step of integrating a difference signal in the calculating step; A noise generating step of generating a proper 1-bit digital signal, a phase modulating step of phase-modulating a random 1-bit digital signal output from the noise generating step, and performing gain adjustment on an output from the phase modulating step. A gain adjustment step, an addition step of adding a noise signal composed of a high-frequency component gain-adjusted in the gain adjustment step and an output signal from the integration step, and a quantum for quantizing the output from the addition step by 1 bit. And a feedback step of feeding back the 1-bit digital signal output from the quantization step as the feedback signal.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Some embodiments of the present invention will be described below with reference to the drawings. First, according to a first embodiment of the present invention, an analog audio signal or a multi-bit digital audio signal is used as an input signal.
This is a Δ 装置 modulator that performs a delta-sigma (ΔΣ) modulation process on this input signal to generate a high-speed 1-bit audio signal.

As shown in FIG. 1, the ΔΣ modulator has
An adder 1 for adding an input signal A and a negative feedback signal D (1-bit digital signal); an integrator 2 for integrating a difference signal B from the adder 1; 1-bit quantizer 3 that performs a digitizing process and outputs a 1-bit digital signal E, and a feedback that feeds back the adder 1 as the feedback signal D by making the sign of the quantized output E of the 1-bit quantizer 3 negative. And a loop 4.

Here, the integrator 2 includes an adder 2a for adding the integrated output C as a feedback input F to the difference signal B, and a delay unit 2b for delaying the added output of the adder 2a.

The 1-bit quantizer 3 is a quantizer that makes the threshold level Th referred to in the quantization process variable with respect to the time axis. That is, as shown in FIG. 2, the 1-bit quantizer 3 randomly changes the threshold Th referred to when quantizing the input signal X (n) within a range of ± Δq with respect to the time axis. .

Next, a description will be given of the ΔΣ modulation processing operation performed on the input signal A by the ΔΣ modulation apparatus shown in FIG.
First, the integrator 2 generates a difference signal B based on the input signal A,
That is, a difference signal B obtained by adding a feedback input D obtained by negatively feeding back the 1-bit signal from the 1-bit quantizer 3 to the input signal A.
Is subjected to integration processing. At this time, the integrator 2 delays the addition output from the internal adder 2a by the delay unit 2b, and then feeds it back to the adder 2a.

Next, the 1-bit quantizer 3 randomly varies the threshold level Th with respect to n [time] within a range of ± Δq, quantizes the integrated output C, and outputs a 1-bit signal E. I do. The 1-bit signal E from the 1-bit quantizer 3
Is output to the outside and the feedback loop 4
(Feedback input D), and is returned to the adder 1. The adder 1 adds the feedback input D to the input signal A, outputs a difference signal B, and supplies the difference signal B to the integrator 2.

As described above, in the ΔΣ modulator shown in FIG. 1, the threshold level Th referred to in the quantization processing in the 1-bit quantizer 3 is a variable threshold level which is randomly varied with respect to the time axis. The variable threshold level is randomly selected within a range of ± Δq with respect to the time axis.

Next, a method of calculating the optimum value of the variable threshold level in the 1-bit quantizer 3 will be described. The behavior of the one-bit quantizer 3 using the variable threshold level is equivalent to adding a component corresponding to the variable threshold level to a signal input to a conventional one-bit quantizer. Therefore, the effect of suppressing the distortion depends on the relative variable amount with respect to the signal input to the conventional 1-bit quantizer.

Here, the signal input to the conventional 1-bit quantizer is an output signal of a final-stage integrator, which will be described later, and therefore, a relative signal obtained based on the amplitude of the final-stage integrator. The variable amount affects the effect of suppressing distortion.

The ΔΣ modulator generally has a plurality of integrators according to the order. FIG. 3 is a schematic configuration diagram of an example of an N-order ΔΣ modulator. It includes an N number of integrators from the first-stage integrator 2 ₁ to the final-stage integrator 2 _e. Then, the output signal of the final stage integrator 2 _e is supplied to the 1-bit quantizer 3.

The actual optimal variable threshold level calculation is performed based on the amplitude obtained by the integrator within 2 _e of the last stage. Specifically, as shown in the following equation (1), a value SαD _end obtained by multiplying the maximum value D _end of the amplitude of the signal generated in the integrator 2 _e of the final stage by a constant Sα is optimally changed. This is a method of setting the threshold level Δq.

Δq = SαD _end (1) By using this calculation method, a result obtained by multiplying a uniquely determined constant in any configuration of ΔΣ modulation can be set as an optimal variable threshold level.

As described above, for any ΔΣ modulator, the optimum amount is obtained by the above-described calculation method based on the amplitude of the signal in the final stage integrator used therein, and the appropriate random amount is obtained. If the threshold value is varied by noise, it is possible to suppress distortion depending on an input signal peculiar to ΔΣ modulation with stable operation and without deteriorating S / N.

FIG. 4 is a flowchart for designing a ΔΣ modulator using the above-described method for calculating the variable threshold level. First, in step S1, a desired ΔΣ modulator is configured. Next, in step S2, the amplitude of the signal in the final integrator is measured. Then, in step S3, the variable threshold level Δq is calculated using the above equation (1). Thereafter, the variable threshold level Δq is set in step S4, and it is determined in step S5 whether or not to continue the use change processing of the ΔΣ modulator.
S) The process from step S1 is repeated, and if the use change process ends (NO), a series of processes ends.

According to the design flow shown in FIG. 4, in any ΔΣ modulation design, the ΔΣ modulation can be flexibly reconstructed by using the variable threshold level quantization of the present invention.
The above effects can be expected. In other words, even when the configuration of the ΔΣ modulator is changed according to the purpose, the above-described effect can be expected as long as the amplitude of the signal in the final stage integrator can be known.

By using the method of calculating the variable threshold level Δq, the effective range of the threshold level to be randomly varied can be determined to be, for example, within 75%. 75
If the threshold level is higher than%, distortion depending on the input signal A cannot be sufficiently suppressed.

Next, FIG. 5 shows a configuration of a ΔΣ modulator 80 including a plurality of integrators, including the ΔΣ modulator shown in FIG. In FIG. 5, an adder 1, an integrator 2, and a 1-bit quantizer 3 constituting the ΔΣ modulator of FIG.
An adder 75, an integrator 76, and a 1-bit quantizer 78 are provided. Further, a bit length converter 79 is provided on a negative feedback path from the 1-bit quantizer 78.

The ΔΣ modulator 80 shown in FIG. 5 is a fifth-order ΔΣ modulator provided with five integrators 63, 66, 69, 73 and 76. Further, the fifth-order Δ 装置 modulator includes a local feedback loop unit 81 that attenuates the output of the fifth integrator 76, requantizes the output, and feeds it back to the input of the previous integrator 73. The local feedback loop unit 81 includes a local feedback attenuator 77 and a noise shaper 82.

The .DELTA..SIGMA. Modulator 80 has an adder 62, which adds a multi-bit digital signal to each integrator before the five integrators 63, 66, 69, 73 and 76.
65, 68, 72 and 75, and four attenuators 64, 67, 71 and 4 connected after the first to fourth integrators 63, 66, 69 and 73 of the five integrators. 74
And a 1-bit quantizer 78 similar to the 1-bit quantizer 3 connected after the fifth integrator 76, and the bit length of the 1-bit digital signal from the 1-bit quantizer 78 It is converted to multi-bit, and five integrators 63, 66,
Adders 62, 6 so as to be input to 69, 73 and 76
Bit length converter 79 for supplying 5, 68, 72 and 75
And

The first integrator 63 integrates the input signal supplied via the input terminal 61 and the adder 62. Therefore, the output from the adder similar to the adder 2a shown in FIG. 1 is delayed by the same delay unit as the delay unit 2b and returned to the adder. Second to fifth integrators 66, 6
9, 73 and 76 are similar.

The integrated output from the fifth integrator 76 is supplied to the 1-bit quantizer 78 and the local feedback attenuator 77 of the local feedback loop unit 81.

The 1-bit quantizer 78 sets the threshold level Th to be referred to in the quantization processing to Δq shown in the above equation (1). That is, Δq is calculated based on the amplitude D _end of the signal inside the fifth integrator 76 at the final stage.

Therefore, in the quantization processing performed by the 1-bit quantizer 78 on the integration output of the fifth integrator 76, the reference threshold level is appropriately and randomly varied with respect to the time axis. No distortion depending on the input signal is generated. This 1-bit output signal is output to output terminal 8
3 and supplied to the bit length converter 79.

The bit length converter 79 converts the one-bit signal from the one-bit quantizer 78 into a multi-bit digital signal, and assigns a minus sign to the adders 62, 65, 68, 72 and 75. Will return. Therefore, each adder 62, 6
5, 68, 72, and 75 are provided from the input terminal 61 and the integrators 63, 66, 69, 73 in the preceding stage to the attenuators 64, 67,
The output signal of the bit length converter 78 is subtracted from the signal supplied via 71 and 74.

The attenuators 64, 67, 71 and 74 use the coefficients K1, K2, K3 and K4 to generate integrators 63, 6
6, 69 and 73 are attenuated, and the adders 65,
68, 72 and 75.

The local feedback attenuator 7 of the local feedback loop unit 81
7 attenuates the integrated output from the fifth integrator 76 using the coefficient Kf and supplies it to the noise shaper 82.

Although not shown, the noise shaper 82 includes an adder, a delay unit, and a multi-bit quantizer.
The attenuated output from local feedback attenuator 77 is requantized without causing data word length truncation. In particular,
Shift the requantization error out of the audible band.

Therefore, this ΔΣ modulator 80
Since the threshold level referred to in the quantization process in the bit quantizer 78 is appropriately and randomly varied with respect to the time axis, no distortion depending on the input signal is generated.
Further, since a local feedback loop is provided, a 1-bit audio signal with high sound quality can be output.

FIG. 6 shows a 1-bit audio signal (64 fs) generated when a 1 KHz sine wave signal is input to the ΔΣ modulator 80 having the fifth-order local feedback loop shown in FIG. 3 shows the spectrum distribution (FFT analysis result) of the sample. Frequency 2,3,4,6K observed in the spectrum distribution of the ΔΣ modulator having the fifth-order local feedback loop including the conventional ΔΣ modulator shown in FIG.
Harmonic noise around Hz is suppressed. That is, it can be seen that the distortion depending on the input signal can be suppressed.

As described above, in the ΔΣ modulation apparatus according to the first embodiment, when any ΔΣ modulation design is designed using quantization of a variable threshold level,
If the amplitude of the signal in the final stage integrator can be known, the optimum variable threshold level can be calculated. Therefore, even in the case where the ΔΣ modulation is flexibly reconfigured according to the purpose at an optimum variable threshold level by, for example, simulation, it is possible to suppress the occurrence of distortion depending on the input signal specific to the ΔΣ modulation. The optimum variable threshold level means that the operation of the ΔΣ modulation itself is stable and that the S / N does not deteriorate as a characteristic, in addition to suppressing the generation of distortion depending on the input signal specific to the ΔΣ modulation. Means

[0050] In the first embodiment, the calculation of the optimal variable threshold level has been performed based on the amplitude obtained by the integrator within 2 _e of the final stage may be carried out in other ways. For example, the limiter value L _{e nd} for limiting the amplitude obtained by the integrator within 2 _e of the final stage may be used. The limiter value L _end here is for clipping an overlevel of 0 dB or more as an input signal to the ΔΣ modulator. Thus, the upper limit of the input signal can be determined. Oscillation,
Used to prevent system instability.

By the way, the distortion caused by the input signal caused by the use of the non-linear 1-bit quantizer 8 shown in FIG. 21 by the ΔΣ modulator shown in FIG. Several measures have been taken as described in [Delta] [Sigma] modulators in which some measures have been taken will be described as first to third comparative examples.

First, in the first comparative example, a random signal r such as a dither signal is supplied to the adder 6 from the random signal generator 14 together with the input signal A as in the ΔΣ modulator shown in FIG. Was.

However, when the random signal r is input together with the input signal A, the 1-bit audio signal E ′ generated through the integrator 7 and the 1-bit quantizer 8 has a desired signal component. In addition, a component (random signal r) added to suppress distortion is also included.

The spectrum distribution of a 1-bit audio signal (64 fs) generated when a sine wave signal having a frequency of 1 KHz is input to a ΔΣ modulator having a fifth-order local feedback loop including the ΔΣ modulator shown in FIG. (FFT analysis result) is shown in FIG. Since random noise is added, the level of the noise floor up to 20 KHz is generally flat and increased by about 20 dB as compared with the spectrum distribution according to the present embodiment shown in FIG. The noise is hidden by the random noise added to the input signal by the adder 6.

Next, in a second comparative example, as in the ΔΣ modulator shown in FIG.
8 to supply an appropriate DC component d to the adder 6.

However, when the DC component d is input together with the input signal A, the 1-bit audio signal E オ ー デ ィ オ generated through the integrator 7 and the 1-bit quantizer 8 includes:
In addition to the desired signal component, a component (DC component) added for suppressing distortion is also included.

The spectrum distribution of a 1-bit audio signal (64 fs) generated when a sine wave signal having a frequency of 1 KHz is input to a ΔΣ modulator having a fifth-order local feedback loop including the ΔΣ modulator shown in FIG. (FFT analysis result) is shown in FIG. Since random noise is added, the level of the noise floor from 1 KHz to 10 KHz is flat as compared with the spectrum distribution according to the present embodiment shown in FIG. The DC component added to the input signal by the adder 6 hides noise from 1 KHz to 10 KHz.

Next, in the third comparative example, ΔΣ shown in FIG.
As in the modulation device, a distortion component due to the input signal A is obtained, and the distortion component is supplied from the distortion canceller 22 to the adder 6.

However, in the third comparative example, since the distortion is determined in advance from the result of passing the input signal A through the ΔΣ modulator, it is difficult to predict the distortion in advance.
In addition, the use of the distortion canceller 22 may theoretically cause distortion due to its own influence.

In contrast to the third comparative example, the ΔΣ modulator according to the present embodiment shown in FIG. 1 can suppress distortion in advance and add components to suppress distortion together with the input signal. Is required, only the desired signal component is Δ
(4) A modulated high-speed 1-bit signal can be generated.

Next, a second embodiment of the present invention will be described. In the second embodiment, a digital signal processing is used in which an analog audio signal or a digital audio signal of a plurality of bits is used as an input signal, and the input signal is subjected to integration processing and quantization processing to generate a high-speed 1-bit audio signal. This is a ΔΣ modulation device which is a type of device.

The ΔΣ modulator of the second embodiment is
As shown in FIG. 12, an adder 1, an integrator 2, a random signal generator 11, an adder 12, and a 1-bit quantizer 8 are provided. Further, the Δ 装置 modulator includes a feedback loop 4 for making the sign of the quantized output E of the 1-bit quantizer 8 negative and feeding it back to the adder 1 as a feedback signal D.

The ΔΣ modulator according to the second embodiment has
It is characterized in that an adder 12 is inserted between the integrator 2 and a conventional general 1-bit quantizer 8, and a random signal from a random signal generator 11 is added to the adder 12.

Next, the ΔΣ modulation operation performed on the input signal A by the ΔΣ modulator shown in FIG. 12 will be described. First, the integrator 2 adds a difference signal B based on the input signal A, that is, a difference signal B obtained by adding a feedback input D obtained by negatively feeding back the 1-bit signal from the 1-bit quantizer 3 to the input signal A. The integration processing is performed, and the integration output is supplied to the adder 12.

The adder 12 includes a random signal generator 11
Also supplies a random signal r 'to the integrated output C'. The added output I of the adder 12, that is, the integrated output I to which the random signal r 'is added is supplied to the 1-bit quantizer 8 as in the prior art.

The 1-bit quantizer 8 performs a quantization process on the integrated output I to which the random signal r 'has been added, and outputs a 1-bit digital signal E.

In the ΔΣ modulator shown in FIG. 12, a random signal r ′ is added to the integrated output C ′ immediately before quantizing the integrated output C ′. This is equivalent to randomly changing the threshold value of the 1-bit quantizer 8.

A Δ１ modulator having a fifth-order local feedback loop including the ΔΣ modulator of the second embodiment has a frequency of 1
The spectrum distribution (FFT analysis result) of the 1-bit audio signal (64 fs) generated when a KHz sine wave signal is input is the same as the characteristic shown in FIG.

The first comparative example, ΔΔ shown in FIG.
ΣThe modulation device also uses the random signal generator 14,
The configuration is different from the ΔΣ modulation device shown in FIG. 12 in which a random signal is added to an input signal to the ΔΣ modulation device and a random signal is added to an integrated output inside the ΔΣ modulation device. As is apparent from a comparison between the spectrum distributions of FIGS. 6 and 8, the spectrum distribution of the ΔΣ modulator of FIG. 12 (FIG. 8) shows that the noise floor level up to 20 KHz is flat as a whole. And 20
There is no characteristic of increasing by about dB, and it is understood that a high-speed 1-bit signal in which only a desired signal component is ΔΣ-modulated can be generated.

Therefore, even in the Δ 装置 modulator of the second embodiment, distortion can be suppressed in advance, and a component added to suppress distortion together with the input signal is not required. A high-speed 1-bit signal modulated by ΔΣ can be generated. Further, since it is only necessary to add a random signal generator immediately before quantization based on the existing ΔΣ modulator, it is possible to easily configure the apparatus.

Next, the ΔΣ modulator of the second embodiment
A modified example will be described with reference to FIGS. This
The ΔΣ modulation device of the modification of
Be prepared. FIG. 13 is an outline of an example of an N-order ΔΣ modulator.
It is a block diagram. First stage integrator 2 ₁To the final stage integrator 2_eMa
And N integrators. And the final stage integrator 2
The gain of the output of e is adjusted by the gain adjuster 31.
The random noise signal from the random signal generator 11
Are added by the adder 12. FIG.
The random noise signal whose gain is adjusted by the
No.R_nTime domain characteristics (a) and frequency domain characteristics (b)
Is shown.

As described above, the modified example of the ΔΣ modulator shown in FIG. 13 includes the gain adjuster 31 and adjusts the gain of the random noise signal from the random signal generator 11 before the final stage integrator 2 _e. Is added to the integral output of.

[0073] gain adjuster 31, as shown in the following equation (2), the random noise signal R absolute value of _n is adder 1
As a variable threshold Δq less based on the amplitude of the 2 immediately before the final stage integrator 2 _e internal signal, adjusts the gain to be multiplied to the random noise signal R _n.

| R _n | ≦ Δq (2) The random noise signal R _n whose gain has been adjusted in this manner
Is added to the integration output of the final stage integrator 2 _e by the adder 12, and the added output signal is quantized by the 1-bit quantizer 8.

Therefore, the .DELTA..SIGMA. Modulator shown in FIG. 13 can vary the quantization at the optimum variable threshold level, so that it operates stably and without deteriorating the S / N, and is unique to the .DELTA..SIGMA. Distortion depending on the input signal can be suppressed.

Further, since the method of calculating the appropriate amount is based on the amplitude of the signal in the final stage integrator, the signal in the final stage integrator used inside any ΔΣ modulator is used. If the optimum amount is obtained by the above-described calculation method based on the fluctuation width of the signal and the threshold value is varied with the appropriate amount of random noise, an input specific to ΔΣ modulation can be performed stably without deteriorating the S / N ratio. Signal-dependent distortion can be suppressed.

Next, a third embodiment of the present invention will be described. In the third embodiment, an analog audio signal or a multi-bit digital audio signal is used as an input signal, and the input signal is subjected to integration processing and quantization processing to generate a high-speed 1-bit audio signal. This is a ΔΣ modulation device which is a type of device.

The ΔΣ modulator of the third embodiment also includes a plurality of integrators according to the order. FIG. 15 is a schematic configuration diagram of an example of an N-order ΔΣ modulator. First stage integrator 2
It includes an N number of integrators from ₁ to the last stage integrator 2 _e. The output of the final-stage integrator 2 _e is provided with the random noise signal Dth_h whose gain has been adjusted by the gain adjuster 34.
f has been added by the adder 12.

FIG. 16 shows a time domain characteristic (a) and a frequency domain characteristic (b) of the random noise signal Dth_hf from which the high frequency component has been extracted by the HPF filter 33.

The gain adjuster 34 includes an HPF filter 33
Random noise signal Dth_hf from which high-frequency components are extracted
Adjust the gain of. The HPF filter 33 extracts a high-frequency component of the random noise Dth generated by the multi-level dither generator 32.

That is, in the ΔΣ modulator shown in FIG. 15, the gain of the random noise signal Dth_hf, which is a high frequency component of the random noise Dth generated by the multilevel dither generator 32, is adjusted by the gain adjuster 34. I have. Then, the gain-adjusted random noise signal Dth
_hf is added to the integration output of the final-stage integrator 2 _e by the adder 12.

As described above, the ΔΣ modulator shown in FIG. 15 is provided with the gain adjuster 34, adjusts the gain of the random noise signal Dth_hf from which the high frequency component is extracted by the HPF filter 33, and then integrates the final stage. It is added to the integrated output of the vessel 2 _e.

As shown in the following equation (3), the gain adjuster 34 adjusts the absolute value of the random noise signal Dth_hf based on the amplitude of the signal inside the last-stage integrator 2 _e immediately before the adder 12. The gain by which the random noise signal Dth_hf is multiplied is adjusted so as to be equal to or less than Δq.

| Dth_hf | ≦ Δq ...
(3) The random noise signal Dth whose gain has been adjusted in this way
_hf is added to the integration output of the final stage integrator 2 _e by the adder 12, and the added output signal is quantized by the 1-bit quantizer 8. 1 obtained by the 1-bit quantizer 8
The bit output signal Y (n) is supplied to the integrator 2 via the feedback loop 4 and is led out.

Focusing on the frequency characteristics of the optimum amount of random noise added immediately before quantization, the effect of suppressing distortion dependent on an input signal peculiar to ΔΣ modulation is how fast and random the time is. Since it depends on whether the quantization threshold level is varied, the effect of suppressing distortion can be expected by using only the variable quantization threshold level of the high frequency component.

That is, when an appropriate amount of random noise is added immediately before a normal 1-bit quantizer, distortion can be suppressed only by random noise of a high-frequency component. This is because random noise of a low-frequency component (corresponding to an audible band component in a high-speed 1-bit audio stream) that has an adverse effect on sound quality is not required.

Therefore, the ΔΣ modulator shown in FIG.
By using a variable quantization threshold level having frequency characteristics, it is possible to suppress distortion depending on an input signal peculiar to ΔΣ modulation without deteriorating sound quality at all.

Next, a fourth embodiment of the present invention will be described. The fourth embodiment also employs an analog audio signal or a digital audio signal of a plurality of bits as an input signal, and performs an integration process and a quantization process on the input signal to generate a high-speed 1-bit audio signal. This is a ΔΣ modulation device which is a type of device.

The ΔΣ modulator of the fourth embodiment also includes a plurality of integrators according to the order. FIG. 17 is a schematic configuration diagram of an example of an N-order ΔΣ modulator. First stage integrator 2
It includes an N number of integrators from ₁ to the last stage integrator 2 _e. The output of the final-stage integrator 2 _e is provided with the random noise signal Dth_p, the gain of which has been adjusted by the gain adjuster 38.
m is added by the adder 12.

[0090] gain adjuster 38, a random noise signal Dth_pm the high-frequency component in the phase modulator 37 _i is extracted
Adjust the gain of _(i) .

[0091] The phase modulator 37 _i is 1 bit dither generator 36 sampling frequency 44.1 the sampling frequency is for example being used in a compact disk which is produced by
The cascaded phase modulators 37 _{1 to} 37 _i for performing multiplex phase modulation on a 1-bit dither signal of 32 Fs which is 32 times KHz (= Fs) are configured. Phase modulator 37
₁ performs a phase modulation process on the 1-bit dither signal from the 1-bit dither generator 36. Multiple phase modulation refers to performing phase modulation several times to obtain a desired frequency characteristic.

[0092] The detailed configuration of a specific example of the phase modulator 37 ₁ shown in FIG. 18. Phase modulator 37 _1, and D latch 43 consisting of D flip-flop, consisting of the changeover switch 44. The D latch 43 outputs a normal-phase output and a negative-phase output of the 1-bit dither signal in response to a clock CK supplied from the clock input terminal 42 and equal to the transmission rate when the 1-bit dither signal is input. Switch 45
Generates the phase modulation signal by alternately outputting the positive-phase output and the negative-phase output according to the clock CK.

The clock CK is, for example, a sampling frequency of 44.1 KHz (=
Fs) (64 Fs clock). That is, the transmission rate of the 1-bit dither signal output after being ΣΔ modulated by the ΣΔ modulator is set to 3 of Fs.
If it is doubled, the 1-bit audio signal input to the phase modulation unit 37 at the data rate of 32 Fs is 64 Fs.
For example, the signal is latched by the D latch 43 at the rising edge by the s clock CK.

The D-latch 43 switches the positive-phase output from the positive terminal Q to the selected terminal a of the switch 44 and switches the negative-phase output from the inverting terminal Q bar (denoted as Q *). b.

The changeover switch 44 alternately arranges the inverted output of the D-latch 43 when the 64Fs clock CK is "1" and the inverted output when the 64Fs clock is "0" to generate a phase modulation signal. As shown in FIG.
Is switched to the selected terminal a or the selected terminal b.

The phase modulation is a modulation method in which the polarity is inverted when the data is "1" and downward when the data is "0". If the data rate after the modulation is twice that before the modulation,
The data is converted to 01 for "1" and to 10 for "0".

Therefore, the phase modulation signal Dth_pm ₍₁₎ switched and output by the changeover switch 44 is 6
It becomes a 1-bit dither signal of 4Fs. 1-bit dither signal of the 64Fs is a 1 bit 32Fs before being supplied to the phase modulator 37 ₂ of the next stage.

By repeatedly performing such phase modulation processing and performing multiple phase modulation, finally, the phase modulator 37 _i
The phase modulation signal Dth_pm _(i) output from the multiplexing section is composed of only high-frequency components in which noise components in the audible range have been sufficiently reduced.

[0099] Also, showing the detailed structure of another embodiment of a phase modulator 37 ₁ in FIG. 19. Another specific example includes a D latch 53 and a shift register 54. The D latch 53 is the same as the D latch 43 shown in FIG.

The shift register 54 controls loading and shifting of data input at the 32Fs clock CK,
The 1-bit dither signal phase-modulated by the 64 Fs clock CK is transmitted from the output terminal 56 to the outside.

Since the shift register 54 is a synchronous load, when the 32Fs clock CK is "1", the positive-phase output and the negative-phase output of the D latch 53 are supplied to the input terminal H and the input terminal at the rising edge of the 64Fs clock CK. When the data is loaded from G and the 32Fs clock CK is "0", the positive-phase output and the negative-phase output are shifted at the rising edge of the 64Fs clock CK. Thus, a 1-bit dither signal is generated at 64 Fs.

As described above, since the 1-bit dither signal is used in the ΔΣ modulator shown in FIG. 17, the audible range component can be attenuated without changing the 1-bit signal. The audible range component can be attenuated while eliminating the need for the HPF filter used in the third embodiment. Further, multiplex phase modulation using the phase modulators 37 ₁ ... 37 _i can be performed on the 1-bit dither signal, and the audible range component can be further attenuated.

That is, by performing the phase modulation several times in a multiplex manner, it is possible to generate random noise having frequency characteristics completely free of audible range components, while maintaining a 1-bit signal. Further, when using an HPF filter as shown in FIG. 15 when configuring with hardware or the like, the scale becomes large to design a filter capable of sufficiently attenuating the audible range component, but as shown in FIG. The configuration using the modulation has an advantage that the configuration can be easily performed on a small scale.

As described above, the ΔΣ modulator according to the third embodiment and the ΔΣ modulator according to the fourth embodiment have a sound quality by providing a frequency characteristic in the quantization of the variable threshold level. Without deterioration and Δ
ΣThe effect of suppressing distortion dependent on the input signal unique to modulation is realized.

Further, the Δ 装置 modulator of the fourth embodiment in which random noise such as dither has frequency characteristics while maintaining a high-speed 1-bit audio stream can be easily and small-scaled by using multiple phase modulation. This is very advantageous for hardware design and the like as compared with the case where a filter is used.

[0106] Also in the third and fourth embodiments, the calculation of the optimal variable threshold level has been performed based on the amplitude obtained by the integrator within 2 _e of the last stage, the limiter value L
_end may be used.

[0107]

The delta-sigma modulator according to the present invention has the following features.
Since the threshold level referred to in the quantization processing performed by the quantization means is relatively varied with respect to the time axis, distortion depending on the input signal is suppressed, and only a desired signal component is ΔΣ-modulated by 1 bit. A digital signal can be generated.

In the delta-sigma modulation method according to the present invention, the threshold level referred to in the quantization process in the quantization step is relatively varied with respect to the time axis. Σ modulated only the signal components of
A bit digital signal can be generated.

The digital signal processing device and the digital signal processing method according to the present invention suppress the distortion depending on the input signal peculiar to the ΔΣ modulation without deteriorating the sound quality by giving frequency characteristics to random noise.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a ΔΣ modulation device according to an embodiment of the present invention.

FIG. 2 is a diagram for explaining a 1-bit quantizer used in the ΔΣ modulator.

FIG. 3 is a schematic configuration diagram of an example of an N-order ΔΣ modulation device.

FIG. 4 is a flowchart for designing a ΔΣ modulator using a method for calculating a variable threshold level.

FIG. 5 is a block diagram illustrating a configuration of a ΔΣ modulation device including a plurality of integrators.

FIG. 6 shows a 1-bit audio signal (64F) generated when a sine wave signal having a frequency of 1 KHz is input to the ΔΣ modulator having a fifth-order local feedback loop shown in FIG.
It is a spectrum distribution figure of s).

FIG. 7 is a block diagram illustrating a configuration of a ΔΣ modulation device according to a first comparative example.

FIG. 8 shows a 1-bit audio signal (64 Fs) generated when a sine wave signal having a frequency of 1 KHz is input to a ΔΣ modulator having a fifth-order local feedback loop including the ΔΣ modulator of the first comparative example. 3 is a spectrum distribution diagram of FIG.

FIG. 9 is a block diagram illustrating a configuration of a ΔΣ modulator according to a second comparative example.

FIG. 10 shows a ΔΣ modulator having a fifth-order local feedback loop including the ΔΣ modulator of the second comparative example, with a frequency of 1 kHz.
FIG. 4 is a spectrum distribution diagram of a 1-bit audio signal (64 Fs) generated when a sine wave signal of FIG.

FIG. 11 is a block diagram illustrating a configuration of a ΔΣ modulation device according to a third comparative example.

FIG. 12 is a block diagram illustrating a configuration of a ΔΣ modulation device according to a second embodiment of the present invention.

FIG. 13 is a block diagram illustrating a schematic configuration of an N-order ΔΣ modulation device, which is a modification of the second embodiment.

FIG. 14 shows a random noise signal R from a random signal generator constituting the N-order ΔΣ modulator shown in FIG. 13;
FIG. 6 is a diagram showing _n time domain characteristics (a) and frequency domain characteristics (b).

FIG. 15 shows an Nth-order Δ according to a third embodiment of the present invention.
FIG. 3 is a block diagram illustrating a schematic configuration of a modulation device.

16 is a time-domain characteristic (a) and a frequency-domain characteristic (b) of a random noise signal _{Dth_hf} from which a high-frequency component is extracted by an HPF filter included in the N-order ΔΣ modulator illustrated in FIG. FIG.

FIG. 17 shows an Nth-order Δ according to a fourth embodiment of the present invention.
FIG. 3 is a block diagram illustrating a schematic configuration of a modulation device.

FIG. 18 is a diagram showing a configuration of a specific example of a phase modulator included in the N-order Δ 装置 modulator shown in FIG. 17;

FIG. 19 is a diagram showing a configuration of another specific example of the phase modulator included in the N-order ΔΣ modulator shown in FIG. 17;

FIG. 20 is a block diagram illustrating a configuration of a conventional ΔΣ modulation device.

FIG. 21 is a diagram for explaining a 1-bit quantizer used in the ΔΣ modulator shown in FIG. 20;

FIG. 22 shows a ΔΣ modulator having a fifth-order local feedback loop including the ΔΣ modulator shown in FIG.
FIG. 4 is a spectrum distribution diagram of a 1-bit audio signal (64 Fs) generated when a sine wave signal of FIG.

[Explanation of symbols]

1 adder, 2 integrator, 31 bit quantizer, 78
1-bit quantizer, 80 ΔΣ modulator, 81 local feedback loop

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Masayoshi Noguchi 6-7-35 Kita-Shinagawa, Shinagawa-ku, Tokyo Sony Corporation F-term (reference) 5J064 AA01 BA03 BB02 BB12 BB14 BC08 BC10 BC11 BC16 BC22 BD02 BD03

Claims (34)

[Claims] 1. A delta-sigma modulation device for performing a delta-sigma modulation process on an input signal and outputting a 1-bit digital signal, comprising: an arithmetic unit for differentiating the input signal and a 1-bit digital signal that is a feedback signal; Integrating means for integrating the difference signal in the calculating means; quantizing means for performing a quantization process on the integrated output of the integrating means to output a 1-bit digital signal; feedback of the quantized output of the quantizing means to the feedback A delta-sigma modulation device, comprising: a feedback loop that feeds back to the arithmetic unit as a signal, wherein a threshold level referred to in a quantization process in the quantization unit is variably controlled with respect to a time axis. . 2. The delta-sigma modulation apparatus according to claim 1, wherein said quantization means changes a threshold level referred to in said quantization processing with respect to a time axis. 3. The delta-sigma modulation device according to claim 1, wherein the variable range of the threshold level is determined based on the amplitude of an integration means connected immediately before the quantization means. 4. The integrator comprises a plurality of stages of cascade-connected integrators, and the quantizer performs a quantization process only on the integrated output of the integrator connected immediately before, and performs one step.
2. The delta-sigma modulator according to claim 1, wherein the delta-sigma modulator outputs a bit digital signal. 5. The delta-sigma modulation apparatus according to claim 4, wherein said quantization means changes a threshold level referred to in said quantization processing with respect to a time axis. 6. The integrator includes a plurality of stages of cascade-connected integrators, and determines a variable range of the threshold level based on an amplitude of an integrator connected immediately before the quantizer. The delta-sigma modulator according to claim 1, wherein: 7. A delta-sigma modulation method for performing a delta-sigma modulation process on an input signal to output a 1-bit digital signal, comprising: An integration step of integrating the difference signal in the calculation step; a quantization step of performing a quantization process on the integration output of the integration step to output a 1-bit digital signal; A feedback step of returning to the operation step as a signal, wherein a threshold level referred to in the quantization processing in the quantization step is variably controlled with respect to a time axis. . 8. The delta-sigma modulation method according to claim 7, wherein said quantization step varies a threshold level referred to in said quantization processing with respect to a time axis. 9. The delta-sigma modulation method according to claim 7, wherein the variable range of the threshold level is determined based on the amplitude of an integration step performed immediately before the quantization step. 10. The integration step is a step of cascading a plurality of integrations, and the quantization step is to perform a quantization process only on the output of the integration performed immediately before to output a 1-bit digital signal. The delta-sigma modulation method according to claim 7, wherein: 11. The delta-sigma modulation method according to claim 10, wherein said quantization step varies a threshold level referred to in said quantization processing with respect to a time axis. 12. The integration step is a step of cascading a plurality of integrations, and the quantization step is to determine a variable range of the threshold level based on an amplitude obtained by an integration performed immediately before. The delta-sigma modulation method according to claim 7, wherein: 13. An arithmetic unit for calculating a difference between a feedback signal and an input signal, an integrating unit for integrating an output signal of the arithmetic unit, a noise generating unit for generating random noise, and an output from the noise generating unit. Addition means for adding random noise to the integration output of the integration means; quantization means for quantizing the addition output from the addition means by 1 bit; and 1-bit digital signal output from the quantization means to the feedback signal. And a feedback loop means for feeding back to the arithmetic means. 14. A gain adjusting means for adjusting a gain of random noise generated by said noise generating means on the basis of an amplitude of an integrating means connected immediately before said adding means, wherein said adding means includes: 14. The digital signal processing device according to claim 13, wherein random noise whose gain has been adjusted by the adjusting means is supplied. 15. The gain adjustment unit according to claim 14, wherein a threshold value for adjusting the gain of the random noise is determined based on an amplitude of an integration unit connected immediately before the addition unit. Digital signal processing equipment. 16. The digital signal processing apparatus according to claim 13, wherein said integrating means comprises a plurality of stages of cascaded integrators. 17. The apparatus according to claim 17, wherein said gain adjusting means adjusts a gain of the random noise generated by said noise generating means based on an amplitude of an integrator connected immediately before said adding means. 17. The digital signal processing device according to item 16. 18. A calculation step for calculating a difference between a feedback signal and an input signal, an integration step for integrating an output signal of the calculation step, a noise generation step for generating random noise, and an output from the noise generation step. An addition step of adding random noise to the integration output of the integration step; a quantization step of quantizing the addition output from the addition step by 1 bit; and a 1-bit digital signal output from the quantization step to the feedback signal. A feedback step of returning to the operation step. 19. A gain adjusting step for adjusting a gain of random noise generated in the noise generating step based on an amplitude in an integrating step performed immediately before the adding step, wherein the adding step includes the step of: 19. The digital signal processing method according to claim 18, wherein random noise whose gain is adjusted in the adjusting step is supplied. 20. The gain adjustment step according to claim 19, wherein a threshold value for adjusting the gain of the random noise is determined based on an amplitude of an integration step performed immediately before the addition step. Digital signal processing method. 21. A calculating means for calculating a difference between the feedback signal and the input signal; an integrating means for integrating the difference signal in the calculating means; a noise generating means for generating random noise; Filter means for extracting a high-frequency component of the noise signal, gain adjustment means for performing gain adjustment on the output from the filter means, and a noise signal comprising the high-frequency component gain-adjusted by the gain adjustment means. Adding means for adding the output signal from the integrating means; quantizing means for quantizing the added output from the adding means by 1 bit; 1-bit digital signal output from the quantizing means as the feedback signal. A digital signal processing device comprising: feedback loop means for feeding back. 22. The digital signal processing device according to claim 21, wherein a threshold value of said gain adjusting means is determined based on an integrated value of said integrating means. 23. An operation step of calculating a difference between a feedback signal and an input signal, an integration step of integrating the difference signal in the operation step, a noise generation step of generating random noise, and an output from the noise generation step. A filtering step of extracting a high-frequency component of the noise signal, a gain adjustment step of performing gain adjustment on an output from the filtering step, and a noise signal including the high-frequency component gain-adjusted in the gain adjustment step. An addition step of adding the output signal from the integration step; a quantization step of quantizing the added output from the addition step by 1 bit; and a 1-bit digital signal output from the quantization step as the feedback signal. A digital signal processing method comprising: a feedback step of returning. 24. The digital signal processing method according to claim 23, wherein a threshold value in said gain adjusting step is determined based on an integral value obtained in said integrating step. 25. A calculating means for calculating a difference between the feedback signal and the input signal; an integrating means for integrating the difference signal in the calculating means; a noise generating means for generating a random 1-bit digital signal; Phase modulation means for phase-modulating a random 1-bit digital signal output from the means, gain adjustment means for performing gain adjustment on the output from the phase modulation means, Adding means for adding a noise signal comprising a frequency component and an output signal from the integrating means; quantizing means for quantizing the output from the adding means by 1 bit; and a 1-bit digital signal outputted from the quantizing means. And a feedback loop means for feeding back a feedback signal as the feedback signal. 26. The digital signal processing device according to claim 25, wherein a threshold value in said gain adjusting means is determined based on an integrated value in said integrating means. 27. The digital signal processing apparatus according to claim 25, wherein said phase modulation means comprises a plurality of cascaded phase modulators. 28. The phase modulating means outputs an input random 1-bit digital signal as a positive-phase output and a negative-phase output based on a first clock. 26. The digital signal processing device according to claim 25, wherein output is performed alternately based on a second clock having a clock twice as large as the first clock. 29. The phase modulating means outputs an input random 1-bit digital signal as a positive-phase output and a negative-phase output based on a first clock, and 28. The digital signal processing device according to claim 27, wherein the digital signal is output alternately based on a second clock having a clock twice as large as the first clock. 30. An operation step of calculating a difference between a feedback signal and an input signal; an integration step of integrating the difference signal in the operation step; a noise generation step of generating a random 1-bit digital signal; A phase modulation step of performing phase modulation on a random 1-bit digital signal output from the step; a gain adjustment step of performing gain adjustment on an output from the phase modulation step; An addition step of adding a noise signal composed of a frequency component and an output signal from the integration step; a quantization step of quantizing the output from the addition step by 1 bit; and a 1-bit digital signal output from the quantization step And a feedback step of feeding back the feedback signal as the feedback signal. 31. The digital signal processing method according to claim 30, wherein a threshold value in said gain adjustment step is determined based on an integrated value in said integration step. 32. The digital signal processing method according to claim 30, wherein in the phase modulation step, a phase modulation process is performed a plurality of times. 33. The phase modulating step comprising: outputting a random 1-bit digital signal as a positive-phase output and a negative-phase output based on a first clock; 31. The digital signal processing method according to claim 30, wherein output is performed alternately based on a second clock having a clock twice as large as the first clock. 34. The phase modulating step includes: outputting a random 1-bit digital signal input as a positive-phase output and a negative-phase output based on a first clock; 33. The digital signal processing method according to claim 32, wherein a phase modulation process of alternately outputting a plurality of times based on a second clock having a clock twice the first clock is performed a plurality of times.