JP2018125964A - Motor control device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress a switching loss by reducing the number of times of switching a switching element in a switching circuit.SOLUTION: A motor control device has a driver generating a driving voltage which drives a motor by switching a switching element based on a switching signal, a command value generator generating a voltage command value which drives the motor on the basis of a speed command value, and a signal generator generating the switching signal from the voltage command value generated by the command value generator. The signal generator is a ΔΣ modulator including a bit converter converting an inputted multi-bit signal into a 1-bit signal and outputting the switching signal, a subtractor outputting a signal obtained by subtracting the switching signal outputted by the bit converter from the voltage command value generated by the command value generator, an integrator integrating the signal outputted by the subtracter, and a quantizer outputting a multi-bit signal which is an integrated result by the integrator quantized by multibit to the bit converter.SELECTED DRAWING: Figure 7

Description

  The present invention relates to a motor control device.

  In general, a motor control device that drives and controls a motor by vector control generates a d-axis current command value and a q-axis current command value so that the rotational speed of the motor becomes a speed command value (target speed). A d-axis voltage command value and a q-axis voltage command value are generated from the current command value and the q-axis current command value. Further, the motor control device converts the d-axis voltage command value and the q-axis voltage command value into a three-phase voltage command value, and the PWM (Pulse Width Modulation) generator generates the PWM based on the three-phase voltage command value. A signal is generated and output to an IPM (Intelligent Power Module). The IPM performs switching control according to the input PWM signal, thereby driving the motor by applying three-phase voltages (U-phase voltage Vu, V-phase voltage Vv, and W-phase voltage Vw) to the motor.

  Specifically, the input signals of the IPM generated by the PWM generator (U-phase upper arm signal Up, V-phase upper arm signal Vp, W-phase upper arm signal Wp, U-phase lower arm signal Un, V-phase lower arm) The signal Vn and the W-phase lower arm signal Wn) are input signals of transistors such as IGBTs (Insulated Gate Bipolar Transistors) and MOS-FETs (Metal Oxide Semiconductor-Field Effect Transistors). The IPM is an inverter circuit configured by bridge-connecting these transistors as switching elements, and includes input signals (U-phase upper arm signal Up, V-phase upper arm signal Vp, W-phase upper arm signal Wp, U-phase lower arm signal). Three-phase voltages (U-phase voltage Vu, V-phase voltage Vv, and W-phase voltage Vw) are generated based on Un, V-phase lower arm signal Vn, and W-phase lower arm signal Wn.

  Here, the magnitude and frequency of the three-phase voltage (U-phase voltage Vu, V-phase voltage Vv, W-phase voltage Vw) are controlled by the input signal of the PWM generator. The PWM signal generated by the PWM generator based on this input signal is input to the IPM, and a three-phase voltage (Vu, Vv, Vw) having characteristics according to the input signal is generated, thereby rotating the motor. Control speed, etc. Therefore, in order to perform motor control with high accuracy, it is desired to generate the PWM signal with high accuracy. As a means for improving the generation of the PWM signal, there is a case where the sampling frequency (carrier frequency) of the input signal of the PWM generator is increased. Thereby, the reproducibility (accuracy) of the input signal by the PWM signal generated by the PWM generator is increased.

  However, increasing the sampling frequency means that although the reproducibility of the input signal by the PWM signal is improved, the number of times of switching of the IPM is increased, that is, the number of times of switching of the transistor (switching element) is increased. As a result, switching loss increases and the efficiency of the motor drive device is reduced. For example, switching for one phase is not performed using two-phase modulation that outputs a two-phase PWM signal of three phases. There is a technique.

  On the other hand, for example, there is a conventional technique using a PDM (Pulse Density Modulation) signal by a 1-bit ΔΣ (delta sigma) modulator as a control signal for a switching element (see, for example, Patent Document 1). By using the PDM signal as a control signal for the switching element, the number of times of switching is reduced and switching loss is suppressed.

  Also, for example, a PDM signal generated using a multi-bit ΔΣ modulator in which the number of output bits of the quantizer is more than 1 bit is input to a multi-input IPM in which each phase input corresponds to multi-bit. A three-phase voltage (U-phase voltage Vu, V-phase voltage Vv, W-phase voltage Vw) having characteristics according to the input signal is generated, and the generated three-phase motor is supplied to a multi-input motor corresponding to multi-bit. There is a conventional technique that improves the reproducibility of an input signal by applying phase voltages (U-phase voltage Vu, V-phase voltage Vv, and W-phase voltage Vw) (see, for example, Patent Document 2).

JP-A-6-225527 International Publication No. 2012/133241

  However, in the above-described prior art, when performing two-phase modulation, the accuracy (resolution) of the time axis (horizontal axis) is increased in order to generate the PWM signal with high accuracy, and therefore depends on the sampling frequency (carrier frequency). As a result, there is still a problem that the number of times of switching increases and switching loss increases. In addition, when a 1-bit ΔΣ modulator is used to reduce the number of switching times compared to the PWM method, the accuracy (resolution) of the amplitude axis (vertical axis) is increased in order to improve the reproducibility of the input signal by the PDM signal. Therefore, the sampling frequency (carrier frequency) of the 1-bit ΔΣ modulator needs to be sufficiently higher than the frequency of the input signal (oversampling rate is increased), the sampling frequency (carrier frequency) is increased, and the switching frequency is increased There is a problem of increasing. In addition, when a multi-bit ΔΣ modulator is used, there is a problem that applicable IPMs and motors are not versatile.

  The present invention has been made in view of the above, and an object of the present invention is to provide a motor control device that suppresses switching loss by reducing the number of switching times of a switching element in a switching circuit.

  In order to solve the above-described problem, an example of an embodiment of the present invention is based on a speed control value and a motor control device that generates a drive voltage for driving a motor by switching a switch element based on a switching signal. A command value generator that generates a voltage command value for driving the motor, and a signal generator that generates a switching signal from the voltage command value generated by the command value generator. The signal generator converts the input multi-bit signal into a 1-bit signal and outputs a switching signal, and the voltage command value generated by the command value generator, which is output by the bit converter. A subtractor that outputs a signal obtained by subtracting the switching signal, an integrator that integrates the signal output by the subtractor, and a quantum that outputs a multibit signal obtained by quantizing the integration result by the integrator to a bit converter. A delta-sigma modulator including a generator.

  According to an example of the embodiment of the present invention, for example, the switching loss of the switching element in the switching circuit can be reduced to suppress the switching loss.

FIG. 1 is a diagram illustrating an example of a motor control device according to a basic technique. FIG. 2 is a diagram illustrating an example of the configuration of the IPM according to the basic technology. FIG. 3 is a diagram illustrating an example of a first-order ΔΣ modulator according to the basic technique. FIG. 4 is a diagram illustrating an example of the operation of the quantizer according to the basic technique. FIG. 5 is a diagram illustrating an example of a second-order ΔΣ modulator (integrator series connection method) according to the basic technique. FIG. 6 is a diagram illustrating an example of a secondary ΔΣ modulator (MASH system) according to the basic technique. FIG. 7 is a diagram illustrating an example of a configuration of a multi-bit first-order ΔΣ modulator that outputs a 1-bit PDM signal according to the disclosed technology. FIG. 8 is a diagram illustrating an example of a configuration of a multi-bit second-order ΔΣ modulator (integrator series connection method) that outputs a 1-bit PDM signal according to the disclosed technique. FIG. 9 is a diagram illustrating an example of a configuration of a multi-bit secondary ΔΣ modulator (MASH system) that outputs a 1-bit PDM signal according to the disclosed technique. FIG. 10A is a diagram illustrating an example of an outline of a bit converter according to the disclosed technique. FIG. 10B is a diagram illustrating an example of an outline of a bit converter according to the disclosed technique. FIG. 11 is a diagram illustrating an example of conversion in the vertical axis direction (resolution) −horizontal axis direction (time) of the quantizer. FIG. 12 is a diagram illustrating an example of a motor control device according to the embodiment. FIG. 13 is a diagram illustrating an example of the bit converter according to the embodiment. FIG. 14 is a flowchart illustrating an example of the bit conversion processing according to the embodiment. FIG. 15A is a diagram illustrating an example of a simulation result (in the case of an input amplitude of 130 V) of an output signal (quantizer output) with respect to an input signal when a first-order ΔΣ modulator according to the related art is used as a PDM generator. . FIG. 15B is a diagram illustrating an example of a simulation result (in the case of an input amplitude of 40 V) of an output signal (quantizer output) with respect to an input signal when a first-order ΔΣ modulator according to the related art is used as a PDM generator. . FIG. 16A is a diagram illustrating a simulation result (in the case of an input amplitude of 130 V) of an output signal (quantizer output) with respect to an input signal when the first-order ΔΣ modulator according to the embodiment is used as a PDM generator. FIG. 16B is a diagram illustrating an example of a simulation result (in the case of an input amplitude of 40 V) of an output signal (quantizer output) with respect to an input signal when the first-order ΔΣ modulator according to the embodiment is used as a PDM generator. .

  Hereinafter, basic techniques and embodiments of a motor control device according to the present invention will be described in detail with reference to the drawings. The present invention is not limited to the basic technology and the embodiment. The motor control device shown in the following basic technology and embodiment will be described as a motor control device that drives a motor used in an air conditioner or the like, but is not limited to this and can be widely applied to motors in general. Embodiments of the basic technology described below and modifications thereof can be appropriately combined and implemented within a consistent range.

  Note that the basic technology and embodiments described below are merely examples, and do not limit the disclosed technology. In addition, the basic technology and the embodiments described below and modifications thereof can be combined as appropriate within a consistent range. In addition, the basic technology and the embodiments described below and modifications thereof are mainly shown for the configuration and processing according to the disclosed technology, and description of the other configuration and processing is simplified or omitted. Further, in the basic technique and embodiment described below and modifications thereof, the same reference numerals are given to the same configuration and processing, and the description of the above-described configuration and processing is omitted.

[Basic technology]
(Motor control device for basic technology)
Prior to the description of the embodiments, basic technology as a background will be described. FIG. 1 is a diagram illustrating an example of a motor control device according to a basic technique. The motor control device 100X includes a subtractor 11, a speed controller 12, an excitation current controller 13, a subtractor 14, a subtractor 15, a d-axis current controller 16, a q-axis current controller 17, a non-interacting controller 18, A subtractor 19, an adder 20, a dq / 3φ converter 21, a PWM (Pulse Width Modulation) generator 22, an IPM (Intelligent Power Module) 23, a resistor R constituting a shunt current detector, a 3φ current calculator 24, A 3φ / dq converter 25, an axis error calculation processing unit 26, a PLL controller 29, a position estimator 30, and a 1 / Pn processor 31 are included. The motor control device 100X includes a switch SW including a contact point CO1, a contact point CO2, and a contact point CO3.

The subtractor 11 is an actual current angular velocity output by the 1 / Pn processor 31 from the speed command value (target speed, here, the mechanical angle target speed) ωm ^* input to the motor control device 100X. A speed deviation (mechanical angular speed deviation) Δω obtained by subtracting the speed (mechanical angular speed) ωm is output to the speed controller 12.

The speed controller 12 generates a q-axis current command value Iq ^* such that the speed deviation Δω output from the subtractor 11 is small, and outputs the q-axis current command value Iq ^* to the excitation current controller 13 and the subtractor 15. The excitation current controller 13 generates a d-axis current command value Id ^* from the q-axis current command value Iq ^* output from the speed controller 12 and outputs it to the subtractor 14. Here, the speed controller 12 and the excitation current controller 13 are collectively referred to as a current command value generation unit. The d-axis and q-axis represent coordinate axes of a two-phase rotating coordinate system, and Id and Iq and Vd and Vq described later are current and voltage on the coordinate axes.

The subtracter 14 subtracts the d-axis current Id output from the 3φ / dq converter 25 from the d-axis current command value Id ^* output from the excitation current controller 13 to generate a d-axis current deviation ΔId. Output to the shaft current controller 16. The subtractor 15 subtracts the q-axis current Iq output from the 3φ / dq converter 25 from the q-axis current command value Iq ^* output from the speed controller 12 to generate a q-axis current deviation ΔIq to generate the q-axis Output to the current controller 17.

The d-axis current controller 16 generates a d-axis voltage command value Vd ^** from the d-axis current deviation ΔId output from the subtractor 14. The q-axis current controller 17 generates a q-axis voltage command value Vq ^** from the q-axis current deviation ΔIq output from the subtracter 15.

The non-interacting controller 18 generates a non-interacting correction value for canceling interference between the d-axis and the q-axis and controlling each independently. Specifically, for decoupling the d-axis voltage command value Vd ^** from the d-axis current Id output from the 3φ / dq converter 25 and the electrical angle estimated speed ωe output from the PLL controller 29. A d-axis non-interacting correction value Vda is generated and output to the subtracter 19. Further, the non-interacting controller 18 determines the q-axis voltage command value Vq ^** from the q-axis current Iq output from the 3φ / dq converter 25 and the electrical angle estimated speed ωe output from the PLL controller 29. A q-axis non-interacting correction value Vqa for interfering is generated and output to the adder 20.

The subtractor 19 subtracts the d-axis non-interacting correction value Vda output from the non-interacting controller 18 from the d-axis voltage command value Vd ^** output from the d-axis current controller 16 to subtract the d-axis voltage. the command value ^{Vd **} and generates a non-interference with the d-axis voltage command value Vd ^*, and outputs it to the dq / 3 [phi] converter 21. The adder 20 adds the q-axis non-interacting correction value Vqa output from the non-interacting controller 18 to the q-axis voltage command value Vq ^** output from the q-axis current controller 17 to add the q-axis voltage. the command value ^{Vq **} generates decoupling the q-axis voltage command value Vq ^*, and outputs it to the dq / 3 [phi] converter 21.

The dq / 3φ converter 21 uses the electrical angle phase (dq axis phase) θe, which is the current rotor position, output from the position estimator 30 to make the two-phase d-axis voltage command value Vd non-interfering. ^{* And} q-axis voltage command value Vq ^* are converted into U-phase output voltage command value Vu ^* , V-phase output voltage command value Vv ^* , and W-phase output voltage command value Vw ^* , which are three-phase voltage command values. Then, the dq / 3φ converter 21 outputs the U-phase output voltage command value Vu ^* , the V-phase output voltage command value Vv ^* , and the W-phase output voltage command value Vw ^* to the PWM generator 22 that is the signal generator 2X. . Note that Vu ^* , Vv ^*, and Vw ^* and Iu, Iv, and Iw described later are voltages and currents in a three-phase fixed coordinate system.

The PWM generator 22 generates a 6-phase PWM signal from the U-phase output voltage command value Vu ^* , the V-phase output voltage command value Vv ^* , the W-phase output voltage command value Vw ^*, and the PWM carrier signal, and sends it to the IPM 23. Output.

  The IPM 23 serving as the driver 3X is supplied with an external AC voltage applied to the U phase, V phase, and W phase of the motor M based on the six-phase PWM signal output from the PWM generator 22. The DC voltage Vdc is generated by conversion, and each AC voltage is applied to the U phase, V phase, and W phase of the motor M.

  When the contact CO1 of the switch SW is connected to the contact CO2, the 3φ current calculator 24 detects one shunt current by the six-phase PWM switching information output from the PWM generator 22 and the resistor R by the one shunt method. The U-phase current Iu, V-phase current Iv, and W-phase current Iw of the motor M are calculated from the bus current detected by the method.

  Alternatively, when the contact CO1 of the switch SW is connected to the contact CO3, the 3φ current calculator 24 uses the 2CT method to select 2 out of the U-phase current Iu, V-phase current Iv, and W-phase current Iw of the motor M. The U-phase current Iu and the V-phase current Iv are detected by two CTs (Current Transformers), and the remaining W-phase current Iw is calculated from the relational expression of Iu + Iv + Iw = 0. The 3φ current calculator 24 outputs the calculated U phase current Iu, V phase current Iv, and W phase current Iw of the motor M to the 3φ / dq converter 25. Note that only one method such as the 1-shunt current detection method and the 2CT method may be used for current detection. In that case, a detection circuit and a switch SW other than the method to be used are unnecessary.

  The 3φ / dq converter 25 uses the electrical angle phase θe output from the position estimator 30 to output the three-phase U-phase current Iu, V-phase current Iv, and W-phase current Iw output from the 3φ current calculator 24. Is converted into a two-phase d-axis current Id and a q-axis current Iq. The 3φ / dq converter 25 subtracts the d-axis current Id from the subtractor 14, the non-interacting controller 18, and the axis error calculation processing unit 26. Each is output to the axis error calculation processing unit 26.

The axis error calculation processing unit 26 outputs the d-axis voltage command value Vd ^* output from the subtracter 19 and the q-axis voltage command value Vq ^* output from the adder 20, and the d-axis output from the 3φ / dq converter 25. An axis error variation Δθ is calculated from the current Id and the q-axis current Iq and output to the PLL controller 29. Here, the axis error is a deviation between the actual dq axis and the control dq axis.

  The PLL controller 29 calculates an electrical angle estimated speed ωe, which is an estimated angular speed of rotation of the motor, from the axis error fluctuation Δθ output from the axis error calculation processing unit 26, and the non-interacting controller 18. The data is output to the position estimator 30 and the 1 / Pn processor 31, respectively.

  The position estimator 30 calculates an electrical angle phase (dq axis phase) θe for estimating the rotor position from the electrical angle estimated speed ωe output from the PLL controller 29. Position estimator 30 then outputs electrical angle phase θe to dq / 3φ converter 21 and 3φ / dq converter 25, respectively.

  The 1 / Pn processor 31 divides the estimated electrical angle speed ωe output from the PLL controller 29 by the pole pair number Pn of the motor M, and obtains the estimated actual speed (actual angular speed) ωm. Calculate and output to the subtractor 11.

Here, the subtractor 11, speed controller 12, excitation current controller 13, subtractor 14, subtractor 15, d-axis current controller 16, q-axis current controller 17, non-interacting controller 18, subtraction 19, adder 20, dq / 3φ converter 21, resistance R, 2 CT, 3φ current calculator 24, 3φ / dq converter 25, axis error calculation processing unit 26, PLL controller 29, position estimator 30 , 1 / Pn processor 31 and switch SW are command value generator 1X. The d-axis voltage command value Vd ^* and the q-axis voltage command value Vq ^* may be used as voltage command values, and the dq / 3φ converter 21 may be added to the signal generator 2X.

(IPM for basic technology)
FIG. 2 is a diagram illustrating an example of the configuration of the IPM according to the basic technology. As shown in FIG. 2, the IPM 23 is based on the U-phase output voltage command value Vu ^* , the V-phase output voltage command value Vv ^* , and the W-phase output voltage command value Vw ^* generated by the dq / 3φ converter 21. A UVW three-phase AC voltage is generated from the PWM signal generated by the PWM generator 22 and supplied to the motor M. The IPM 23 includes U-phase switching elements 23Up and 23Un, V-phase switching elements 23Vp and 23Vn, and W-phase switching elements 23Wp and 23Wn.

  The switching elements 23Up, 23Vp, and 23Wp are upper arm switching elements, and the switching elements 23Up, 23Vp, and 23Wp are lower arm switching elements. The switching elements 23Up, 23Un, 23Vp, 23Vn, 23Wp, and 23Wn are transistors such as IGBT (Insulated Gate Bipolar Transistor) and MOS-FET (Metal Oxide Semiconductor-Field Effect Transistor).

The IPM 23 generates a switching signal based on a PWM signal generated from the U-phase output voltage command value Vu ^* , the V-phase output voltage command value Vv ^* , and the W-phase output voltage command value Vw ^*. The elements 23Up, 23Un, 23Vp, 23Vn, 23Wp, and 23Wn are turned on and off to generate a UVW three-phase AC voltage that is a driving voltage for driving the motor M and supply the generated voltage to the motor M.

(Improvement of motor control accuracy using ΔΣ modulator)
Here, in order to control the motor M more accurately, the U-phase output voltage command value Vu ^* , the V-phase output voltage command value Vv ^* , and the W-phase output voltage command value output from the dq / 3φ converter 21 are used. It is desired to generate an input signal such as a PWM signal input to the IPM 23 with high accuracy from Vw ^* . Furthermore, in order to generate an input signal to be input to the IPM 23 with high accuracy while suppressing the switching loss by reducing the switching frequency, the PDM (Pulse Density Modulation) signal by the ΔΣ (delta sigma) modulator is switched by the IPM 23. Used as an element control signal.

(Primary ΔΣ modulator for basic technology)
FIG. 3 is a diagram illustrating a first-order ΔΣ modulator according to the basic technique. FIG. 3 shows an example of the configuration of the first-order ΔΣ modulator. The primary ΔΣ modulator M1 includes a subtractor S1, an integrator I1, a quantizer Q1, and a delay device D1. The subtracter S1 subtracts the feedback signal obtained by delaying the output signal of the quantizer Q1 by the delay device D1 from the input signal. The integrator I1 integrates the output signal of the subtracter S1. The quantizer Q1 uses the output signal of the integrator I1 as an input signal, and quantizes the input signal. In FIG. 3, the quantizer Q1 is replaced with an adder A1 that adds a quantization error Q10 generated at the time of quantization to an input signal. The quantizer Q1 quantizes the input signal (output signal of the integrator I1) to generate and output a PDM (Pulse Density Modulation) signal. The PDM signal becomes the output signal of the primary ΔΣ modulator M1. The output signal of the quantizer Q1 is input to the delay device D1.

(Primary ΔΣ modulator for basic technology)
FIG. 4 is a diagram illustrating an example of the operation of the quantizer according to the basic technique. As shown in FIG. 4, generally, the quantizer Q1 quantizes the input signal based on the magnitude relationship between the level of the input signal and a reference value that is a comparison value. FIG. 4 shows a case where the reference value has four levels of reference values 1 to 4. Since the quantizer Q1 can quantize the input signal with higher resolution as the number of steps of the reference value is larger, the quantization error Q generated in the quantization can be reduced. As can be seen from FIG. 4, the quantization error Q is the total area of the area corresponding to the difference between the curve indicating the input signal and the staircase wave indicating the signal after the input signal is quantized. This is because the area of the region corresponding to the difference from the staircase wave indicating the signal after the input signal is quantized becomes smaller as the number of steps of the reference value increases.

(High accuracy of ΔΣ modulator)
A ΔΣ modulator having a 1-bit quantizer performs pulse density modulation (PDM) and outputs a PDM signal. Therefore, the pulse density is high in the section where the amplitude of the input signal is large, and the pulse density is low in the section where the amplitude is small. When the sampling frequency (carrier frequency) of the ΔΣ modulator and the sampling frequency (carrier frequency) of the PWM modulator are the same, comparing the PDM signal and the PWM signal, the PDM signal is It is superior to the PWM signal. In order to improve the generation of the output signal of the ΔΣ modulator and increase the reproducibility of the input signal, the order of the ΔΣ modulator is increased and / or the resolution (number of bits) of the quantizer is increased. Is done. In addition, by increasing the sampling frequency (carrier frequency) of the ΔΣ modulator, the oversampling rate increases, and the signal-to-noise ratio (SNR) is improved and generated by the noise shaping characteristics that are characteristic of the ΔΣ modulator. The accuracy of the output signal is improved. Further, as a general technique for increasing the order of the ΔΣ modulator, an integrator series connection system in which a plurality of integrators are connected in series, and a MASH in which a plurality of primary ΔΣ modulators are cascade-connected (k-stage dependent connection). (Multi stAage noise SHaping) method.

(Secondary ΔΣ modulator for basic technology (integrator series connection method))
FIG. 5 is a diagram illustrating an example of a second-order ΔΣ modulator (integrator series connection method) according to the basic technique. FIG. 5 shows an example of the configuration of a second-order ΔΣ modulator using an integrator serial connection system in which two integrators are connected in series. As shown in FIG. 5, the secondary ΔΣ modulator M2 based on the integrator serial connection system includes subtracters S2-1 and S2-2, integrators I2-1 and I2-2, a quantizer Q2, and a delay device D2. Have.

  The subtracter S2-1 subtracts the feedback signal obtained by delaying the output signal of the quantizer Q2 by the delay unit D2 from the input signal. The integrator I2-1 integrates the output signal of the subtracter S2-1. The subtracter S2-2 subtracts the feedback signal obtained by delaying the output signal of the quantizer Q2 by the delay unit D2 from the integration result obtained by the integrator I2-1. The quantizer Q2 uses the output signal of the integrator I2-2 as an input signal and quantizes the input signal. In FIG. 5, the quantizer Q2 is replaced with an adder A2 that adds a quantization error Q20 generated during quantization to the input signal. The quantizer Q2 outputs a PDM signal obtained by quantizing the input signal (output signal of the integrator I2-2). The output signal of the quantizer Q2 is input to the delay unit D2.

  An n-order ΔΣ modulator using an integrator series connection system can increase the order by the number n of integrators connected in series. However, if the order is increased, there is a risk of oscillation due to an increase in the number of feedback circuits. Therefore, it is difficult to ensure stability at a higher order than the third order. Therefore, in order to achieve higher order than the third order, an appropriate setting of the coefficient of the integrator and a configuration for compensating the stability are required.

(Secondary ΔΣ modulator (MASH system) according to basic technology)
FIG. 6 is a diagram illustrating an example of a secondary ΔΣ modulator (MASH system) according to the basic technique. FIG. 6 shows an example of the configuration of a second-order ΔΣ modulator based on the MASH system in which two first-order ΔΣ modulators are cascade-connected. As shown in FIG. 6, the MASH-based secondary ΔΣ modulator M3 includes subtractors S3-1, S3-2, S3-3, integrators I3-1, I3-2, and quantizers Q3-1, Q3. -2, delay devices D3-1 and D3-2, differentiator d3, and adder A3-3.

  The subtractor S3-1 subtracts the first feedback signal obtained by delaying the output signal of the quantizer Q3-1 by the delay unit D3-1 from the input signal. The integrator I3-1 integrates the output signal of the subtracter S3-1. The quantizer Q3-1 uses the output signal of the integrator I3-1 as an input signal and quantizes the input signal. In FIG. 6, the quantizer Q3-1 is replaced with an adder A3-1 that adds a quantization error Q31 generated during quantization to the input signal. The quantizer Q3-1 outputs a signal obtained by quantizing the input signal (the output signal of the integrator I3-1). The output signal of the quantizer Q3-1 is input to the delay unit D3-1. The subtracter S3-3 subtracts the output signal of the quantizer Q3-1 from the output signal of the integrator I3-1.

  The subtractor S3-2 subtracts the second feedback signal obtained by delaying the output signal of the quantizer Q3-2 by the delay unit D3-2 from the output signal of the subtractor S3-3. The integrator I3-2 integrates the output signal of the subtracter S3-2. The quantizer Q3-2 uses the output signal of the integrator I3-2 as an input signal and quantizes the input signal. In FIG. 6, a quantizer Q3-2 is replaced with an adder A3-2 that adds a quantization error Q32 generated during quantization to an input signal. The quantizer Q3-2 outputs a signal obtained by quantizing the input signal (output signal of the integrator I3-2) to the differentiator d3. Further, the output signal of the quantizer Q3-2 is input to the delay unit D3-2. Differentiator d3 differentiates the output signal of quantizer Q3-2. The adder A3-3 adds the output signal of the quantizer Q3-1 and the output signal of the differentiator d3 to generate and output a PDM signal.

  The nth order (n is a natural number greater than or equal to 2 unless otherwise specified) ΔΣ modulator according to the MASH system can increase the order by the number n of cascaded primary ΔΣ modulators. The n-th order ΔΣ modulator using the MASH system cascades n stable first-order ΔΣ modulators, so it is more stable than the n-order ΔΣ modulator using the integrator series connection system in which n integrators are connected in series. It can be secured. Further, the n-th order ΔΣ modulator of the MASH system has a multi-bit final output signal by increasing the order even if the quantizer of each cascaded first-order ΔΣ modulator is 1 bit.

  As shown in FIG. 6, the second-order ΔΣ modulator according to the MASH system is the sum of the outputs of the ΔΣ modulators of the respective stages to become the output of the second-order ΔΣ modulator. For example, in FIG. 6, when the output of the first-stage ΔΣ modulator is “1” of 1 bit and the output of the second-stage ΔΣ modulator is “1” of 1 bit, the final output is “1 + 1”. = 2 ". Since “2” is represented as “10” in binary, it is a multi-bit of 2 bits. That is, even if each stage is a 1-bit quantizer, the final output becomes multibit by increasing the order (increasing the number of stages).

  Therefore, the n-order ΔΣ modulator using the integrator series connection system uses a low-order (for example, first-order) ΔΣ modulator and the number of output bits of the quantizer is multi-bit while maintaining stability. Increase the resolution. On the other hand, the n-order ΔΣ modulator based on the MASH system can increase the order and improve the resolution while ensuring stability by cascading the first-order ΔΣ modulator even if the output bit of the quantizer is 1 bit. Can be planned.

  Further, for example, a second-order ΔΣ modulator based on the MASH method quantizes a quantization error when quantized by the first-stage ΔΣ modulator by the second-stage ΔΣ modulator, and adds them, that is, 1 Information missing due to quantization in the second-stage ΔΣ modulator is supplemented by quantizing with the second-stage ΔΣ modulator and adding. In this way, the n-order ΔΣ modulator according to the MASH system adds the outputs of the quantizers at each stage, so that the resolution on the vertical axis (quantizer resolution) increases and the output becomes multibit. Note that the number of output bits of an n-order ΔΣ modulator using an integrator serial connection system is determined only by the resolution of the quantizer.

  Regardless of the integrator series connection method or the MASH method, a multi-bit output signal (PDM signal) can be driven only by an IPM having a plurality of inputs corresponding to the multi-bit. Control is only possible with motors with multiple inputs.

  Therefore, in order to drive an IPM not having a plurality of inputs corresponding to multi-bit and to control a motor not having a plurality of inputs corresponding to multi-bit, a multi-bit output signal output from the multi-bit ΔΣ modulator is The quantization noise of the ΔΣ modulator is converted to a 1-bit signal while maintaining noise shaping characteristics that are reduced by shifting to the high frequency side.

(Multi-bit ΔΣ modulator that outputs a 1-bit PDM signal according to the disclosed technology)
FIG. 7 is a diagram illustrating an example of a configuration of a multi-bit first-order ΔΣ modulator that outputs a 1-bit PDM signal according to the disclosed technology. FIG. 7 shows a basic configuration for configuring a high-order ΔΣ modulator using an integrator series connection system and a MASH system.

  The first-order ΔΣ modulator M4 shown in FIG. 7 is different from the first-order ΔΣ modulator M1 shown in FIG. 3 in that the quantization error is Q10 instead of the quantizer Q1 in the loop of the ΔΣ modulator. And a bit converter C4 in the subsequent stage of the quantizer Q1. The quantizer Q1 outputs a PDM signal obtained by quantizing the input signal (output signal of the integrator I1) with multi-bits. The bit converter C4 converts the multi-bit signal quantized by the quantizer Q1 into a 1-bit signal. The output signal of the bit converter C4 is input to the delay unit D1. Since the bit converter C4 is located in the loop of the ΔΣ modulator, noise generated by the bit converter C4 can be canceled and deterioration of noise shaping characteristics can be suppressed. That is, the noise shaping characteristic is maintained.

(Multi-bit ΔΣ modulator that outputs 1-bit PDM signal according to the disclosed technology (integrator serial connection method))
FIG. 8 is a diagram illustrating an example of a configuration of a multi-bit second-order ΔΣ modulator (integrator series connection method) that outputs a 1-bit PDM signal according to the disclosed technique. The second-order ΔΣ modulator M5 shown in FIG. 8 is a subsequent stage of the quantizer Q2 in the loop of the ΔΣ modulator as compared with the second-order ΔΣ modulator M2 in which two integrators shown in FIG. 5 are connected in series. Further includes a bit converter C5. The quantizer Q2 quantizes the input signal (the output signal of the integrator I2-2) with multiple bits. The bit converter C5 converts the multi-bit signal quantized by the quantizer Q2 into a 1-bit signal. The output signal of the bit converter C5 is input to the delay unit D2.

(Multi-bit ΔΣ modulator (MASH system) that outputs a 1-bit PDM signal according to the disclosed technology)
FIG. 9 is a diagram illustrating an example of a configuration of a multi-bit secondary ΔΣ modulator (MASH system) that outputs a 1-bit PDM signal according to the disclosed technique. The second-order ΔΣ modulator M6 shown in FIG. 9 is different from the second-order ΔΣ modulator M3 in which the two first-order ΔΣ modulators shown in FIG. 3 further includes a bit converter C6. The signal input to the delay unit D3-1 is the output of the bit converter C6. The bit converter C6 converts a multi-bit signal obtained by adding the signals quantized by the quantizers Q3-1 and Q3-2 into a 1-bit signal. The output signal of the bit converter C6 is input to the delay unit D3-1.

  The second-order ΔΣ modulator M6 quantizes the input signal in the first-stage ΔΣ modulator including the subtractor S3-1, the integrator I3-1, the quantizer Q3-1, and the delay unit D3-1. The second-stage ΔΣ modulator including the subtracters S 3-2, S 3-3, the integrator I 3-2, the quantizer Q 3-2, and the delay unit D 3-2 is a quantum generated by the first-stage ΔΣ modulator. The quantization error Q31 is quantized. Therefore, the second-order ΔΣ modulator M6 is a bit converter that receives as input a signal obtained by adding the quantized signals of the first-stage ΔΣ modulator and the second-stage ΔΣ modulator in the adder A3-3. The error generated in C6 is input to the subtracter S3-1 so that only the first-stage ΔΣ modulator is fed back. Therefore, the output of the bit converter C6 becomes a noise-shaped 1-bit PDM signal.

(Outline of bit converter)
10A and 10B are diagrams illustrating an example of an outline of a bit converter according to the disclosed technique. As shown in FIG. 10A, in the bit converters C4 to C6, for example, the comparison value to be compared with the level of the input signal has three levels of reference value 3 <reference value 2 <reference value 1, and the level of the input signal is the reference. A 2-bit output value “11” when the value is 3 or more, a 2-bit output value “10” when the input signal level is the reference value 2 or more and less than the reference value 3, and the input signal level is the reference value 1 An output signal of a quantizer that outputs a 2-bit output value “01” when the value is less than the reference value 2 and a 2-bit output value “00” when the input signal level is less than the reference value 1. Is converted to 1 bit.

  The bit converters C4 to C6 convert the output value of the maximum value “11” into the conversion value “1”, and convert the output value of the minimum value “00” into the conversion value “0”. Then, the bit converters C4 to C6 convert the output values of the intermediate value “10” and the intermediate value “01” into the converted value “1” or the converted value “0” by adding the correction amount.

  As shown in FIG. 10B, the processing of the bit converter will be conceptually described using a buffer for storing decimal numbers. For example, when the output value at the timing “2” is the intermediate value “01”, the bit converters C4 to C6 have the buffer stored value “0” at the previous timing “1”. 1 ”is stored in the buffer (as a result, the buffer becomes“ 1 ”), and an intermediate value“ 01 ”, which is an output value at timing“ 2 ”, is converted into a converted value“ 0 ”.

  Further, for example, when the output value at the timing “3” is the intermediate value “10”, the bit converters C4 to C6 have the buffer stored value “1” at the previous timing “2”. Then, “1” is extracted from the buffer and added (as a result, the buffer becomes “0”), and the intermediate value “10”, which is the output value at timing “3”, is converted into the converted value “1”.

  For example, when the output value at the timing “4” is the maximum value “11”, the bit converters C4 to C6 change the maximum value “11” that is the output value at the timing “4” to the conversion value “1”. Convert.

  Further, for example, in the bit converters C4 to C6, when the output value at the timing “6” is the intermediate value “10”, the stored value of the buffer is “0” at the previous timing “5”. Then, “1” is extracted from the buffer and added (as a result, the buffer becomes “−1”), and the intermediate value “10”, which is the output value at the timing “6”, is converted into the converted value “1”.

  Further, for example, when the output values at the timing “8” are the intermediate value “01”, the bit converters C4 to C6 have the buffer stored value “−1” at the previous timing “7”. Then, “1” is stored in the buffer (the result buffer becomes “0”), and the intermediate value “01”, which is the output value at timing “8”, is converted into the converted value “0”.

  Further, for example, in the bit converters C4 to C6, when the output value at the timing “12” is the intermediate value “10”, the stored value of the buffer is “−1” at the previous timing “11”. Then, “2” is stored in the buffer (the result buffer becomes “1”), and the intermediate value “10” which is the output value at the timing “12” is converted into the converted value “0”.

  Further, for example, in the bit converters C4 to C6, when the output value at the timing “14” is the intermediate value “10”, the stored value of the buffer is “1” at the previous timing “13”. Then, “1” is extracted from the buffer and added (as a result, the buffer becomes “0”), and the intermediate value “10”, which is the output value at timing “14”, is converted into the converted value “1”. In FIG. 10B, the bit converter process is conceptually described using a buffer that stores decimal numbers, but the actual buffer may be a buffer that stores binary numbers.

  In summary, the bit converters C4 to C6 have the timing “n−1” when the output value at the timing “n” (n is a natural number) is the intermediate value “10” or the intermediate value “01”. When the stored value of the buffer at 0 is less than or equal to 0, “1” is stored in the buffer and the intermediate value “01”, which is the output value at timing “n”, is converted to the converted value “0”, or “ 2 ”is stored in the buffer, and the intermediate value“ 10 ”, which is the output value at timing“ n ”, is converted into the converted value“ 0 ”. On the other hand, the bit converters C4 to C6 are provided when the output value at the timing “n” (n is a natural number) is the intermediate value “10” or the intermediate value “01”, and the buffer converter at the timing “n−1”. If the stored value is positive, “1” is extracted from the buffer and added to convert the intermediate value “10”, which is the output value at timing “n”, into the converted value “1”, or “2” from the buffer. Are extracted and added to convert the intermediate value “01”, which is the output value at timing “n”, into the converted value “1”.

  Although details will be described later, in the bit converters C4 to C6, the operation of adding the correction amount to the intermediate value “10” or the intermediate value “01” compares the digital output signals of the quantizer Q1 and the quantizer Q2. Input to the instrument and integrate other than the maximum value of the digital output signal. In the bit converters C4 to C6, the conversion value converted in this way becomes an output value of the PDM signal, and is also input to the subtractor together with the input signal as a feedback signal by the feedback loop of the output value. The noise generated by C4 to C6 is canceled, and noise shaping characteristics are given to the bit converters C4 to C6. Thereby, the bit converters C4 to C6 can output the PDM signal as an output signal as a highly accurate 1-bit signal.

(Quantizer vertical axis direction (resolution)-horizontal axis direction (time) conversion)
FIG. 11 is a diagram illustrating an example of conversion in the vertical axis direction (resolution) −horizontal axis direction (time) of the quantizer. As described above, when the output value at the time of quantization is an intermediate value that is neither the maximum value nor the minimum value, converting the intermediate value to either the maximum value or the minimum value is the resolution of the vertical axis ( This is equivalent to replacing the resolution of the quantizer) with the resolution (density amount) on the horizontal axis.

  By performing such conversion, as shown in FIG. 11, compared with the signal output from the 1-bit quantizer (see FIG. 11A), it is output from the multi-bit quantizer, In the signal (see FIG. 11B) in which the multi-bit vertical component is converted into the horizontal component, the number of times the same value is continuously output increases. Since the bit “0” is the switching element OFF and the bit “1” is the switching element ON command value, the number of times the same value is continuously output increases, so that the switching element ON and The number of times of switching off is reduced. In other words, the ΔΣ modulator that converts the output signal of the multi-bit ΔΣ modulator into a 1-bit PDM signal by the bit converter and outputs the converted signal is more than the PDM signal output by the general 1-bit ΔΣ modulator. There is an effect of reducing the number of times of switching.

  As described above, the ΔΣ modulator according to the disclosed technique performs the first PDM on the output of the multibit quantizer in the process of generating the output signal (PDM signal) from the input signal by the ΔΣ modulator. The structure obtained by double pulse density modulation (DPDM) in which PDM is further performed on the value obtained by removing the most significant bit of the result and the final result is output as a 1-bit PDM signal. Become.

[Embodiment]
Based on the basic technology and the disclosed technology described above, embodiments of the present application will be described below.

(Motor control device and bit converter according to embodiments)
FIG. 12 is a diagram illustrating an example of a motor control device according to the embodiment. The motor control device 100 according to the embodiment is different from the motor control device 100X according to the basic technique shown in FIG. 1 in that a PDM generator 22A is provided instead of the PWM generator 22. In other respects, the motor control device 100 according to the embodiment is the same as the motor control device 100X according to the basic technology.

Here, the subtractor 11, speed controller 12, excitation current controller 13, subtractor 14, subtractor 15, d-axis current controller 16, q-axis current controller 17, non-interacting controller 18, subtraction 19, adder 20, dq / 3φ converter 21, resistance R, 2 CT, 3φ current calculator 24, 3φ / dq converter 25, axis error calculation processing unit 26, PLL controller 29, position estimator 30 The 1 / Pn processor 31 and the switch SW are the command value generator 1. The PDM generator 22A is the signal generator 2. The IPM 23 is a driver 3. The d-axis voltage command value Vd ^* and the q-axis voltage command value Vq ^* may be used as voltage command values, and the dq / 3φ converter 21 may be added to the signal generator 2.

  The PDM generator 22A has the same ΔΣ modulator for each of the U phase, the V phase, and the W phase. This ΔΣ modulator is one of the first-order ΔΣ modulator M4, the second-order ΔΣ modulator M5, and the second-order ΔΣ modulator M6. The PDM generator 22A generates a U-phase upper arm signal Up, a V-phase upper arm signal Vp, and a W-phase upper arm signal Wp, which are 1-bit PDM signals, from the input signals for the U phase, V phase, and W phase. In accordance with the U-phase lower arm signal Un corresponding to the U-phase upper arm signal Up, the V-phase lower arm signal Vn corresponding to the V-phase upper arm signal Vp, and the W-phase upper arm signal Wp, which are also 1-bit PDM signals. W-phase lower arm signal Wn is generated. The PDM generator 22A generates the generated 6-phase PDM signals (U-phase upper arm signal Up, V-phase upper arm signal Vp, W-phase upper arm signal Wp, U-phase lower arm signal Un, V-phase lower arm signal Vn, W The lower arm signal Wn) is output to the IPM 23.

(Bit Converter According to Embodiment)
FIG. 13 is a diagram illustrating an example of the bit converter according to the embodiment. The PDM generator 22A has one of the above-described first-order ΔΣ modulator M4, second-order ΔΣ modulator M5, and second-order ΔΣ modulator M6 for each of the three phases U phase, V phase, and W phase, It has quantizers 22A-Q and bit converters 22A-C. In FIG. 13, the elements other than the quantizers 22A-Q and the bit converters 22A-C are not shown. The quantizer 22A-Q is one of the above-described quantizers Q1 to Q3-1, Q3-2, and the bit converter 22A-C corresponds to the quantizers Q1 to Q3-1, Q3-2. Any of the above-described bit converters C4 to C6.

  As shown in FIG. 13, the bit converters 22A-C are digital circuits that use the output of the multi-bit digital signal of the quantizers 22A-Q as an input signal. The bit converters 22A-C include a comparator 41, a multiplier 42, a subtractor 43, an integrator 44, a comparator 45, a multiplier 46, an adder 47, an inverter 48, and a multiplier 49.

  The comparator 41 compares the 2-bit input signal from the quantizers 22A-Q with the maximum value ("11" in the example of FIG. 10A) that can be taken by the input signal, and the two match. In this case, data “0” obtained by inverting data “1” is output, and data “1” obtained by inverting data “0” is output when they do not match. The multiplier 42 multiplies the input signal from the quantizer 22A-Q and the inverted output of the comparator 41, so that the input signal from the quantizer 22A-Q other than the maximum value is sent to the subtractor 43. Entered.

  The subtractor 43 subtracts the signal from the multiplier 49 from the input signal from the multiplier 42 and outputs the result to the integrator 44. The integrator 44 integrates the input signal from the subtractor 43 except for the maximum value among the input signals from the quantizers 22A-Q.

  The comparator 45 compares the input signal from the integrator 44 with the maximum value that the input signal can take (“11” in the example of FIG. 10A), and if the input signal is greater than or equal to the maximum value. Data “1” is output, and when the input signal is less than the maximum value, data “0” is output to determine whether or not overflow has occurred. The output when the overflow occurs is “1”, and the output when the overflow does not occur is “0”. In the embodiment, the overflow is a 2-bit overflow because the quantizer 22A-Q outputs 2-bit. Depending on the output of the comparator 45, the output signal of the bit converter 22A-C changes.

  The multiplier 46 multiplies the inverted output of the comparator 41 and the output (overflow signal) of the comparator 45, so that the output signal 22A-C changes according to the input signal. Further, the output of the comparator 45 is input to the multiplier 49 so that the integrator 44 is reset. The adder 47 adds the re-inverted output of the inverted output of the comparator 41 by the inverter 48 and the output of the multiplier 46, thereby converting the 2-bit input signal from the quantizer 22A-Q into 1 bit. To output signal.

  The multiplier 49 inputs the result of multiplying the output signal of the integrator 44 and the output signal of the comparator 45 to the subtractor 43 so that the integrator 44 is reset when the integrator 44 overflows. Control.

(Bit conversion processing according to the embodiment)
FIG. 14 is a flowchart illustrating an example of the bit conversion processing according to the embodiment. FIG. 14 shows a bit conversion process in the bit converters 22A-C executed by the control of the bit converters 22A-C by a control unit (not shown) included in the bit converters 22A-C shown in FIG. The process of converting the 2-bit output signal of the quantizer 22A-Q into a 1-bit signal is repeated every sampling period of the quantizer 22A-Q. The 2-bit output signal of the quantizer 22A-Q is any one of “00”, “01”, “10”, and “11”.

  As shown in FIG. 14, in the bit converters 22A-C, whether or not the input signal from the quantizers 22A-Q is the maximum value that the input signal can take (in this embodiment, “11”). Is determined (step S11). When the input signal from the quantizer 22A-Q is the maximum value (step S11: Yes), the bit converter 22A-C moves the process to step S12, and the input signal from the quantizer 22A-Q is the maximum. If it is not a value (step S11: No), the process proceeds to step S13. In step S12, the bit converters 22A-C output data “1”. This output becomes a PDM signal.

  On the other hand, in step S13, the bit converters 22A-C integrate other than the maximum value of the input signals from the quantizers 22A-Q. Next, the bit converters 22A-C determine whether or not the value integrated in step S13 has overflowed (step S14). If the value integrated in step S13 overflows (step S14: Yes), the bit converter 22A-C moves to step S12, and if the value integrated in step S13 does not overflow (step S14: No). Then, the process proceeds to step S15. In step S15, the bit converters 22A-C output data “0”. Bit converter 22A-C will complete | finish a bit conversion process, after step S12 or step S15 is complete | finished.

  According to an example of the bit conversion processing according to the above embodiment, when the 2-bit output signal of the quantizer 22A-Q is “11”, the digital signal has the maximum value, and thus the output data is “1”. Become. Further, when the 2-bit output signal of the quantizer 22A-Q is other than “11”, that is, when the value is not the maximum value of the digital signal, the value of the digital signal is integrated. When the integrated value is equal to or greater than the maximum value “11”, the output data is “1”. On the other hand, when the integrated value is not overflowed, the output data is “0”.

(Simulation result of output signal (quantizer output) with respect to input signal)
As an example of the above-described embodiment and a comparative example according to the prior art, a primary ΔΣ modulator is used (for example, the primary ΔΣ modulator M4 shown in FIG. 7 is used in the example, and the comparative example shown in FIG. A simulation was performed (using the next ΔΣ modulator M1). FIG. 15A is a diagram illustrating an example of a simulation result (in the case of an input amplitude of 130 V) of an output signal (quantizer output) with respect to an input signal when a first-order ΔΣ modulator according to the related art is used as a PDM generator. . FIG. 15B is a diagram illustrating an example of a simulation result (in the case of an input amplitude of 40 V) of an output signal (quantizer output) with respect to an input signal when a first-order ΔΣ modulator according to the related art is used as a PDM generator. .

  FIG. 16A is a diagram illustrating a simulation result (in the case of an input amplitude of 130 V) of an output signal (quantizer output) with respect to an input signal when the first-order ΔΣ modulator according to the embodiment is used as a PDM generator. . FIG. 16B is a diagram illustrating an example of a simulation result (in the case of an input amplitude of 40 V) of an output signal (quantizer output) with respect to an input signal when the first-order ΔΣ modulator according to the embodiment is used as a PDM generator. .

  15A, FIG. 15B, FIG. 16A, and FIG. 16B show the comparison values (intermediate potentials) of the simulation results as the reference for quantization by the 1-bit quantizer in the first-order ΔΣ modulator according to the prior art. Indicates the voltage value. The intermediate potential when the 2-bit quantizer is used in the primary ΔΣ modulator according to the embodiment is also set to the same condition as that of the 1-bit ΔΣ modulator according to the conventional technique. In the first-order ΔΣ modulator according to the embodiment, this intermediate potential corresponds to the reference value 2 shown in FIG. 10A. In order to set the output of the first-order ΔΣ modulator according to the embodiment to a 2-bit output, as shown in FIG. 10A, reference values 1 and 3 are provided as potentials above and below the reference value 2 (intermediate potential). Yes.

  In the comparison between FIG. 15A and FIG. 16A, the PDM generator to which the 1-bit ΔΣ modulator according to the prior art is applied and the PDM generator 22A to which the ΔΣ modulator according to the embodiment is applied are compared with each other. In the case of 22A, the period in which the same value of data “0” or data “1” is continuously output as an output signal is longer than that of the PDM generator to which the conventional 1-bit ΔΣ modulator is applied. The result was that the number of rises of the pulse in one cycle of the signal, that is, the number of switchings was small.

  15A and FIG. 16A, in one period of an input signal with an input amplitude of 130V, the PDM generator to which the 1-bit ΔΣ modulator according to the prior art is applied has an output PDM signal of 90 pulses. However, since the PDM generator 22A according to the embodiment showed the rise of 77 pulses, the embodiment can reduce the switching frequency of the IPM 23 and reduce the switching loss as compared with the prior art. I understand.

  Similarly, in the comparison between FIG. 15B and FIG. 16B, the PDM generator to which the 1-bit ΔΣ modulator according to the prior art is applied in one cycle of the input signal having an input amplitude of 40 V has an output PDM signal of 192. However, since the PDM generator 22A according to the embodiment showed the rise of 145 pulses, the embodiment reduces the number of times of switching of the IPM 23 and reduces the switching loss. It can be seen that it can be reduced.

  According to the above embodiment, the multi-bit PDM signal generated by the multi-bit quantizer is converted to 1 bit by the bit converter rather than the 1-bit PDM signal generated by using the conventional 1-bit ΔΣ modulator. The PDM signal thus reduced can reduce the number of times of switching and reduce the switching loss. Further, as shown in FIGS. 7, 8, and 9, the bit converter according to the present embodiment is arranged in the feedback loop of the ΔΣ modulator, and therefore generated by the bit converter due to the noise shaping characteristics of the ΔΣ modulator. Noise is canceled. As a result, the number of times of switching and switching loss can be reduced while maintaining the noise characteristics of the motor drive device using the conventional ΔΣ modulator.

(Modification of the embodiment)
In the above-described embodiment, the outputs of the quantizers Q1 to Q3-1 and Q3-2 of the PDM generator 22A are “2” bits, that is, the resolution of the vertical axis of the quantizers Q1 to Q3-1 and Q3-2. Is “2” bits, but is not limited to this, and may be “m” (m is a natural number of 3 or more) bits. The orders of the first-order ΔΣ modulator M4, the second-order ΔΣ modulator M5, and the second-order ΔΣ modulator M6 are the ΔΣ modulators of the integrators connected in series or the cascaded primary ΔΣ modulators. The number may be three or more and the order may be higher. By increasing the resolution (number of bits) of the quantizer and / or increasing the order of the ΔΣ modulator, the output signal of the ΔΣ modulator can be further improved in accuracy.

  In the above-described embodiment, it is assumed that the PDM generator 22A performs three-phase modulation in which a three-phase command voltage value is ΔΣ-modulated as an input signal and a three-phase PDM signal is output. However, the present invention is not limited to this, and two-phase modulation in which two-phase ΔΣ modulation is performed using two phases of three-phase command voltage values as input signals to output a two-phase PDM signal may be used. Alternatively, two-phase modulation may be performed in which a three-phase command voltage value is used as an input signal and a two-phase command voltage value of the input signal is ΔΣ modulated to output a two-phase PDM signal. In any case, the switching frequency can be further reduced and the switching loss can be reduced.

  The information including the above-described embodiment and the specific names, processes, controls, various data and parameters shown in the drawings is merely an example, and can be changed as appropriate unless otherwise specified. In addition, the configuration of each unit or each device in the above-described embodiment may be appropriately distributed or integrated from the processing load, mounting efficiency, and the like. In addition, each process in the above-described embodiment may be executed by appropriately changing the process order from the processing load, the mounting efficiency, and the like.

  The broader aspects of the embodiments described above are not limited to the specific details and representative embodiments described and described above. Accordingly, various modifications can be made without departing from the general inventive concept or scope defined by the appended claims and their equivalents.

M1, M4 primary ΔΣ modulator M2, M3, M5, M6 secondary ΔΣ modulator S1, S2-1, S2-2, S3-1, S3-2, S3-3 subtractors I1, I2-1, I2 -2, I3-1, I3-2 Integrators Q1, Q2, Q3-1, Q3-2 Quantizers D1, D2, D3-1, D3-2 Delay devices A1, A2, A3-1, A3-2 A3-3 Adder d3 Differentiator C4, C5, C6 Bit converter 100X, 100 Motor controller 1, 1X Command value generator 2, 2X Signal generator 3, 3X Driver 11 Subtractor 12 Speed controller 13 Excitation Current controller 14, 15 Subtractor 16 d-axis current controller 17 q-axis current controller 18 non-interacting controller 19 subtractor 20 adder 21 dq / 3φ converter 22 PWM generator 22A PDM generator 22A-Q quantum 22A-C Bit converter 23 IPM
23Up, 23Un, 23Vp, 23Vn, 23Wp, 23Wn Switching element 24 3φ current calculator 25 3φ / dq converter 26 Axis error calculation processor 29 PLL controller 30 Position estimator 31 1 / Pn processor 41 Comparator 42 Multiplier 43 Subtractor 44 Integrator 45 Comparator 46 Multiplier 47 Adder 48 Inverter 49 Multiplier SW Switch CO1 Contact CO2 Contact CO3 Contact R Resistance M Motor

Claims (3)

A driver for generating a driving voltage for driving the motor by switching of a switching element based on a switching signal; a command value generator for generating a voltage command value for driving the motor based on a speed command value; and the command value generator A motor control device comprising a signal generator for generating the switching signal from the voltage command value generated by
The signal generator is
A bit converter that converts an input multi-bit signal into a 1-bit signal and outputs the switching signal;
A subtractor that outputs a signal obtained by subtracting the switching signal output by the bit converter from the voltage command value generated by the command value generator;
An integrator for integrating the signal output by the subtractor;
A motor control device comprising: a ΔΣ modulator comprising: a quantizer that outputs a multi-bit signal obtained by quantizing an integration result of the integrator with multi-bits to the bit converter. The ΔΣ modulator is
The motor control device according to claim 1, wherein the plurality of integrators are second-order or higher-order ΔΣ modulators connected in series. The ΔΣ modulator is
The motor control device according to claim 1, wherein a plurality of primary ΔΣ modulators are secondary or higher ΔΣ modulators connected in cascade.

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