JPH0563544A - Binmos logic circuit - Google Patents

Abstract

PURPOSE:To decrease number of circuit components while the performance such as an operating speed and low power consumption is kept. CONSTITUTION:When input signals Si1-SiN are all at an H level, PMOS 12-1-12-N are all turned off and an NMOS 13 for extracting a base charge and output NMOS 16-1-16-N for extracting an output charge are all tuned on, the output TR 14 is turned off and an output signal So goes to an L level. Since the NMOS 16-2-16-N for extracting an output charge extract the base charge at the trailing of the output signal So, number of the base charge extract NMOS TRs 13 is minimized.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a bipolar transistor and an N-type MOS transistor (hereinafter referred to as NMO) in an output stage.
S)) and obtains the logic of a plurality of input signals.

[0002]

2. Description of the Related Art Conventionally, as a technique in such a field,
For example, some documents were described in the following documents.

Proceedings of the 1990 Autumn Meeting of the Institute of Electronics, Information and Communication Engineers SC-10-2, Seta et al., "0.5 μm BiNM
Performance Evaluation of OS Gate "P. 5-304 As described in the above-mentioned document, CMOS (complementary MOS transistor) capable of low power consumption operation is often used in various integrated circuits. However, this CMO
Since S has a slow operation speed, various BiCMOS logic circuits have been proposed in which a bipolar transistor having a high operation speed and a CMOS capable of low power consumption operation are combined.

This BiCMOS logic circuit has the advantages of a CMOS and a bipolar, and therefore has the advantage of operating at a higher speed than the CMOS logic circuit. However, as the semiconductor manufacturing process technology is miniaturized to, for example, 0.5 μm, if the power supply voltage is lowered (for example, 3.3 V) for reliability reasons, there is a problem that the advantage is lost. Has been done. Therefore, BiCMOS
BiNMOS logic circuits are drawing attention as an alternative to logic circuits. An example of the configuration is shown in FIG.

FIG. 2 shows the conventional Bi described in the above document.
It is a circuit diagram of a 2-input NAND gate having an NMOS configuration.

This 2-input NAND gate has an input signal S
It has input terminals 1-1 and 1-2 for inputting i1 and Si2. P-type MOS transistors (hereinafter referred to as PMOS) 2-2 and 2-1 are provided at the input terminals 1-1 and 1-2. The gates are connected to each other, and the gates of the NMOS 3-1 and 3-2 for extracting the base charges are also connected to each other.

The PMOSes 2-1 and 2-2 are connected in parallel between the power supply VCC and the base of the NPN type output transistor 4, and the collector of the output transistor 4 is connected to the power supply VCC.
The emitters are respectively connected to the output terminals 5 for the output signal So. The NMOSs 3-1 and 3-2 are connected in series between the base of the output transistor 4 and the ground VSS. The output NMOSs 6-1 and 6-2 for extracting the output charges, which have the gates commonly connected to the gates of the NMOSs 3-1 and 3-2, have output terminals 5 and ground VS.
It is connected in series with S.

Next, the operation will be described.

When either one of the input signals Si1 and Si2 input to the input terminals 1-1 and 1-2 is at "L" level, the PMOS 2-1 or 2-2 is turned on and the NMOS 3 is turned on.
Either one of -1 and 3-2 is turned off, and N
One of the MOSs 6-1 and 6-2 is turned off. Then, the output transistor 4 base is "H".
Then, the output transistor 4 is turned on and the output signal So output from the output terminal 5 becomes "H" level.

Next, when both the input signals Si1 and Si2 become "H" level, the PMOS 2-1 and 2-2 are turned off and the NMOS 3-1 and 3-2 are turned on, so that the output transistor 4 is turned off. Becomes In addition, NMOS 6-1,
Since 6-2 is turned on, the output signal So becomes "L" level.

In this 2-input NAND gate, the NMOS
Compared to a two-input NAND gate having a primitive BiNMOS configuration in which 3-1 and 3-2 are omitted, N for quickly extracting the charge of the base-collector capacitance of the output transistor 4
By using the MOS 3-1 and 3-2, the output signal S
The output transistor 4 is turned off quickly when o falls,
It improves power consumption and operating speed.

[0012]

However, in the conventional circuit, in order to pull out the base parasitic capacitance of the output transistor 4 when the output signal So becomes "L" level,
It is necessary to have the same number of NMOSs 3-1 and 6-2 as the output charge extraction NMOSs 6-1 and 6-2, which are gate-controlled by the input signals Si1 and Si2. Therefore, as the number of inputs of the input signals Si1 and Si2 increases, the output N
As the number of MOSs 6-1 and 6-2 increases, the number of base charge extracting NMOSs 3-1 and 3-2 also increases accordingly, which leads to an increase in the number of elements, resulting in reduction in operating speed and low power consumption. It was difficult to reduce the number of elements while maintaining such performance.

The present invention provides a BiNMOS logic circuit which solves the problem that it is difficult to reduce the number of circuit constituent elements while maintaining the performance such as operating speed and low power consumption, which is a problem of the prior art. Is provided.

[0014]

In order to solve the above problems, the present invention has a bipolar transistor and an NMO as an output stage.
In a BiNMOS logic circuit composed of S, an NPN type output transistor connected between a power supply and an output terminal and a series connection between the output terminal and a ground are gate-controlled by a plurality of input signals. A plurality of output NMOSs for extracting the output charge, and a plurality of PMOSs connected in parallel between the power supply and the base of the output transistor and gate-controlled by the one or more input signals.
And an NMOS for extracting the base charge.

Here, an NMOS for base charge extraction
Is a source of the output NMOS whose drain (or source) is connected to the base of the output transistor and whose source (or drain) is connected to the output terminal of the plurality of output NMOSs. Or a drain) and is gate-controlled by the input signal.

[0016]

According to the present invention, since the BiNMOS logic circuit is constructed as described above, when the output transistor is turned off and the output NMOS is turned on and the output signal falls, the base charge is extracted. For the output transistor and the output NMOS for extracting the output charge
Since the electric charge is extracted to the ground side, the fall time of the output signal is shortened.

As described above, the output NMOS has not only the output charge extraction function but also the base charge extraction function, so that the number of base charge extraction NMOSs can be significantly reduced as compared with the conventional one. As a result, the number of circuit constituent elements can be reduced. Therefore, the above problem can be solved.

[0018]

FIG. 1 is a BiNMO showing an embodiment of the present invention.
FIG. 6 is a circuit diagram of a multi-input NAND gate including an S logic circuit. This multi-input NAND gate has input terminals 11-1 to 11-N for inputting a plurality of input signals Si1 to SiN.
And the input terminals 11-1 to 11-N have PMO
The gates of S12-1 to 12-N are connected to each other, and the gate of the NMOS 13 for extracting the base charge is also connected. The PMOS 12-1 to 12-N have a power source V
It is connected in parallel between the CC and the gate of the NPN type output transistor 14, and the base of the output transistor 14 is connected.
The drain of the NMOS 13 is connected to the drain. The collector of the output transistor 14 is connected to the power supply VCC, and the emitter is connected to the output terminal 15 that outputs the output signal So.

Between the output terminal 15 and the ground VSS, a plurality of output NMOSs 16-1 to 16-2 for extracting output charges are provided.
16-N are connected in series and each output NMOS 16-
Gates 1 to 16-N have input terminals 11-1 to 11-N
Respectively connected to. Furthermore, output NMOS16
The -1 source and the NMOS 13 source are commonly connected.

Next, the operation will be described. Input terminal 11-1
To 11-N, when any of the input signals Si1 to SiN is at "L" level, the PMOS 12-1 to 1
Any of 2-N turns on, and output NMOS 16-1 to
Since any one of 16-N is turned off, the output transistor 14 is turned on and the output signal So output from the output terminal 15 becomes "H" level.

When all of the input signals Si1 to SiN are at "H" level, all of the PMOS 12-1 to 12-N are in the off state, and the NMOS 13 and the output NMOS 16-.
Since all of 1 to 16-N are turned on, the output transistor 14 is turned off and the output signal So becomes "L" level.

As described above, in the multi-input NAND gate of this embodiment, when the input signals Si1 to SiN are all at the "H" level, the NMOS 13 and the output NMOSs 16-1 to 16 are provided.
-N are all turned on, and the NMOS 13, 16-2
.About.16-N extracts the base charge of the output transistor 14 to the ground VSS side, so that the output transistor 14 is quickly turned off at the fall of the output signal So. As a result, power consumption can be reduced and operating speed can be improved.

Further, output NMOS 16-2 to 16-N
Is the output transistor 1 in addition to the output charge extraction function.
Since it also has a 4 base charge extraction function, the number of elements for base charge extraction of the output transistor 14 can be minimized compared to the conventional one, and the operation speed and low power consumption performance are the same as the conventional one. The performance of can be maintained.

The present invention is not limited to the above embodiment,
Various modifications are possible. Examples of such modifications include the following.

(A) A plurality of PMOSs 12-1 to 12-N
If the gate control is performed in common by one of the plurality of input signals Si1 to SiN, substantially the same operation and effect as in the above embodiment can be obtained.

(B) Input signals Si1 to SiN and output N
The number of MOSs 16-2 to 16-N can be set to an arbitrary number of 2 or more, and the number of PMOSs 12-1 to 12-N can be changed accordingly.

(C) In the above embodiment, an example of a multi-input NAND gate has been described. However, by changing the polarity of the MOS transistor of FIG. 1 or adding another element such as an inverter. It is also possible to configure a logic circuit other than the NAND gate.

[0028]

As described in detail above, according to the present invention, in a BiNMOS logic circuit, a base charge extracting element of an output transistor is provided in accordance with the number of inputs separately from an output NMOS for extracting an output charge. In addition to the output charge extraction function, the output NMOS is provided with the output transistor base charge extraction function without providing another NMOS. Therefore, it is possible to minimize the number of base charge extraction elements while maintaining the performance of operation speed and low power consumption, and thereby to significantly reduce the number of circuit constituent elements.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a multi-input NAND gate including a BiNMOS logic circuit according to an embodiment of the present invention.

FIG. 2 is a circuit diagram of a 2-input NAND gate including a conventional BiNMOS logic circuit.

[Explanation of symbols]

11-1 to 11-N input terminals 12-1 to 12-N PMOS 13 NMO for base charge extraction
S 14 NPN type output transistor 15 Output terminal 16-1 to 16-N Output charge extraction NM
OS

Claims (1)

[Claims] 1. A NP connected between a power supply and an output terminal
An N-type output transistor, a plurality of N-type output MOS transistors connected in series between the output terminal and the ground for gate extraction of a plurality of output charges for gate charge control, the power supply and the output transistor And a plurality of P-type MOS transistors gate-controlled by the one or more input signals, and a drain or a source connected to the output transistor base. And the source or drain is the output M
Output M connected to the output terminal in the OS transistor
Connected to the source or drain of the OS transistor,
A BiNMOS logic circuit, comprising: an N-type MOS transistor for gate charge extraction that is gate-controlled by the input signal.