JPH0562986A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To enable the base and the base lead-out electrode of a bipolar transistor to be fully connected together to lessen the bipolar transistor in base resistance. CONSTITUTION:An opposite conductivity type link base diffusion layer 1L which is lower in concentration than a base contact region and formed in a region that spreads over a base region and a base contact region is provided, an opposite conductivity type semiconductor film is deposited on a certain conductivity type semiconductor substrate 1, an insulating film 4 provided with an opening correspondent to a base forming region is formed thereon, the opposite conductivity type semiconductor film is etched using the insulating film 4 as a mask to form a base lead-out electrode 3, opposite conductivity type impurities are introduced into the opening for the formation of a P-type base region 1B, an insulating film is formed on the side face of the opening to serve as a side wall 5, opposite conductivity type ions are obliquely implanted into the opening to form a link base diffusion layer 1L, an emitter electrode 6 of certain conductivity type semiconductor film is formed on the substrate 1 covering the opening, and the substrate 1 is thermally treated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to connection between a base of a bipolar transistor and a base lead electrode.

In a bipolar transistor having a structure in which an emitter is formed by self-alignment with a base extraction electrode through a side wall made of an insulator, a connection between a base region and an impurity diffusion layer (base contact region) from the base extraction electrode is established. It was done by lateral diffusion under the sidewall.

The present invention can be used to complete this connection.

[0004]

2. Description of the Related Art FIGS. 3A and 3B are sectional views for explaining a conventional example of a bipolar transistor. FIG. 3 (A) is an overall view of the bipolar transistor, and FIG. 3 (B) is an enlarged view of the conventional base lead-out connection portion.

In the figure, 1 is an n-type silicon (n-Si) substrate, 1B is an (internal) base region, 1E is an emitter region, and 1BC.
Is a base contact region, 2 is an isolation insulating film which is a silicon dioxide (SiO ₂ ) film, 3 is a base extraction electrode which is a polysilicon film, 4 is a polysilicon etching mask which is a SiO ₂ film, 5
Is a sidewall made of SiO ₂ , 6 is an emitter electrode, which is a polysilicon film, 7 is a polysilicon etching mask, which is a SiO ₂ film, 8
Is a cover insulating film, a phosphosilicate glass (PSG) film, and 9 is an electrode wiring, which is an aluminum (Al) wiring.

The figure shows a bipolar transistor having a structure in which the emitter 1E is self-aligned with the base extraction electrode 3 and the side wall 5 made of an insulator is formed, and a base region 1B and a base contact region (from the base extraction electrode 3) are formed. The connection with the impurity diffusion layer) 1BC was made by lateral diffusion of impurities under the side wall 5.

Further, in the prior art, in order to secure the emitter-base breakdown voltage, the base region 1B is formed before the side wall 5 is formed, then the side wall 5 is formed laterally thicker, and the base region 1B and the base are formed immediately below the side wall. Had contact with contact area 1BC.

[0008]

According to the structure of the conventional example, the base resistance between the emitter junction and the base lead electrode 3 is determined by the concentration of the base region 1B.
Generally, it was set to a high value, which deteriorated the transistor characteristics.

Further, in recent years, with the progress of miniaturization of devices, the diffusion process and the heat treatment for activating impurities after ion implantation are lowered in temperature, diffusion is not extended laterally, and the base resistance is further increasing.

An object of the present invention is to reduce the base resistance by perfecting the connection between the base region and the base contact region.

[0011]

[Means for Solving the Problems] 1)
Base region of opposite conductivity type formed in one conductivity type substrate (1)
(1B), a one conductivity type emitter region (1E) formed in the opposite conductivity type base region, and a high concentration opposite conductivity type base contact region (1) formed in the substrate adjacent to the base region.
BC), an opposite conductivity type link base diffusion layer (1L) formed in the substrate in a region extending over the base region and the base contact region and having a lower concentration than the base contact region
Or 2) a semiconductor film of opposite conductivity type is deposited on a semiconductor substrate (1) of one conductivity type, and an insulating film (4) is formed on the substrate to form a base formation region. And forming a base extraction electrode (3) by etching the opposite conductivity type semiconductor film using the mask as a mask, and introducing the opposite conductivity type impurity into the substrate in the opening of the insulating film and the base extraction electrode to form a p-type A step of forming a base region (1B),
A step of forming a side wall (5) made of an insulating film on the side surface of the opening, and a step of obliquely implanting ions of opposite conductivity type into the substrate of the opening to form a link base diffusion layer (1L), This is achieved by a method of manufacturing a semiconductor device, which includes a step of forming an emitter electrode (6) made of a semiconductor film of one conductivity type on the substrate so as to cover the opening, and a step of heat-treating the substrate.

[0012]

According to the present invention, the link base diffusion layer is provided immediately below the side wall, which is the connecting portion between the base region and the base contact region, and the two are connected via this, whereby the connection is completed.

As a result, the base resistance can be reduced and the increase of the base resistance due to the reduction of the heat treatment temperature can be suppressed.

[0014]

1 (A) and 1 (B) are sectional views for explaining an embodiment of the present invention of a bipolar transistor.

FIG. 1 (A) is an overall view of a bipolar transistor, and FIG. 1 (B) is an enlarged view of a base lead-out connection portion of an embodiment. In the figure, 1 is an n-Si substrate, 1B is a p-type base region, 1E is a high-concentration n-type (n ⁺ -type) emitter region, 1BC is a high-concentration p-type (p ⁺ -type) base contact region, and 1L is a p-type. Link base diffusion layer, 2 is an isolation insulating film of SiO ₂ film, 3 is a base extraction electrode of polysilicon film, 4 is an etching mask of polysilicon, SiO ₂ film, 5 is a sidewall made of SiO ₂ , 6 is an emitter electrode Polysilicon film, 7 is an etching mask of polysilicon, SiO ₂ film, 8 is a cover insulating film, PSG film, 9
Is an electrode wiring and is an Al wiring.

The outline of the manufacturing process of this device is as follows. The n-Si substrate usually uses an epitaxial Si layer and has a resistivity of 0.5 Ωcm. Next, LOCOS (selective oxidation)
The SiO ₂ film 2 as an isolation insulating film in the element isolation region by
To form.

Then, a 3000 Å-thick polysilicon film is grown on the substrate by the vapor phase epitaxy (CVD) growth method, and boron ions (B ⁺ ) are energy 35 KeV and the dose is 3 × 10 ¹⁵ cm.
After implantation at ^-2 , a 2000Å-thick SiO ₂ film 4 patterned by a lithography process is formed thereon, and the polysilicon film is etched by using this as a mask to form a base extraction electrode 3.

Then, B ⁺ is injected into the substrate at the opening of the SiO ₂ film 4 and the base extraction electrode 3 to p-type base region.
Form 1B. An example of injection conditions is energy 25 KeV,
The dose is 3 × 10 ¹³ cm ^-2 .

Then, a side wall 5 is formed on the substrate by growing a 2500Å-thick CVD SiO ₂ film and anisotropically etching this film. Then, under the conditions of Fig. 2, B ⁺
Inject diagonally.

Then, a 2000 Å-thick polysilicon film is grown on the substrate, and a 2000 Å-thick SiO ₂ film 7 patterned by a lithography process is formed on the polysilicon film, and the polysilicon film is etched using this as a mask. Then, the emitter electrode 6 is formed.

The n ⁺ type emitter region 1E is formed in self-alignment with the side wall 5 by thermal diffusion from the heavily doped emitter electrode 6. By the heat treatment at this time, impurities are diffused from the polysilicon film 3 of the p ⁺ type base extraction electrode into the substrate to form the base contact region 1BC, and the impurities implanted in the base region are activated.

Next, the PSG film 8 as a cover insulating film is formed on the substrate.
Is grown, an Al wiring 9 is formed by opening on the electrode, and the process is completed. FIG. 2 is a cross-sectional view illustrating an example of forming the link base diffusion layer.

The link base diffusion layer 1L is formed by injecting B ⁺ into the substrate obliquely. Now, assuming that the width of the opening for forming the emitter is W and the height of the opening is d, the angle θ formed by the perpendicular line standing on the substrate and the ion beam is determined by the following equation.

Θ = tan ^-1 (W / d). B ⁺ An example of implantation conditions is an energy of 25 KeV and a dose of 1
× 10 ¹⁴ cm ^-2 .

[0025]

The connection between the base region and the base contact region is perfected and the base resistance is reduced.

As a result, it was possible to contribute to the speedup of the bipolar transistor.

[Brief description of drawings]

FIG. 1 is a sectional view illustrating an embodiment of the present invention of a bipolar transistor.

FIG. 2 is a cross-sectional view illustrating an example of forming a link base diffusion layer.

FIG. 3 is a sectional view illustrating a conventional example of a bipolar transistor.

[Explanation of symbols]

1 is a semiconductor substrate, which is an n-Si substrate 1B p-type base region 1E n ⁺ -type emitter region 1BC p ⁺ -type base contact region 1L p-type link base diffusion layer 2 isolation insulating film SiO ₂ film 3 base extraction electrode polysilicon film 4 SiO ₂ film with a polysilicon etching mask 5 Sidewall made of SiO ₂ 6 Polysilicon film with an emitter electrode 7 SiO ₂ film with a polysilicon etching mask 8 PSG film with a cover insulating film 9 Al wiring with an electrode wiring

Claims (2)

[Claims] 1. An opposite conductivity type base region (1B) formed in a one conductivity type substrate (1), a one conductivity type emitter region (1E) formed in the opposite conductivity type base region, and the base. A high-concentration opposite conductivity type base contact region (1BC) formed on the substrate adjacent to the region, and a region lower than the base contact region formed in the substrate in a region extending over the base region and the base contact region. A semiconductor device comprising: a link base diffusion layer (1L) of opposite conductivity type. 2. A semiconductor film of opposite conductivity type is deposited on a semiconductor substrate of one conductivity type (1), a base formation region is opened on the semiconductor film to form an insulation film (4), and the insulation film is used as a mask. A step of etching the opposite conductivity type semiconductor film to form a base lead electrode (3), and introducing a opposite conductivity type impurity into the substrate at the opening of the insulating film and the base lead electrode to form the p-type base region (1B). ), A step of forming a side wall (5) made of an insulating film on the side surface of the opening, and an ion of opposite conductivity type is obliquely injected into the substrate of the opening to form a link base diffusion layer (1L). ), A step of forming an emitter electrode (6) made of a one conductivity type semiconductor film on the substrate so as to cover the opening, and a step of heat treating the substrate. Device manufacturing method.