JPH0562982A - Manufacture of bump electrode - Google Patents

Manufacture of bump electrode

Info

Publication number
JPH0562982A
JPH0562982A JP3220818A JP22081891A JPH0562982A JP H0562982 A JPH0562982 A JP H0562982A JP 3220818 A JP3220818 A JP 3220818A JP 22081891 A JP22081891 A JP 22081891A JP H0562982 A JPH0562982 A JP H0562982A
Authority
JP
Japan
Prior art keywords
film
bump electrode
resin film
base film
etching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3220818A
Other languages
Japanese (ja)
Inventor
Yoshikiyo Usui
吉清 臼井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP3220818A priority Critical patent/JPH0562982A/en
Publication of JPH0562982A publication Critical patent/JPH0562982A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods

Abstract

PURPOSE:To enable the surface of a resin film to be cleaned after a bump electrode is built in an integrated circuit device where the resin film is made to serve as an outermost protective film. CONSTITUTION:A bump electrode metal 8 is made to grow through electroplating making a metal base film 6 in contact with a resin film 5 serve as a plating electrode, the metal base film is removed from the resin film 5 by etching, the resin film is slightly dry-etched not only to clean its surface but also to remove etching residue 6a of the base film left unremoved by etching carried out in a preceding process.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、通常の窒化シリコン等
の保護膜の他に最外殻用の保護膜としてポリイミド樹脂
等の樹脂膜が用いられる集積回路装置に外部接続用の突
起電極であるバンプ電極を組み込むための製造方法に関
する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a protruding electrode for external connection to an integrated circuit device in which a resin film such as a polyimide resin is used as a protective film for the outermost shell in addition to a normal protective film such as silicon nitride. A manufacturing method for incorporating a bump electrode.

【0002】[0002]

【従来の技術】周知のように、バンプ電極は集積回路装
置のチップから外部接続のために突設される金属の突起
電極であって、これが組み込まれたいわゆるフリップチ
ップはパッケージに収納することなくチップ状態のまま
で配線基板等に実装することにより集積回路装置自身の
コストを下げ、かつその実装に要するスペースや手間を
大幅に節約できる利点があるので、集積回路装置を多数
用いる電子装置,とくに量産品に広く採用されるに至っ
ている。
2. Description of the Related Art As is well known, a bump electrode is a metal projection electrode projecting from an integrated circuit device chip for external connection, and a so-called flip chip incorporating the bump electrode is not housed in a package. The cost of the integrated circuit device itself can be reduced by mounting the device in a chip state on a wiring board, and the space and labor required for the mounting can be significantly saved. It has been widely adopted in mass-produced products.

【0003】このようにチップ実装される集積回路装置
は、パッケージに一旦収納した上で実装する場合より使
用中に外気に直接曝されて特性が劣化する危険が高いの
で、チップの集積回路を作り込んだ方の表面に外気遮断
性に優れた窒化シリコン等の保護膜を厳重に施して、そ
の要所に開口した窓の個所にバンプ電極を実装相手方と
の接続に適する高さに突設する。この突設高さには最低
でも数十μmを要するので、バンプ電極用の金属を電解
めっき法により必要な個所にだけ選択的に成長させるの
が通例であるが、電解めっきにはめっき電極が必要なの
で保護膜の上に金属の薄い下地膜を被着し、これをめっ
き電極膜としてバンプ電極用金属を電解めっきした後に
下地膜中のバンプ電極の相互間部分をエッチングにより
除去するのがふつうである。以下、この要領を図2を参
照して簡単に説明する。
In such an integrated circuit device mounted on a chip, there is a higher risk that the characteristics are deteriorated by being directly exposed to the outside air during use, as compared with the case where the integrated circuit device is mounted in a package and then mounted. Strictly apply a protective film such as silicon nitride, which has an excellent ability to block the outside air, to the surface of the embedded side, and project bump electrodes at the windows that are opened at the relevant points at a height suitable for connection with the mounting partner. .. Since this protruding height requires at least several tens of μm, it is customary to selectively grow the metal for the bump electrode only at the required place by the electrolytic plating method. Since it is necessary, a thin metal base film is deposited on the protective film, and using this as a plating electrode film, the metal for bump electrodes is electrolytically plated, and then the portions between the bump electrodes in the base film are removed by etching. Is. Hereinafter, this procedure will be briefly described with reference to FIG.

【0004】図2は集積回路装置用ウエハ10のバンプ電
極20が組み込まれた部分の拡大断面を示す。ウエハ10の
半導体基板やその上のエピタキシャル層である半導体領
域1を覆う酸化シリコン等の絶縁膜2の上に集積回路と
接続されたアルミの配線膜3を配設し、それを覆う上述
の窒化シリコン等の保護膜4に明けた窓内で配線膜3と
接続されたバンプ電極20を突設する。このバンプ電極20
の金属8を電解めっきにより成長させるため、チタン等
の下側下地膜6と銅等の上側下地膜7からなるふつうは
2層構成の下地膜を全面被着し、上側下地膜7を保護膜
4の窓よりやや大きなサイズにパターンニングする。
FIG. 2 shows an enlarged cross section of a portion of the integrated circuit device wafer 10 in which the bump electrodes 20 are incorporated. An aluminum wiring film 3 connected to an integrated circuit is provided on an insulating film 2 such as silicon oxide which covers the semiconductor substrate of the wafer 10 and the semiconductor region 1 which is an epitaxial layer thereon, and the above-mentioned nitriding film which covers the wiring film 3 is formed. A bump electrode 20 connected to the wiring film 3 is projected in the window opened in the protective film 4 made of silicon or the like. This bump electrode 20
In order to grow the metal 8 of FIG. 3 by electrolytic plating, a lower layer 6 of titanium or the like and an upper layer 7 of copper or the like are usually entirely coated with a two-layered lower layer, and the upper layer 7 is protected by a protective film. Pattern a slightly larger size than the 4th window.

【0005】次に、図では細線で示したフォトレジスト
のマスク膜Mを付けて上側下地膜7のみを露出させる窓
を開口し、下側下地膜6をめっき電極膜としてマスク膜
Mの窓内の上側下地膜7の上に金属8を電解めっきによ
り所望の高さに成長させる。さらに、マスク膜Mをまず
除去した後に下側下地膜6の図で細線で示した部分を金
属8と上側下地膜7をマスクとする化学エッチング等で
除去することにより、金属8を相互間接続のない独立し
たバンプ電極20とする。なお、下側下地膜6のエッチン
グ後にその残渣6aが残りやすいが、超音波浴に浸漬する
等の手段により除去して保護膜4の表面を清浄化する。
Next, a window for exposing the upper base film 7 only is opened by attaching a photoresist mask film M shown by a thin line in the drawing, and the lower base film 6 is used as a plating electrode film in the window of the mask film M. A metal 8 is grown to a desired height on the upper base film 7 by electroplating. Further, the mask film M is first removed, and then the portion of the lower base film 6 indicated by a thin line in the drawing is removed by chemical etching or the like using the metal 8 and the upper base film 7 as a mask to connect the metal 8 to each other. There is no independent bump electrode 20. Although the residue 6a tends to remain after the etching of the lower base film 6, the surface of the protective film 4 is cleaned by removing the residue 6a by means such as immersion in an ultrasonic bath.

【0006】[0006]

【発明が解決しようとする課題】以上説明した従来方法
によりバンプ電極を組み込んだ集積回路装置は実装後の
長期の使用期間に亘って安定な特性を維持できるのがふ
つうであるが、実装時や使用中の条件によっては上述の
窒化シリコンの保護膜のほか最外殻の保護膜用に樹脂膜
を被覆して外気に対する遮断性を強化する必要がある。
ところが、樹脂膜は窒化シリコン膜とは性状がかなり異
なるので、上述の従来方法ではその表面の清浄化が不充
分になりやすい問題がある。
It is usual that the integrated circuit device incorporating the bump electrode by the above-described conventional method can maintain stable characteristics over a long use period after mounting. Depending on the conditions during use, it is necessary to coat the resin film for the protective film of the outermost shell in addition to the above-mentioned protective film of silicon nitride to enhance the barrier property against the outside air.
However, since the properties of the resin film are considerably different from those of the silicon nitride film, the conventional method described above has a problem that the cleaning of the surface thereof tends to be insufficient.

【0007】すなわち、保護膜としての窒化シリコン膜
は組織が緻密で透気性が非常に低い特長があるが硬くて
やや脆い欠点があるため、フリップチップの実装時に掛
かる圧力や温度ないしは使用中に掛かる熱サイクルによ
り微細なクラック等の欠陥が発生して外気遮断性が低下
するおそれがある。一方、ポリイミド樹脂等を用いる樹
脂膜は実装時や使用中の温度,圧力条件下でずっと強靱
で、窒化シリコン膜と組み合わせれば外気遮断性を低下
させる欠陥の発生防止上非常に有利であるが、バンプ電
極の突設後にめっき電極用下地膜をエッチングで除去す
る際に微小残渣の除去や表面の清浄化が不完全になりや
すく、このため集積回路装置の漏洩電流が増加したり耐
圧が低下したりする問題が発生する。
That is, a silicon nitride film as a protective film has features that it has a dense structure and very low air permeability, but it has the drawback of being hard and slightly brittle, so that the pressure and temperature applied during flip-chip mounting or during use will be applied. There is a possibility that defects such as minute cracks may occur due to the heat cycle and the external air barrier property may be deteriorated. On the other hand, a resin film using a polyimide resin or the like is much more tough under the temperature and pressure conditions during mounting and in use, and when combined with a silicon nitride film, it is very advantageous in preventing the occurrence of defects that lower the outside air barrier property. , When removing the plating electrode base film by etching after the bump electrode is protruded, removal of minute residues and surface cleaning are likely to be incomplete, which increases the leakage current of the integrated circuit device and lowers the withstand voltage. Or problems occur.

【0008】本発明の目的はかかる問題点を解決して、
最外殻保護膜として樹脂膜を用いる集積回路装置にバン
プ電極を組み込んだ後の樹脂膜表面を高清浄化できるバ
ンプ電極の製造方法を提供することにある。
The object of the present invention is to solve the above problems,
It is an object of the present invention to provide a bump electrode manufacturing method capable of highly cleaning the surface of a resin film after incorporating the bump electrode into an integrated circuit device using a resin film as the outermost shell protective film.

【0009】[0009]

【課題を解決するための手段】この目的は本発明によれ
ば、樹脂膜に接する金属の下地膜をめっき電極として電
解めっきによりバンプ電極の金属を成長させる工程と、
下地膜をバンプ電極の金属をエッチングマスクとするエ
ッチングにより樹脂膜上から除去する工程と、酸素を含
むプラズマふん囲気内で樹脂膜の表面をドライエッチン
グする工程とを経由してバンプ電極を集積回路装置に組
み込むことにより達成される。
According to the present invention, there is provided a step of growing a metal of a bump electrode by electrolytic plating using a metal underlayer in contact with a resin film as a plating electrode.
The bump electrode is integrated circuit through a step of removing the base film from the resin film by etching using the metal of the bump electrode as an etching mask, and a step of dry etching the surface of the resin film in a plasma atmosphere containing oxygen. This is achieved by incorporating it in the device.

【0010】なお、集積回路装置が 300℃以上の温度下
で実装される場合は、樹脂膜としてポリイミド樹脂膜を
用いるのがよく、それに対するドライエッチングは純酸
素のプラズマふん囲気内で施すのが好適である。また、
めっき電極用の下地膜の除去はドライエッチング法によ
っても可能であるが、この下地膜にチタン膜を用いる場
合は希ふっ酸液やアンモニウム系のエッチング液を用い
るウエットエッチングによりこれを樹脂膜上から除去す
るのが最も簡単でかつ処理時間を短縮する上で有利であ
る。
When the integrated circuit device is mounted at a temperature of 300 ° C. or higher, it is preferable to use a polyimide resin film as the resin film, and dry etching for it is performed in a pure oxygen plasma atmosphere. It is suitable. Also,
The base film for the plating electrode can be removed by dry etching, but if a titanium film is used for this base film, it can be removed from the resin film by wet etching using a dilute hydrofluoric acid solution or an ammonium-based etching solution. It is the easiest to remove and is advantageous in reducing the processing time.

【0011】[0011]

【作用】上述のように従来はめっき電極用下地膜の除去
と集積回路装置の表面の清浄化とを同じ化学エッチング
により行なっていたが、本発明はエッチングによりまず
下地膜をほぼ除去した後にその下側の樹脂膜に浅くドラ
イエッチングを施すことにより、樹脂膜の表面を清浄化
すると同時に前のエッチングで取り切れなかった下地膜
の微小な残渣をも除去して、集積回路装置の表面を従来
の化学エッチングによるより高清浄化することに成功し
たものである。
As described above, conventionally, the removal of the underlayer film for the plating electrode and the cleaning of the surface of the integrated circuit device were carried out by the same chemical etching. By performing shallow dry etching on the lower resin film, the surface of the resin film can be cleaned at the same time by removing the minute residues of the underlying film that could not be removed by the previous etching. It has succeeded in achieving higher cleanliness by chemical etching.

【0012】従って、本発明方法ではめっき電極用下地
膜をエッチングにより従来のようにほぼ完全に除去しな
くても、次のドライエッチングにより下地膜の残渣をふ
つう数分以下の短時間内に容易に除去することができ、
下地膜のバンプ電極の付け根の下側部分へのいわゆるサ
イドエッチングの発生をなくしてそれによる付け根部の
強度低下を防止することができる。
Therefore, according to the method of the present invention, the residue of the base film can be easily removed by the next dry etching within a short time of usually several minutes or less, even if the base film for the plating electrode is not almost completely removed by etching as in the conventional case. Can be removed to
It is possible to prevent the so-called side etching from occurring in the lower portion of the base of the bump electrode of the base film, and prevent the strength of the base from lowering as a result.

【0013】[0013]

【実施例】以下、図を参照しながら本発明の実施例を説
明する。図1は同図(a) 〜(d) に本発明による集積回路
装置用バンプ電極の製造方法における主な工程を集積回
路装置のウエハ10の図2にほぼ対応する部分の拡大断面
で示すもので、図2と同じ部分には同じ符号が付けられ
ているので以下の説明中の前と重複する部分は適宜省略
することとする。
Embodiments of the present invention will be described below with reference to the drawings. 1 (a) to 1 (d) are enlarged sectional views showing the main steps in the method of manufacturing a bump electrode for an integrated circuit device according to the present invention in a portion substantially corresponding to FIG. 2 of a wafer 10 of the integrated circuit device. Since the same parts as those in FIG. 2 are designated by the same reference numerals, the parts overlapping with those in the following description will be appropriately omitted.

【0014】図1(a) はバンプ電極を突設する前のウエ
ハ10の状態を示す。半導体領域1の表面を覆う絶縁膜2
の上にアルミ等の配線膜3を配設した後、窒化シリコン
等の保護膜4をCVD法等により1〜1.5 μmの膜厚で
成膜してその配線膜3の端部の上側部分に窓をプラズマ
エッチング法等により開口するのは図2と同じである
が、その上にポリイミド樹脂等を例えばスピンコートし
て焼き付けることにより樹脂膜5を 1.5〜2μm程度の
膜厚で成膜しかつ同様に窓を開口して配線膜3を露出さ
せる。もちろん、両膜4と5とを順次成膜した上でそれ
らに対して同時に窓を開口してもよい。
FIG. 1 (a) shows the state of the wafer 10 before the bump electrodes are projected. Insulating film 2 covering the surface of the semiconductor region 1
After arranging the wiring film 3 made of aluminum or the like on the above, a protective film 4 made of silicon nitride or the like is formed to a film thickness of 1 to 1.5 μm by the CVD method or the like, and is formed on the upper portion of the end of the wiring film 3. Although the window is opened by the plasma etching method or the like as in FIG. 2, a resin film 5 having a film thickness of about 1.5 to 2 μm is formed by, for example, spin coating and baking polyimide resin or the like on the window. Similarly, a window is opened to expose the wiring film 3. Of course, both films 4 and 5 may be sequentially formed, and then windows may be simultaneously opened for them.

【0015】この窓の開口部にバンプ電極を電解めっき
により突設するため、図2と同様に下側下地膜6と上側
下地膜7をこの実施例でも2層構成の下地膜として被着
し、上側下地膜7の方を窓の開口よりやや大なバンプ電
極用サイズにパターンニングする。例えば、下側下地膜
6は 0.2μm程度の膜厚のチタン膜, 上側下地膜7は0.
5μm程度の膜厚の銅膜とされる。なお、チタンやクロ
ームの下側下地膜6はめっき電極としての役目のほか、
配線膜3のアルミとバンプ電極用金属との相互拡散を防
止するバリア膜としての役目を兼ね、上側下地膜7はこ
の下側下地膜6をバンプ電極用金属と低抵抗で接続する
役目を果たし、場合により下側下地膜6と上側下地膜7
の双方がめっき電極として利用される。
Since the bump electrode is projected in the opening of this window by electrolytic plating, the lower base film 6 and the upper base film 7 are applied as a base film having a two-layer structure also in this embodiment as in FIG. The upper base film 7 is patterned to a size for the bump electrode which is slightly larger than the window opening. For example, the lower base film 6 is a titanium film having a thickness of about 0.2 μm, and the upper base film 7 is 0.1 μm.
The copper film is about 5 μm thick. The lower base film 6 of titanium or chrome functions as a plating electrode,
The upper base film 7 also functions as a barrier film for preventing mutual diffusion between the aluminum of the wiring film 3 and the bump electrode metal, and the upper base film 7 connects the lower base film 6 to the bump electrode metal with low resistance. , Lower base film 6 and upper base film 7 in some cases
Both are used as plating electrodes.

【0016】図1(b) はバンプ電極用金属8の電解めっ
き工程を示す。まず、電解めっき用のマスク膜Mとして
フォトレジストをウエハ10の全面にスピンコートし、フ
ォトプロセスにより上側下地膜7のみを露出させる窓を
数十〜百μm角ないしは径のサイズに開口する。電解め
っきに際しては、通例のようにめっき治具にウエハ10を
セットしてめっき電極用の下側下地膜6を図示しない個
所でめっき電源に接続した状態で、バンプ電極用金属8
として例えば金を図のようにマスク膜Mの窓内の上側下
地膜7上にふつう数十〜百μmの所望の高さに成長させ
る。もちろん、金属8はウエハ10の面内のバンプ電極を
設けるべき個所に一斉に成長され、この電解めっきの終
了後にマスク膜Mが剥離液を用いて除去される。
FIG. 1 (b) shows an electrolytic plating process of the bump electrode metal 8. First, a photoresist as a mask film M for electrolytic plating is spin-coated on the entire surface of the wafer 10, and a window exposing only the upper base film 7 is opened in a size of several tens to hundreds of μm square or a diameter by a photo process. At the time of electrolytic plating, the wafer 10 is set on a plating jig as usual, and the lower base film 6 for the plating electrode is connected to a plating power source at a location not shown, and the metal 8 for bump electrode is formed.
As an example, gold is grown on the upper base film 7 in the window of the mask film M to a desired height of several tens to 100 μm as shown in the figure. Of course, the metal 8 is simultaneously grown on the surface of the wafer 10 where the bump electrodes are to be provided, and the mask film M is removed using a stripping solution after completion of this electrolytic plating.

【0017】図1(c) は下地膜, この実施例では下側下
地膜6の除去工程を示す。この工程では、下側下地膜6
がチタンの場合ふっ酸を50〜100 倍に希釈したエッチン
グ液にウエハ10を30〜60秒程度の短時間内浸漬すること
により、バンプ電極用金属8と上側下地膜7をマスクと
する化学エッチングにより下側下地膜6を除去する。樹
脂膜5に接する下側下地膜6を除去する場合は従来より
もその残渣6aが図示のように残りやすいが、本発明方法
では次の図1(d) の工程で容易に除去できる。なお、上
側下地膜7もめっき電極として利用する場合は、例えば
その銅を過硫酸アンモニウム等のエッチング液により除
去した後に下側下地膜6を除去することでよい。また、
この図1(c) の工程での下地膜の除去は化学エッチング
に限らずドライエッチングによっても同様にバンプ電極
用金属8等をマスクとして行なうことができる。
FIG. 1C shows a step of removing the base film, in this embodiment the lower base film 6. In this step, the lower base film 6
When titanium is used, the wafer 10 is immersed in an etching solution diluted with hydrofluoric acid 50 to 100 times for a short time of about 30 to 60 seconds to perform chemical etching using the bump electrode metal 8 and the upper base film 7 as a mask. The lower base film 6 is removed by. When the lower base film 6 in contact with the resin film 5 is removed, the residue 6a tends to remain as shown in the figure than in the conventional case, but the method of the present invention can easily remove the residue 6a in the next step of FIG. 1 (d). When the upper base film 7 is also used as the plating electrode, the lower base film 6 may be removed after removing the copper with an etching solution such as ammonium persulfate. Also,
The removal of the base film in the step of FIG. 1C can be performed not only by chemical etching but also by dry etching using the bump electrode metal 8 or the like as a mask.

【0018】図1(d) は本発明方法に特有な樹脂膜に対
するドライエッチング工程を示す。有機物である樹脂の
ドライエッチングには酸素を含むガス,この実施例のよ
うにポリイミド樹脂の場合は純粋な酸素をエッチングガ
スとするプラズマふん囲気内で施すのがよく、例えば 3
00〜500Wのプラズマ発生用高周波電力で2〜5分程度の
短時間処理により樹脂膜5の表面に浅くドライエッチン
グを施す。これにより樹脂膜5の下側下地膜6に接して
いた表面が清浄化され、かつ図1(b) の残渣6aが除去さ
れないし表面から遊離して容易に除去可能な状態にな
る。これでバンプ電極20の組み込みが完了するので、以
後はウエハ10をスクライブしてチップ実装用のフリップ
チップに単離することでよい。
FIG. 1D shows a dry etching process for the resin film, which is peculiar to the method of the present invention. Dry etching of a resin which is an organic substance is preferably carried out in a plasma atmosphere in which a gas containing oxygen is used, and in the case of a polyimide resin as in this embodiment, pure oxygen is used as an etching gas.
The surface of the resin film 5 is shallowly dry-etched by a short-time treatment of about 2 to 5 minutes with high-frequency power for plasma generation of 00 to 500 W. As a result, the surface in contact with the lower base film 6 of the resin film 5 is cleaned, and the residue 6a of FIG. 1 (b) is not removed or becomes free from the surface and can be easily removed. This completes the assembly of the bump electrode 20, and thereafter, the wafer 10 may be scribed and isolated into a flip chip for chip mounting.

【0019】なお、下地膜の残渣6aの除去に関しては、
上述のドライエッチング工程によるのが従来の超音波浴
への浸漬法より完全で、事後のブラッシングの手間を省
けるので簡単であり、かつ樹脂膜5の表面の無用な汚染
を避け得る点で有利である。もちろん、ドライエッチン
グの最大の利点は樹脂膜5の表面の目に見えない汚染を
除去して清浄化できる点にあるので、この工程後は表面
に清浄な窒素ガス等を吹き付けて樹脂の灰分等を飛散さ
せるだけにするのがよい。
Regarding the removal of the residue 6a of the base film,
The dry etching process described above is more complete than the conventional immersion method in an ultrasonic bath, is easy because it does not require post-brushing, and is advantageous in that unnecessary contamination of the surface of the resin film 5 can be avoided. is there. Of course, the greatest advantage of dry etching is that invisible contamination on the surface of the resin film 5 can be removed and the surface can be cleaned. Therefore, after this step, clean nitrogen gas or the like is sprayed onto the surface to remove the ash content of the resin. It is better to just scatter.

【0020】以上説明した本発明方法によりバンプ電極
を組み込んだフリップチップでは、漏洩電流は通常の数
mm角のチップの1個あたり数十pAで、従来の数十〜百数
十nAと比べて約3桁改善され、従来のような下地膜の残
渣によるチップ耐圧の低下はほぼ皆無になる。また、従
来の窒化シリコン等の保護膜4を樹脂膜5により補強す
ることにより、フリップチップの実装時にバンプ電極あ
たり数十〜百g程度の圧力や 400〜500 ℃の高温が掛か
った場合にも保護膜等の内部微細欠陥の発生を有効に防
止して、実装後の長期の使用期間中に外気に対する高い
遮断性を安定に維持することができる。
In the flip chip in which bump electrodes are incorporated by the method of the present invention described above, the leakage current is a normal number.
It is several tens of pA per mm square chip, which is improved by about three orders of magnitude as compared with the conventional tens to hundreds of tens nA, and there is almost no decrease in the chip breakdown voltage due to the residue of the underlying film. In addition, by reinforcing the conventional protective film 4 such as silicon nitride with the resin film 5, even when a pressure of several tens to 100 g per bump electrode or a high temperature of 400 to 500 ° C. is applied to each bump electrode during flip chip mounting. It is possible to effectively prevent the generation of internal fine defects such as a protective film, and stably maintain a high barrier property against external air during a long use period after mounting.

【0021】[0021]

【発明の効果】以上説明したとおり本発明方法では、最
外殻保護膜として樹脂膜を用いる集積回路装置に対し
て、樹脂膜に接する金属の下地膜をめっき電極とする電
解めっきによりバンプ電極用金属を成長させる工程と、
下地膜をエッチングにより樹脂膜の上からほぼ除去する
工程と、酸素を含むプラズマふん囲気内で樹脂膜の表面
をドライエッチングする工程とを経由してバンプ電極を
組み込むことにより、次の効果を得ることができる。
As described above, according to the method of the present invention, for an integrated circuit device using a resin film as the outermost shell protective film, bump electrodes are formed by electrolytic plating using a metal base film in contact with the resin film as a plating electrode. A step of growing a metal,
By incorporating the bump electrode through the step of substantially removing the base film from above the resin film by etching and the step of dry etching the surface of the resin film in a plasma atmosphere containing oxygen, the following effects can be obtained. be able to.

【0022】(a) 下地膜を除去した後の樹脂膜の表面に
ドライエッチングを施して、樹脂膜の表面を清浄化する
と同時に下地膜の微小な残渣をも除去することにより、
集積回路装置の漏洩電流を従来と比べて約3桁減少さ
せ、下地膜の残渣によるチップ耐圧の低下をほぼ皆無に
することができる。 (b) 絶縁膜上の下地膜の残渣をドライエッチングにより
数分以下の短時間内に従来の超音波浴への浸漬法より完
全に除去することができ、従来のブラッシング等の余分
な手間を省き、かつ樹脂膜の表面の無用な汚染を防止で
きる。 (c) 従来のように下地膜を化学エッチングによりほぼ完
全に取り切らなくてもその残渣をドライエッチング工程
で容易に除去できるので、化学エッチング時間を短縮し
て下地膜のバンプ電極の付け根の下側部分へのサイドエ
ッチングの発生をなくし、付け根部の強度低下を防止す
ることができる。
(A) By performing dry etching on the surface of the resin film after removing the base film to clean the surface of the resin film and also to remove minute residues of the base film,
The leakage current of the integrated circuit device can be reduced by about three orders of magnitude as compared with the conventional one, and the reduction of the chip breakdown voltage due to the residue of the underlying film can be almost eliminated. (b) The residue of the underlying film on the insulating film can be completely removed by dry etching in a short time of a few minutes or less compared with the conventional immersion method in an ultrasonic bath, and the extra labor such as conventional brushing is required. It is possible to omit and prevent unnecessary contamination of the surface of the resin film. (c) Since the residue can be easily removed by the dry etching process even if the underlying film is not completely removed by chemical etching as in the conventional case, the chemical etching time can be shortened and the residue under the base of the bump electrode of the underlying film can be reduced. It is possible to prevent side etching from occurring in the side portion and prevent the strength of the root portion from being reduced.

【0023】さらに、本発明方法が対象とする集積回路
装置では窒化シリコン等の保護膜が樹脂膜により補強さ
れるので、実装時にかなりの圧力や高温が掛かった場合
にも保護膜等に微細な欠陥が発生するおそれが少なく、
実装後の使用期間を通じ高い外気遮断性を長期に亘って
安定に維持することができる。
Further, in the integrated circuit device to which the method of the present invention is applied, since the protective film such as silicon nitride is reinforced by the resin film, even if a considerable pressure or a high temperature is applied during mounting, the protective film and the like are finely divided. Less likely to cause defects,
It is possible to stably maintain a high outside air blocking property for a long period of time throughout the usage period after mounting.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明によるバンプ電極の製造方法の実施例を
同図(a) 〜(d) にそれぞれその主な工程ごとの状態で示
す集積回路装置用ウエハのバンプ電極が設けられる部分
の拡大断面図である。
FIG. 1 is an enlarged view of a portion of a wafer for an integrated circuit device where a bump electrode is provided, showing an embodiment of a method for manufacturing a bump electrode according to the present invention in each of the main steps in FIGS. 1 (a) to 1 (d). FIG.

【図2】従来技術によるバンプ電極が組み込まれた集積
回路装置用ウエハの一部の拡大断面図である。
FIG. 2 is an enlarged cross-sectional view of a part of a wafer for integrated circuit device in which bump electrodes according to the related art are incorporated.

【符号の説明】[Explanation of symbols]

4 窒化シリコン等の保護膜 5 集積回路装置の最外殻保護膜としての樹脂膜 6 めっき電極用の下地膜ないしは下側下地膜 7 上側下地膜 8 バンプ電極用金属 10 集積回路装置用ウエハ 20 バンプ電極 4 Protective film such as silicon nitride 5 Resin film as outermost shell protective film of integrated circuit device 6 Base film or lower base film for plating electrode 7 Upper base film 8 Metal for bump electrode 10 Wafer for integrated circuit device 20 Bump electrode

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】最外殻保護膜として樹脂膜を用いる集積回
路装置にバンプ電極を組み込む方法であって、樹脂膜に
接する金属の下地膜をめっき電極として電解めっきによ
りバンプ電極の金属を成長させる工程と、下地膜をバン
プ電極の金属をエッチングマスクとするエッチングによ
り樹脂膜上から除去する工程と、酸素を含むプラズマふ
ん囲気内で樹脂膜の表面をドライエッチングする工程と
を含むことを特徴とするバンプ電極の製造方法。
1. A method of incorporating a bump electrode into an integrated circuit device using a resin film as an outermost shell protective film, wherein a metal of a bump electrode is grown by electrolytic plating using a metal base film in contact with the resin film as a plating electrode. And a step of removing the base film from the resin film by etching using the metal of the bump electrode as an etching mask, and a step of dry etching the surface of the resin film in a plasma atmosphere containing oxygen. Method of manufacturing bump electrode.
【請求項2】請求項1に記載の方法において、樹脂膜と
してポリイミド樹脂膜が用いられ、その表面に対するド
ライエッチングが純酸素のプラズマふん囲気内でなされ
ることを特徴とするバンプ電極の製造方法。
2. The method for manufacturing a bump electrode according to claim 1, wherein a polyimide resin film is used as the resin film, and the dry etching of the surface is performed in a plasma atmosphere of pure oxygen. ..
【請求項3】請求項1に記載の方法において、めっき電
極として用いられる下地膜がチタン膜であり、その樹脂
膜上からの除去がウエットエッチングによりなされるこ
とを特徴とするバンプ電極の製造方法。
3. The method for manufacturing a bump electrode according to claim 1, wherein the base film used as the plating electrode is a titanium film, and the removal from the resin film is performed by wet etching. ..
JP3220818A 1991-09-02 1991-09-02 Manufacture of bump electrode Pending JPH0562982A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3220818A JPH0562982A (en) 1991-09-02 1991-09-02 Manufacture of bump electrode

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3220818A JPH0562982A (en) 1991-09-02 1991-09-02 Manufacture of bump electrode

Publications (1)

Publication Number Publication Date
JPH0562982A true JPH0562982A (en) 1993-03-12

Family

ID=16757040

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3220818A Pending JPH0562982A (en) 1991-09-02 1991-09-02 Manufacture of bump electrode

Country Status (1)

Country Link
JP (1) JPH0562982A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009503852A (en) * 2005-07-29 2009-01-29 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド Efficient patterning of under bump metal layer using dry etch process

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009503852A (en) * 2005-07-29 2009-01-29 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド Efficient patterning of under bump metal layer using dry etch process
TWI397957B (en) * 2005-07-29 2013-06-01 Globalfoundries Us Inc Technique for efficiently patterning an underbump metallization layer using a dry etch process

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