JPH0562875U - Waveform output device for IC tester - Google Patents

Abstract

(57) [Summary] [Purpose] One timing generator is omitted for each test system. Structure: Gates 16 to 22 are controlled to be opened and closed according to a designated waveform mode and pattern data, and flip-flops 24 are set and reset by timing clocks T1 to T3 from timing generators 11 to 13 for waveform generation. Then, the target waveform pattern data is obtained at the output thereof and is supplied to the driver 26. T1
T1 having the most advanced phase in T3 is supplied to the set terminal of the flip-flop 31 through the gate 28, and T1 to T1
Timing clock T5 whose phase is later than all three
Is supplied to the reset terminal of the flip-flop 31 through the gate 29. The output of the flip-flop 31 controls the driver 26 to be enabled or disabled. The setting of the flip-flop 31 is delayed by the delay element 41 after the driver 26 has set up with respect to the waveform change based on T1.

Description

[Detailed description of the device]

[0001]

[Industrial applications]

 This invention selectively distributes and supplies three timing clocks to the set terminal and the reset terminal of the first set-reset flip-flop according to the specified waveform mode and pattern data, and outputs the output of the first flip-flop. The present invention relates to a waveform output device for an IC tester, which outputs through a driver and controls the driver to an enable state or a disable state by an output of a second set reset flip-flop.

[0002]

[Prior Art]

 FIG. 3 shows a conventional waveform output device. Timing clocks T1 to T5 are output from the timing generators 11 to 15, respectively. The timing clock T1 from the timing generator 11 is applied to the gates 16 and 17, the timing clock T2 from the timing generator 12 is applied to the gates 18 and 19, and the timing clock T3 from the timing generator 13 is applied to the gates 21 and 22, respectively. Is entered. The respective outputs of the gates 16, 18, 21 are supplied to the set terminal S of the first set / reset flip-flop 24 through the OR circuit 23, and the respective outputs of the gates 17, 19, 22 are passed through the OR circuit 25 to the first flip-flop 24. Is supplied to the reset terminal R.

The output of the first flip-flop 24 is supplied to one pin terminal of the IC device under test 27 through the driver 26. The timing clocks T4 and T5 from the timing generators 14 and 15 are supplied to the gates 28 and 29, respectively, and the outputs of the gates 28 and 29 are supplied to the set terminal S 1 and the reset terminal R of the second set reset flip-flop 31, respectively. To be done. The output of the second flip-flop 31 controls the driver 26 to be in an enabled state or a disabled state. Control signals are supplied from the terminals 31, 32, 33, 34, 35, 36, 37 and 38 as the other inputs of the gates 16, 17, 18, 19, 21, 22, 28 and 29, respectively.

When the SBC mode is designated as the waveform mode and the pattern data D1, D2, D3 ... Are given, the operation is performed as shown in FIG. When the pattern data D1 is “0” in the first test cycle, the control signals “1”, “0”, “0”, “1”, are supplied to the terminals 31, 32, 33, 34, 35, 36, respectively. "1" and "0" are given. The timing clocks T1, T2, T3 are sequentially delayed in phase from the beginning of the test cycle, that is, T1 is the most advanced and T3 is the most delayed. Therefore, T1 passes through the gate 16 and the first flip-flop 24 is set at T1, then T2 passes through the gate 19, the first flip-flop 24 is reset at T2, and then T3 passes through the gate 21. Then, the first flip-flop 24 is set at T3, and for the pattern data D1 = 0, the output of the first flip-flop 24 becomes as shown in the output of the FF 24 in the test cycle of D1 in FIG.

When the waveform mode is SBC and the pattern data is D2 = “1”, as shown in the second test period of FIG. 4, the terminals 31 to 36 are respectively inverted from the case of D1 = “0”. Control signals are provided. Therefore, T1 passes through the gate 17 and the first flip-flop 24 is reset by T1, then T2 passes through the gate 18 and the first flip-flop 24 is set from T2, and then T3 passes through the gate 22. Then, the first flip-flop 24 is reset by T3. Therefore, when D1 = 1, the output of the first flip-flop 24 becomes as shown by the output of the FF 24 in the test cycle of D2 in FIG.

As can be understood from these, the SBC waveform is such that an RZ waveform is created by T2 and T3 with respect to the pattern data, and the RZ waveform is surrounded by data obtained by inverting the pattern data. Therefore, in addition to T2 and T3, T1 is used as a timing clock to generate inverted data before the RZ waveform created by T2 and T3.

Further, in order to use this test system for input / output pins, the driver 26 is enabled (operating) by the output of the second flip-flop 31 or disabled (inoperative: high impedance). Output status). To enable the driver 26, the control signal at the terminal 37 is set to "1", the gate 28 is opened, and the second flip-flop 31 is set at T4. To disable the driver 26, the control signal at the terminal 38 is set to "1", the gate 29 is opened, and the second flip-flop 31 is reset at T5. As shown in the test cycles D1 to D3 in FIG. 4, the driver 26 is enabled over a plurality of test cycles, or as shown in the test cycle D4, it is enabled only between T4 and T5 of one test cycle. You will be disappointed. The output of the driver 26 in the control state of FIG. 4 is as shown in the bottom row of FIG.

[0008]

[Problems to be solved by the device]

 As described above, in order to create the SBC waveform, in addition to the timing clocks T2 and T3 for creating the RZ waveform, one timing clock T1 that is advanced from these is required. Further, in order to output the SBC waveform data to the IC element under test 27 for one test cycle, a timing clock T4 which is advanced from T2 and a timing clock T5 which is delayed from T3 are required. As described above, conventionally, five timing clocks T1 to T5 are used, and accordingly, five timing generators 11 to 15 are prepared. A timing generator that operates at high speed and with high accuracy is expensive, and costs 200,000 yen, for example. Therefore, providing five timing generators for all test systems (each pin) was a large sum of money for the timing generators alone.

[0009]

[Means for Solving the Problems]

 According to this invention, among the three timing clocks for generating the output waveform of the specified waveform mode and pattern data as the timing clock for enabling the driver, that is, for setting the second flip-flop. The one with the most advanced phase is used, and one of the three timing clocks for creating the output waveform as the timing clock for disabling the driver, that is, for resetting the second flip-flop. Also uses the fourth timing clock with a delayed phase.

[0010]

【Example】

 FIG. 1 shows an embodiment of the present invention, in which parts corresponding to those in FIG. 3 are designated by the same reference numerals. In this embodiment, the timing generator 14 in FIG. 3 is omitted, that is, the timing clock T4 is omitted, and the timing clock T1 from the timing generator 11, that is, the output waveform is supplied to the gate 28 controlled by the control signal at the terminal 37. The one with the most advanced phase among the three timing clocks T1 to T3 for making the clock is given. Further, a delay element 41 is inserted in series between the output side of the gate 28 and the set terminal S of the second flip-flop 31 if necessary.

FIG. 2 shows an operation example in this case corresponding to the example of FIG. Since T1 to T3 are the same as in the case of FIG. 4, the output (FF24 output) of the first flip-flop 24 generated by the designated waveform mode and the pattern data is the same, and therefore the output to the terminals 31 to 36 is made. Each control signal is also the same. The control signals of the terminals 37 and 38 to the gates 28 and 29 for setting the driver 26 in the enable state or the disable state are also the same as in the case of FIG. However, when the driver 26 is enabled, the gate 37 is opened, T1 passes through this, and the second flip-flop 31 is set. At this time, in this example, the second flip-flop 31 is set by the delay element 41 with a delay of Ta from T1, so that the first flip-flop 24 is set or reset by T1 as shown in FIG. The second flip-flop 31 is set after the driver 26 is set to the set or reset state without fail, that is, after the driver 26 is set up to the set or reset state. Therefore, the state of the waveform set by T1 is surely obtained as the output of the driver 26.

As for the control for disabling the driver 26, T5, which is later than any of the timing clocks T1 to T3 for waveform generation, is used as in the conventional case, and is controlled in the same manner as in the conventional case. Similarly to the operation shown in FIG. 4, the target driver output can be obtained. Even if the delay element 41 is omitted, the delay element 41 can be omitted if the rise of the output of the first flip-flop 31 is delayed with respect to the setup of the driver 26 for the waveform control by T1.

[0013]

[Effect of the device]

 As described above, according to the present invention, since the timing clock for enabling the driver is the one having the most advanced phase among the three timing clocks for waveform creation, the timing generator is used. Since one can be omitted for each test system and the timing generator is more expensive than before, the price of the IC tester as a whole can be reduced considerably.

[Brief description of drawings]

FIG. 1 is a logic circuit diagram showing an embodiment of the present invention.

FIG. 2 is a time chart showing an operation example of the embodiment of FIG.

FIG. 3 is a logic circuit diagram showing a conventional waveform output device.

FIG. 4 is a time chart showing an operation example of the apparatus of FIG.

Claims (1)

[Scope of utility model registration request] 1. The three timing clocks are selectively distributed and supplied to a set terminal and a reset terminal of a first set / reset flip-flop according to a designated waveform mode and pattern data, and an output of the first flip-flop is supplied. A waveform output device for an IC tester, which outputs through a driver and controls the driver to an enable state and a disenable state by an output of a second set / reset flip-flop, wherein the three timing clocks are used as a set timing clock of the second flip-flop. An IC having the most advanced phase is used, and a fourth timing clock having a phase later than any of the three timing clocks is used as a reset timing clock of the second flip-flop. Waveform output for tester Force device.