JPH0562466B2 - - Google Patents
Info
- Publication number
- JPH0562466B2 JPH0562466B2 JP58144715A JP14471583A JPH0562466B2 JP H0562466 B2 JPH0562466 B2 JP H0562466B2 JP 58144715 A JP58144715 A JP 58144715A JP 14471583 A JP14471583 A JP 14471583A JP H0562466 B2 JPH0562466 B2 JP H0562466B2
- Authority
- JP
- Japan
- Prior art keywords
- rom
- film
- transparent resin
- sealing
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000011347 resin Substances 0.000 claims description 14
- 229920005989 resin Polymers 0.000 claims description 14
- 238000007789 sealing Methods 0.000 claims description 10
- 239000004065 semiconductor Substances 0.000 claims description 9
- 239000011521 glass Substances 0.000 claims description 7
- 229910018072 Al 2 O 3 Inorganic materials 0.000 claims description 4
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 4
- 238000000034 method Methods 0.000 claims description 4
- 238000005229 chemical vapour deposition Methods 0.000 claims description 3
- 238000004544 sputter deposition Methods 0.000 claims description 3
- 239000000919 ceramic Substances 0.000 description 3
- 230000003287 optical effect Effects 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3135—Double encapsulation or coating and encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Non-Volatile Memory (AREA)
Description
【発明の詳細な説明】
本発明は光消去、電気的書き込み可能リード・
オンリー・メモリー（以下EP・ROMと略記す
る）半導体装置の樹脂封止方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention provides a photo-erasable, electrically writable lead.
This invention relates to a resin sealing method for an only memory (hereinafter abbreviated as EP/ROM) semiconductor device.
従来、EP・ROMは、第１図に示す如くセラミ
ツク・ステム２に組み立てられたEP・ROM素子
１をセラミツク・キヤツプ３で封止し、セラミツ
ク・キヤツプ３には石英あるいはサフアイヤから
なるガラス窓４が取付けられた構造となつてい
る。 Conventionally, in the EP-ROM, an EP-ROM element 1 assembled on a ceramic stem 2 is sealed with a ceramic cap 3 as shown in FIG. 1, and the ceramic cap 3 has a glass window 4 made of quartz or sapphire. The structure is equipped with
しかし、上記従来技術では、EP・ROMの封止
部品のコストが高くつき、且つ、封止工数が大き
いという欠点があつた。 However, the above-mentioned conventional technology has disadvantages in that the cost of the EP/ROM sealing parts is high and the number of sealing steps is large.
本発明は、かかる従来技術の欠点をなくし、低
コストで且つ封止工数の少ない、また信頼性がよ
い半導体装置の樹脂封止方法を提供することを目
的とする。 SUMMARY OF THE INVENTION An object of the present invention is to eliminate the drawbacks of the prior art, and to provide a method for resin-sealing a semiconductor device that is low in cost, requires fewer sealing steps, and has good reliability.
上記目的を達成するための本発明の基本的な構
成は、半導体装置において、EP・ROM半導体素
子が透明樹脂に封止されて成ることを特徴とする
こと、及び、前記透明樹脂封止EP・ROMの少な
くとも透明樹脂表面には、SiO2膜あるいはAl2O3
膜が形成されて成ることを特徴とする。 The basic structure of the present invention for achieving the above object is that, in a semiconductor device, an EP/ROM semiconductor element is sealed with a transparent resin, and the EP/ROM semiconductor element sealed with the transparent resin is At least the transparent resin surface of the ROM is coated with SiO 2 film or Al 2 O 3
It is characterized by the formation of a film.
以下、実施例により本発明を詳述する。 Hereinafter, the present invention will be explained in detail with reference to Examples.
第２図は本発明の一実施例を示すEP・ROM装
置の断面図である。EP・ROM素子１１はリード
フレーム１２に組立てられ、透明樹脂１３にて封
止され、該透明樹脂１３の表面にはスパツタ法あ
るいは光CVD法等により常温乃至200℃程度で
SiO2膜あるいはAl2O3膜から成るガラス膜１４が
形成されて成る。 FIG. 2 is a sectional view of an EP/ROM device showing an embodiment of the present invention. The EP/ROM element 11 is assembled on a lead frame 12 and sealed with a transparent resin 13, and the surface of the transparent resin 13 is coated at room temperature to about 200°C by a sputtering method or optical CVD method.
A glass film 14 made of a SiO 2 film or an Al 2 O 3 film is formed.
本発明の如く、EP・ROM素子を透明樹脂に封
止することにより、EP・ROMの光消去機能を保
つたまゝ、低コストで且つ封止工数の少ない
EP・ROM装置が製作できると共に、透明樹脂表
面にSiO2膜またはAl2O3膜を形成することによ
り、EP・ROM装置の耐湿性を光消去特性の劣化
もなく向上させることができる等の効果がある。 By encapsulating the EP/ROM element in a transparent resin as in the present invention, the optical erasing function of the EP/ROM can be maintained, while the cost is low and the number of sealing steps is reduced.
Not only can EP/ROM devices be manufactured, but by forming a SiO 2 film or Al 2 O 3 film on the transparent resin surface, the moisture resistance of EP/ROM devices can be improved without deterioration of optical erasing characteristics. effective.
また、スパツタ法または光CVD法により常温
から200℃程度の温度範囲でガラス膜を、素子を
封止した透明樹脂の表面に形成できるので、高温
にさらされることにより発生する素子の信頼性低
下を招くこともない。 In addition, since a glass film can be formed on the surface of the transparent resin that seals the device at a temperature range from room temperature to about 200℃ using the sputtering method or photo-CVD method, it is possible to reduce the reliability of the device due to exposure to high temperatures. I don't even invite you.
第１図は従来技術によるEP・ROM装置の断面
図、第２図は本発明の一実施例を示すEP・ROM
装置の断面図である。
１，１１……EP・ROM素子、２……ステム、
３……キヤツプ、４……ガラス窓、１２……フレ
ーム、１３……透明樹脂、１４……ガラス層。
FIG. 1 is a sectional view of an EP/ROM device according to the prior art, and FIG. 2 is an EP/ROM showing an embodiment of the present invention.
FIG. 2 is a cross-sectional view of the device. 1, 11... EP/ROM element, 2... Stem,
3...Cap, 4...Glass window, 12...Frame, 13...Transparent resin, 14...Glass layer.
Claims (1)
ー・メモリー半導体素子の全体を透明樹脂で封止
する工程、前記半導体素子の全体を封止している
前記透明樹脂の表面に、常温から200℃程度の温
度範囲でスパツタ法または光CVD法により、ガ
ラス膜を形成する工程を有することを特徴とする
半導体装置の樹脂封止方法。 ２ 前記ガラス膜はSiO2膜またはAl2O3膜からな
ることを特徴とする特許請求の範囲第１項記載の
半導体装置の樹脂封止方法。[Claims] 1. A step of sealing the entire optically erasable and electrically writable read-only memory semiconductor element with a transparent resin, the surface of the transparent resin sealing the entire semiconductor element, A resin sealing method for a semiconductor device, comprising a step of forming a glass film by a sputtering method or a photo CVD method at a temperature range from room temperature to about 200°C. 2. The resin sealing method for a semiconductor device according to claim 1, wherein the glass film is made of a SiO 2 film or an Al 2 O 3 film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58144715A JPS6035546A (en) | 1983-08-08 | 1983-08-08 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58144715A JPS6035546A (en) | 1983-08-08 | 1983-08-08 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6035546A JPS6035546A (en) | 1985-02-23 |
| JPH0562466B2 true JPH0562466B2 (en) | 1993-09-08 |
Family
ID=15368608
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58144715A Granted JPS6035546A (en) | 1983-08-08 | 1983-08-08 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6035546A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56142245U (en) * | 1980-03-25 | 1981-10-27 |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5730351A (en) * | 1980-07-30 | 1982-02-18 | Nec Corp | Resin-sealed type semiconductor device |
| JPS57164585A (en) * | 1981-04-02 | 1982-10-09 | Toshiba Corp | Photosemiconductor device |
-
1983
- 1983-08-08 JP JP58144715A patent/JPS6035546A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5730351A (en) * | 1980-07-30 | 1982-02-18 | Nec Corp | Resin-sealed type semiconductor device |
| JPS57164585A (en) * | 1981-04-02 | 1982-10-09 | Toshiba Corp | Photosemiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6035546A (en) | 1985-02-23 |
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