JPH056177B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a defect inspection technique, and in particular to a technique for inspecting defects in the appearance of a pattern. Concerning effective techniques used for inspection.

[Background Art] As a method for performing visual defect inspection on patterns of photomasks (including reticles, hereinafter referred to as masks) used in the manufacture of semiconductor devices, a virtual pattern that is virtually created from pattern design data and a A possible method is to compare the actual pattern of the mask manufactured from the data and determine a difference between the two as a defect.

However, in such a defect inspection method, the input to the comparison section of the virtual pattern cannot keep up with the input to the comparison section of the real pattern in an area with high pattern density, so the overall inspection speed becomes slow and the inspection time increases. The inventor of the present invention has revealed that there is a problem in that the length becomes long.

[Objective of the Invention] The object of the present invention is to provide a method for detecting defects that can reduce the time required for automatic inspection of an object to be inspected with variations in pattern density to the minimum without performing any special processing on pattern design data or the like. Our goal is to provide inspection technology.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the Invention] A brief overview of typical inventions disclosed in this application is as follows.

In other words, defects are detected by comparing a virtual pattern virtually obtained from pattern design data with an actual pattern obtained by an imaging device that relatively scans an inspection object manufactured based on the pattern design data. In a defect inspection method that detects defects, the frequency of defect detection is monitored for each desired scanning range, and the relative scanning speed of the imaging device is reduced to selectively scan defects in the scanning range where defects frequently occur. This will cause the system to retry the process.

Further, the defect inspection device of the present invention includes a virtual pattern generation device that generates a virtual pattern from pattern design data and stores it in a virtual pattern memory, an imaging device that detects an image of a real pattern on an object to be inspected, and an image pickup device that detects an image of a real pattern on an inspection target. A binarization circuit that binarizes an image and stores it in the real pattern memory, a defect determination circuit that compares corresponding areas in the virtual pattern memory and the real pattern memory to determine the presence or absence of a defect in the real pattern, and a detected defect. a defect memory that stores the number of
By controlling the table, a driving device that drives this XY table, a laser length measuring device that detects the position of the XY table, and the driving device based on the positional information of the XY table obtained from this laser length measuring device, A control means for relative scanning of the inspection object by the imaging device, a virtual pattern creation device, a virtual pattern memory, The control means includes a binarization circuit, an actual pattern memory, and a timing generator that sends a timing signal to the defect determination circuit, and the control means refers to the number of defects stored in the defect memory for each desired scanning area,
For a scanning range where defects frequently occur, a control operation is performed in which the relative scanning speed of the imaging device is reduced and defect inspection is selectively retried.

Embodiment 1 FIG. 1 is a block diagram showing a defect inspection device used in a defect inspection method according to an embodiment of the present invention, and FIG.
FIG. 3, FIG. 4 are explanatory diagrams for explaining the operation thereof.

In FIG. 1, reference numeral 1 denotes a mask as an object to be inspected, and a pattern for transferring an integrated circuit or the like in a semiconductor device is formed on the mask 1. The mask 1 is aligned and placed on an XY table 2, and the XY table 2 is moved in the XY directions by a drive device 3.
A light source 4 such as a mercury lamp is installed below the XY table 2, and the light source 4 illuminates the mask 1. Above the XY table 2, a one-dimensional solid-state imaging device (hereinafter referred to as CCD) 5 as an imaging device converts the light transmitted through the mask 1 into an objective lens 6.
The CCD 5 is configured to relatively scan the mask 1 by moving the XY table 2. There are many CCD5s (for example,
1024 bits) pixels are arranged in a row in the X direction, and the mask 1 is scanned in the Y direction perpendicular to the array, and the pixel group self-scans in the X direction during scanning. It is designed to output a pattern imaging signal.

A binarization circuit 7 is connected to the CCD 5, and this circuit 7 converts the image signal from the CCD 5 into 2 bits using a threshold value.
It is configured to be converted into a value. A real pattern memory 8 is connected to the output terminal of the binarization circuit 7, and this memory 8 stores information regarding the pattern (hereinafter referred to as the real pattern) on the mask 1 obtained by the imaging signal of the CCD 5. It's becoming like that.
An output end of the actual pattern memory 8 is connected to one input end of a defect determination circuit 9, and a defect memory 10 is connected to the output end of the defect determination circuit 9.

11 is a magnetic tape for inspection, and the mask 1
Inspection data obtained by reorganizing pattern design data used to create a pattern for defect inspection is stored. This tape is played back by the magnetic recording/playback device 12. A buffer memory 13 is connected to the magnetic recording/reproducing device 12,
The output end of this memory 13 is connected to a virtual pattern creation device 14. This creation device 14 creates a virtual pattern (hereinafter referred to as a virtual pattern) using defect inspection data reproduced from the magnetic tape 11, and outputs a signal of the pattern to a virtual pattern memory 15. .

The output end of the virtual pattern memory 15 is connected to the other input end of the defect determination circuit 9. The defect determination circuit 9 is composed of a comparison circuit and the like, and is configured to compare the real pattern and the virtual pattern, and determine a defect if there is a difference between the two.

The XY table 2 is provided with a laser length measuring device 16, and a timing generator 17 is connected to this length measuring device 16. The timing generator 17 includes a binarization circuit 7, a real pattern memory 8, a virtual pattern creation device 14, and a virtual pattern memory 1.
5 and the defect determination circuit 9 to synchronize them. The timing generator 17 is adapted to also transmit data to a first central processing unit (CPU) 18 and is configured to be controlled by this CPU 18. The first CPU 18 is linked with a second CPU 19 for controlling the magnetic recording/reproducing device 12, buffer memory 13, virtual pattern creation device 14, and the like.

Note that peripheral devices 20 such as an input device, a display device, and an external storage device are connected to the first CPU 18.

Next, a mask defect inspection method according to an embodiment of the present invention will be described using the defect inspection apparatus having the above configuration.

When the CCD 5 starts scanning in the Y direction due to the movement of the XY table 2, the CCD 5 images the pattern of the mask 1, and thereby the actual pattern is stored in the memory 8. On the other hand, inspection data corresponding to the design pattern data is read from the tape 11, a virtual pattern is created by the creation device 14 based on this data, and the virtual pattern is stored in the virtual pattern memory 1.
5 will be remembered.

For example, as shown in FIG.
When the density of the patterns 21 in the first scanning line region _L1 is sparse, the scanning of the CCD 5 in the Y direction is performed at a normal high speed. That is, as shown in FIG. 3, this scanning speed is the speed at which the pixel 5a is advanced by one pitch corresponding to the width W when the self-scanning of the group of pixels 5a of the CCD 5 is completed once, and the pattern is is the maximum speed required to obtain

This scanning speed is created by controlling the driving device 3 of the XY table 2 based on the timing signal of the timing generator 17 via the first CPU 18.

A timing generator 17 converts the same timing signal into a binarization circuit 7, a real pattern memory 8, a virtual pattern creation device 14, and a virtual pattern memory 15.
and the defect creation circuit 9, and are operated synchronously. Thereby, the defect determination circuit 9 compares the real pattern reproduced and inputted from the real pattern memory 8 and the virtual pattern reproduced and inputted from the virtual pattern memory 15, and determines that it is defective if the two are different. and transmits the defect signal to the defect memory 10.
Output it to and store its coordinates etc.

Then, if the density of the pattern 21 in the mask 1 is dense in the second scanning line region _L2 ,
The CCD 5 scans in the Y direction at a low speed, for example, at half the scanning speed. That is, as shown in FIG.
When the self-scanning of the pixel 5a group of 5 is completed once, the speed advances by 1/2 of the width W of the pixel 5a. Therefore, the pattern shown in the shaded area in FIG. 4 is duplicated.
Therefore, it is necessary to remove the actual pattern signal in this overlapping portion.

The timing generator 17 intermittently sends timing signals to the binarization circuit 7 and the actual pattern memory 8 every other week so that the overlapping portions are removed according to instructions from the first CPU 18. As a result, a normal actual pattern with no overlapping portions is input from the actual pattern memory 8 to the defect determination circuit 9.

On the other hand, the timing generator 17 continues to send the same timing signal as during the high-speed scanning to the virtual pattern creation device 14, virtual pattern memory 15, and defect determination circuit 9. Therefore, the virtual pattern creation device 14 continues to create virtual patterns using the same level of ability as during high-speed scanning, but since the pattern 21 in the second scanning line area _L2 has a high density, it takes time to create it. . However, since the input from the real pattern memory 8 to the actual pattern defect determination circuit 9 is made every other cycle, the input from the virtual pattern memory 15 to the virtual pattern defect determination device 9 is delayed in time for the input of the actual pattern. It will never go away. In other words, the virtual pattern creation device 14 continues to work even while the binarization circuit 7 and the real pattern memory 8 are at rest, and relatively fills in the time required. That is, by slowing down the pattern input speed to the defect measurement circuit 9, delays in creating virtual patterns can be relatively avoided.

Then, the defect determination circuit 9 compares the virtual pattern that is input without delay with the normal real pattern that is input after removing the overlapping portion, and performs defect determination.

Subsequently, when the density of the pattern 21 in the mask 1 returns to sparse again in the third scanning line region, the scanning of the CCD 5 in the Y direction is returned to the normal high speed. In this case, since the pattern density is sparse,
The virtual pattern creation device 14 does not take much time to create a virtual pattern, and even if the actual pattern is input to the defect determination circuit 9 at high speed, the virtual pattern can be input in sufficient time.

Here, the switching of the scanning speed according to the pattern density is set in advance for each scanning line area, and this is recorded on the magnetic tape 11 together with the pattern data, and the second CPU 19 issues a switching command based on this switching data. The 1st CPU18
This is done by sending the

Note that the density of the pattern can be easily known from the pattern design data, and when organizing the inspection data based on this data, it is easily possible to take the scanning speed switching data into consideration.

Embodiment 2 FIG. 5 is an explanatory diagram showing another embodiment of the present invention.

This embodiment is different from the previous embodiments in that the scanning speed switching information is not set in advance, and the input of the ideological pattern to the defect determination circuit is delayed due to the increase in the required calculation time due to the increase in pattern density. The point is that the scanning speed is switched each time the scanning speed is recognized based on the frequency of defect detection, and the scanning speed is switched each time.

In other words, a mask 1 created with sufficient care
There is naturally an upper limit to the number of pattern defects detected in the
By utilizing the fact that it can be estimated that a real pattern in a region shifted from the virtual pattern is erroneously compared, an input delay of the virtual pattern due to an increase in pattern density is detected.

For example, as shown in FIG. 5, when scanning is performed at high speed and a high-density part of the pattern 21 in the first scanning line area _L1 is reached, the virtual pattern creation device 14 (see FIG. 1, the same applies hereinafter) ) has a high density, so it takes time to create a virtual pattern. Accordingly, the input of the virtual pattern to the defect determination circuit 9 is delayed from the input of the actual pattern. As a result, defective signals occur frequently, so
1CPU 18 recognizes this through defective memory 10 and sends a scanning speed switching command to drive device 3. The drive device 3 moves the XY table 2 according to this command.
is moved back, the CCD 5 is relatively returned to the beginning of the first scanning line region _L1 of the mask 1, and the same region _L1 is rescanned at a slower scanning speed.

The first CPU 18 simultaneously reports to the second CPU 19 that the scanning speed is switched. 2nd CPU19
Based on this report, the test tape 11 is rewound and the test data is replayed from a portion corresponding to the beginning of the first scanning line area.

The effect after the scanning speed is slowed is similar to that in the high-density region described above.

When the inspection by low-speed scanning for the first scanning line area L ₁ is completed and the CCD 5 moves relatively to the second scanning line area L ₂ , the first CPU 18 sends a scanning speed switching command to the driving device 3 .

Based on this command, the drive device 3 moves the XY table 2 at the original normal speed. This allows CCD
5 scans the second scanning line _L2 area at high speed. This high-speed scanning is interrupted after the CCD 5 moves to another scan line area, unless a high-density portion is encountered which causes a delay in inputting the virtual pattern. Therefore, lengthening of the inspection time can be suppressed as a whole.

[Effects] (1) The pattern density is determined based on the frequency of defect detection, and control is performed by selectively lowering the scanning speed in scanning areas with large pattern density to perform defect scanning. Inspection time for inspection objects with variations in pattern density can be shortened to the minimum without performing special processing on pattern design data or the like for the purpose of identifying large and small densities.

Although the invention made by the present inventor has been specifically explained based on Examples above, the present invention is not limited to the above-mentioned Examples, and it is understood that various changes can be made without departing from the gist of the invention. Needless to say.

For example, the method for setting the section in which the scanning speed is slowed is not limited to the above-mentioned embodiment, but it may also be possible to move a CCD for pattern density measurement in front of the inspection CCD and set the section in a timely manner according to the measurement results of this CCD. good.

The imaging device is not limited to a CCD, but may be a combination of a photodiode array and a shift register for scanning the photodiode array, for example.

[Field of Application] In the above explanation, the invention made by the present inventor was mainly applied to defect inspection of masks, which is the background field of application, but the invention is not limited to this, for example. ,
It can also be applied to visual defect inspection of patterns formed on wafers.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention;
FIG. 2, FIG. 3, and FIG. 4 are explanatory diagrams for explaining the operation thereof, and FIG. 5 is an explanatory diagram for explaining the operation of another embodiment of the present invention. 1...Mask (inspection target), 2...XY table, 3...Drive device, 4...Light source, 5...CCD
(Imaging device), 7... Binarization circuit, 8... Real pattern memory, 9... Defect determination circuit, 10... Defect memory, 11... Inspection data tape, 13... Buffer memory, 14... Virtual pattern making device,
15... Virtual pattern memory, 16... Laser length measuring device, 17... Timing generator, 18...
...1st CPU (control means), 19...2nd CPU.

Claims (1)

[Claims] 1. A virtual pattern virtually obtained from pattern design data and an actual pattern obtained by an imaging device that relatively scans an inspection object manufactured based on the pattern design data. A defect inspection method for detecting defects by comparison, which monitors the frequency of defect detection for each desired scanning range,
A defect inspection method comprising selectively retrying the defect inspection by selectively lowering the relative scanning speed of the imaging device for the scanning range where the defects frequently occur. 2. A virtual pattern generation device that generates a virtual pattern from pattern design data and stores it in a virtual pattern memory, an imaging device that detects an image of a real pattern on an object to be inspected, and a device that binarizes the image of the real pattern to generate a real pattern. A binarization circuit for storing in a memory, a defect determination circuit for comparing corresponding areas in the virtual pattern memory and the real pattern memory to determine the presence or absence of a defect in the real pattern, and a defect storing the number of detected defects. A memory, an XY table on which the object to be inspected is placed, a drive device for driving the XY table, a laser length measuring device for detecting the position of the XY table, and the XY table obtained from the laser length measuring device. A control means for causing the imaging device to perform relative scanning of the inspection object by controlling the drive device based on position information of the table; and a control means interposed between the laser length measuring device and the control means. and a timing generator that sends a timing signal to the virtual pattern creation device, the virtual pattern memory, the binarization circuit, the real pattern memory, and the defect determination circuit based on a command from the control means. , the control means refers to the number of defects stored in the defect memory for each desired scanning area, and selectively controls the relative scanning speed of the imaging device for the scanning range where the defects frequently occur. 1. A defect inspection device characterized by performing a control operation of selectively retrying a defect inspection by reducing the number of defects.