JPH0561723B2 - - Google Patents

Info

Publication number
JPH0561723B2
JPH0561723B2 JP10094085A JP10094085A JPH0561723B2 JP H0561723 B2 JPH0561723 B2 JP H0561723B2 JP 10094085 A JP10094085 A JP 10094085A JP 10094085 A JP10094085 A JP 10094085A JP H0561723 B2 JPH0561723 B2 JP H0561723B2
Authority
JP
Japan
Prior art keywords
conductor
film
glass substrate
paste
metallo
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP10094085A
Other languages
Japanese (ja)
Other versions
JPS61258439A (en
Inventor
Kazuo Baba
Yoshinori Yamaguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujifilm Business Innovation Corp
Original Assignee
Fuji Xerox Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Xerox Co Ltd filed Critical Fuji Xerox Co Ltd
Priority to JP10094085A priority Critical patent/JPS61258439A/en
Publication of JPS61258439A publication Critical patent/JPS61258439A/en
Publication of JPH0561723B2 publication Critical patent/JPH0561723B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はガラス基板にメタロオーガニツク金ペ
ーストを用いて導体を形成する場合の密着強度を
大きくし、半導体素子とのワイヤーボンデイング
を可能にする厚膜混成集積回路に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention increases the adhesion strength when forming a conductor on a glass substrate using a metallo-organic gold paste, thereby enabling wire bonding with a semiconductor element. Concerning thick film hybrid integrated circuits.

〔従来の技術〕[Conventional technology]

従来の厚膜混成回路として、例えば、粉体の金
ペーストを用い、セラミツク（アルミナセラミツ
ク等）基板上にスクリーン印刷および焼成によつ
て導体を形成し、この導体に半導体素子及びその
他の電子部品を接続したものがある。 In conventional thick film hybrid circuits, for example, a conductor is formed using powdered gold paste on a ceramic (alumina ceramic, etc.) substrate by screen printing and firing, and semiconductor elements and other electronic components are attached to this conductor. There is something connected.

しかし、アルミナセラミツクを基板に用いた場
合、その表面が1μm程度の凹凸を有しているた
め、厚膜回路を形成後に更に同一基板上に薄膜素
子を接続しようとすると、グレーズ層を形成する
必要がある。また、金ペーストに粉体を原材料と
しているために、導体膜の高密化に限界がある。 However, when alumina ceramic is used as a substrate, its surface has irregularities of about 1 μm, so if you try to connect thin film elements on the same substrate after forming a thick film circuit, it is necessary to form a glaze layer. There is. Furthermore, since the gold paste uses powder as its raw material, there is a limit to how high the density of the conductor film can be made.

そこで、基板にガラスを用い、導体材料にメタ
ロオーガニツク金ペーストを用いて前述の表面
性、高密度化の不具合を解消し、かつコストダウ
ンを図つた方法が提案されている。 Therefore, a method has been proposed in which glass is used for the substrate and metallo-organic gold paste is used as the conductor material to solve the above-mentioned problems with surface quality and high density, and to reduce costs.

メタロオーガニツク金ペーストは、 CH3（CH2）ｎ−Ｓ−Au の化学式で示される金属錯体と有機溶媒（ターピ
ネオール）を約40wt％対60wt％の割合いで混合
し、ペースト状にしたものである。また、ガラス
基板としては、バリウムホウケイ酸、ホウケイ
酸、アルミノケイ酸等が用いられる。このような
ガラス基板にメタロオーガニツク金ペーストをス
クリーン印刷および焼成を行なうことにより、所
望のパターンの導体膜を形成することができる。 Metallo-organic gold paste is made into a paste by mixing a metal complex represented by the chemical formula CH 3 (CH 2 ) n-S-Au and an organic solvent (terpineol) at a ratio of approximately 40 wt% to 60 wt%. be. Further, as the glass substrate, barium borosilicate, borosilicate, aluminosilicate, etc. are used. By screen printing and baking a metallo-organic gold paste on such a glass substrate, a conductive film with a desired pattern can be formed.

尚、基板の多層化に厚膜技術を用いた発明とし
て、特開昭52−137666号があり、大面積化及び高
密度化を図つたものとして、ソリツド・ステー
ト・テクノロジイ（Solid state technology）日
本版1980，11月号（31ページ〜36ページ）に記載
の「大面積基板上への微細な導体パターンの形成
法」がある。 In addition, there is an invention in Japanese Patent Application Laid-Open No. 137666/1989 that uses thick film technology to multilayer a substrate, and solid state technology is an invention that aims to increase the area and density. There is a ``method for forming fine conductor patterns on large-area substrates'' described in the November issue of Japan Edition 1980 (pages 31 to 36).

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

しかし、従来の厚膜混成集積回路にあつては、
低温で焼成する必要がある（ガラス基板を用いた
ことに起因する）ため、形成された導体膜の密着
強度が小さく、半導体素子を導体膜へボンデイン
グできないという不具合があつた。 However, in the case of conventional thick film hybrid integrated circuits,
Since it is necessary to bake at a low temperature (due to the use of a glass substrate), the adhesion strength of the formed conductor film is low, resulting in a problem that the semiconductor element cannot be bonded to the conductor film.

〔問題点を解決するための手段及び作用〕[Means and actions for solving problems]

本発明は上記に鑑みてなされたものであり、半
導体素子等に対するボンデイング等を可能にする
ため、メタロオーガニツク金ペーストに所定量の
カルボン酸第二銅を添加して導体膜の密着強度を
高めるようにした厚膜混成集積回路を提供するも
のである。 The present invention has been made in view of the above, and in order to enable bonding to semiconductor elements, etc., a predetermined amount of cupric carboxylate is added to a metallo-organic gold paste to increase the adhesion strength of a conductor film. The present invention provides a thick film hybrid integrated circuit as described above.

〔実施例〕〔Example〕

以下、本発明による厚膜混成集積回路を詳細に
説明する。 Hereinafter, the thick film hybrid integrated circuit according to the present invention will be described in detail.

図は本発明の一実施例を示し、バリウムホウケ
イ酸、ホウケイ酸、アルミノケイ酸等を用いたガ
ラス基板１と、前記メタロオーガニツク金ペース
トに所定量の脂肪族カルボン酸第二銅を添加した
ペーストをガラス基板１上にスクリーン印刷した
のち600℃〜700℃の温度により焼成して形成され
る導体膜２ａ，２ｂ，２ｃと、導体膜２ｂ上にダ
イボンデイングされる半導体素子３と、該素子３
の入、出力部と導体膜２ａ，２ｃとを接続する金
線４ａ，４ｂ（導体膜２ａ，２ｂに対してはワイ
ヤボンデイングにより接続）と、導体膜２ａに対
してスルーホール５を形成すべく導体膜２ａ及び
ガラス基板１上に設けられるガラス膜６と、該ガ
ラス膜６の表面に形成されると共に一部がスルー
ホール５を介して導体膜２ａに接続される導体膜
７より構成される。 The figure shows an embodiment of the present invention, which includes a glass substrate 1 made of barium borosilicate, borosilicate, aluminosilicate, etc., and a paste made by adding a predetermined amount of cupric aliphatic carboxylate to the metallo-organic gold paste. conductor films 2a, 2b, 2c formed by screen printing on a glass substrate 1 and then baking at a temperature of 600°C to 700°C, a semiconductor element 3 die-bonded on the conductor film 2b, and the element 3.
In order to form gold wires 4a and 4b (connected to the conductor films 2a and 2b by wire bonding) connecting the input and output parts to the conductor films 2a and 2c, and a through hole 5 to the conductor film 2a. It is composed of a glass film 6 provided on the conductor film 2a and the glass substrate 1, and a conductor film 7 formed on the surface of the glass film 6 and partially connected to the conductor film 2a via the through hole 5. .

前記ペーストとしては、炭素数が４〜18の脂肪
族カルボン酸第二銅をメタロオーガニツク金ペー
ストに0.2％〜３％を添加すると共に、ブチルカ
ルビトールアセテート、ターピネオール等の溶剤
を加えて粘度を調整する。尚、炭素数が３以下で
はターピネオールに溶けずに分離し、炭素数が19
以上では銅の割合いが減少して接着強度が下が
る。従つて、炭素数としては４〜18の間が好適な
値となる。また、重量％においては、0.19wt％以
下では銅の割合いが減るために接着強度が下が
り、一方、3.1wt％以上ではスクリーンメツシユ
による印刷性が低下して材料の溶解度に基づく不
溶のものが表われ、ペーストの伸びが悪くなるほ
か、焼成により生じた導体膜と金線とのボンデイ
ング性が低下する現象を生じる。従つて、重量％
としては、0.2wt％〜3wt％が最適な値となる。 The paste is prepared by adding 0.2% to 3% of cupric aliphatic carboxylic acid having 4 to 18 carbon atoms to a metallo-organic gold paste, and adding a solvent such as butyl carbitol acetate or terpineol to reduce the viscosity. adjust. In addition, if the carbon number is 3 or less, it will not dissolve in terpineol and will separate, and if the carbon number is 19
If this is the case, the copper content will decrease and the adhesive strength will decrease. Therefore, a suitable value for the carbon number is between 4 and 18. In addition, when the weight percentage is less than 0.19wt%, the adhesion strength decreases because the proportion of copper decreases, while when it is more than 3.1wt%, the printability by screen mesh decreases, and it becomes insoluble due to the solubility of the material. This results in a phenomenon in which not only does the paste spread poorly, but also the bonding properties between the conductive film and the gold wire produced by firing are reduced. Therefore, weight%
The optimal value is 0.2wt% to 3wt%.

以上の構成において、前記配分によるペースト
（導体材料）をガラス基板１面上にスクリーン印
刷し、これを700℃で焼成して、導体膜２ａ，２
ｂ，２ｃを形成する。ついで半導体素子（トラン
ジスタチツプ等）３を導体膜２ｂ上に導電性接着
剤によつてダイボンデイングし、この半導体素子
３と導体膜２ａ及び２ｃとを金線２により接続す
る。また、スルーホール５を形成するために導体
膜２ａの表面にガラス膜６を形成し、その表面に
導体膜７を導体膜２ａ〜２ｃと同一の材料によつ
て形成する。 In the above structure, the paste (conductor material) according to the above distribution is screen printed on one surface of the glass substrate, and is fired at 700°C to form the conductive films 2a, 2.
b, 2c are formed. Next, a semiconductor element (such as a transistor chip) 3 is die-bonded onto the conductor film 2b using a conductive adhesive, and the semiconductor element 3 and the conductor films 2a and 2c are connected by gold wires 2. Further, in order to form the through holes 5, a glass film 6 is formed on the surface of the conductor film 2a, and a conductor film 7 is formed on the surface thereof using the same material as the conductor films 2a to 2c.

導体膜２ａ〜２ｃはカルボン酸第二銅を添加し
たことにより、ガラス基板との密着強度が著しく
増大し、従来の厚膜金導体と同一の条件によつて
ワイヤボンデイングを行なうことができる。ま
た、配線密度を従来に比べ約２倍（24本／１mm）
にすることができる。 By adding cupric carboxylate to the conductor films 2a to 2c, the adhesion strength to the glass substrate is significantly increased, and wire bonding can be performed under the same conditions as conventional thick film gold conductors. In addition, the wiring density is approximately twice that of the conventional method (24 lines/1mm).
It can be done.

〔発明の効果〕〔Effect of the invention〕

以上説明した通り本発明の厚膜混成集積回路に
よれば、メタロオーガニツク金ペーストに銅カル
ボン酸錯体を添加して導体材料としたため、導体
膜の密着強度が向上し半導体素子の実装が可能に
なると共に高密度配線が可能となる。更に、基板
及び配線材料のコストを従来に比べて大幅に低減
（例えば、70％減）させることができる。 As explained above, according to the thick film hybrid integrated circuit of the present invention, since a copper carboxylic acid complex is added to the metallo-organic gold paste to make the conductor material, the adhesion strength of the conductor film is improved and semiconductor elements can be mounted. At the same time, high-density wiring becomes possible. Furthermore, the cost of substrates and wiring materials can be significantly reduced (for example, by 70%) compared to conventional methods.

【図面の簡単な説明】[Brief explanation of the drawing]

図は本発明の一実施例を示す断面図。 符号の説明、１……ガラス基板、２ａ，２ｂ，
２ｃ，７……導体膜、３……半導体素子、４ａ，
４ｂ……金線、５……スルーホール、６……ガラ
ス膜。 The figure is a sectional view showing one embodiment of the present invention. Explanation of symbols, 1...Glass substrate, 2a, 2b,
2c, 7... Conductor film, 3... Semiconductor element, 4a,
4b...Gold wire, 5...Through hole, 6...Glass membrane.

Claims (1)

【特許請求の範囲】 １ ガラス基板上に導体材料を印刷し、これを焼
成して導体膜を形成し、該導体膜に半導体素子等
を接続して構成される厚膜混成集積回路におい
て、 前記導体材料は、メタロオーガニツク金ペース
トに炭素数４乃至18のカルボン酸第二銅を0.2重
量％乃至３重量％含む組成を有することを特徴と
する厚膜混成集積回路。[Scope of Claims] 1. A thick film hybrid integrated circuit configured by printing a conductor material on a glass substrate, baking it to form a conductor film, and connecting a semiconductor element, etc. to the conductor film, comprising: A thick film hybrid integrated circuit characterized in that the conductor material has a composition containing 0.2% to 3% by weight of cupric carboxylate having 4 to 18 carbon atoms in a metallo-organic gold paste.
JP10094085A 1985-05-13 1985-05-13 Thick film hybrid integrated circuit Granted JPS61258439A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10094085A JPS61258439A (en) 1985-05-13 1985-05-13 Thick film hybrid integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10094085A JPS61258439A (en) 1985-05-13 1985-05-13 Thick film hybrid integrated circuit

Publications (2)

Publication Number Publication Date
JPS61258439A JPS61258439A (en) 1986-11-15
JPH0561723B2 true JPH0561723B2 (en) 1993-09-07

Family

ID=14287346

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10094085A Granted JPS61258439A (en) 1985-05-13 1985-05-13 Thick film hybrid integrated circuit

Country Status (1)

Country Link
JP (1) JPS61258439A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3225854B2 (en) * 1996-10-02 2001-11-05 株式会社デンソー Thick film circuit board and wire bonding electrode forming method thereof

Also Published As

Publication number Publication date
JPS61258439A (en) 1986-11-15

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