JPH0560843A - Self-test circuit - Google Patents

Abstract

PURPOSE:To obtain a self-test circuit which can reduce a ratio of area in an IC device. CONSTITUTION:A linear feedback shift register (LFSR) 4 allows a test input data 7 to be input to a circuit 5 to be tested. A signature register (MISR) 6 compresses a test result data 8 which is output from the circuit 5 to be tested and then outputs it. A data comparison circuit 1 compares an output of an LFSR 4 with a comparison data 2 and then outputs a test end signal 3 based on the comparison result. The test end signal 3 allows operation of the LFSR 4 and the MISR 6 to be stopped. The circuit configuration is simpler than a conventional circuit where the number of input data is counted by a counter and execution of a test is stopped automatically based on this count value.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention particularly relates to a linear feedback shift register (hereinafter referred to as LFSR) and a signature register (hereinafter referred to as LFSR) when incorporated in an IC device.
MISR) to execute a test and automatically stop the execution of this test.

[0002]

2. Description of the Related Art Conventionally, in this type of self-test circuit, the output of the LFSR is used as a pseudo-random number generating circuit, and the test result based on the output of this LFSR is used as the MISR.
After compressing the data with, compare it with the expected value as a signature. Then, generally, the number of test executions is counted by a counter such as an up counter and a down counter, and when the count value reaches the required number, the test execution is automatically stopped. (Nikkei Electronics "Design Method of Logic LSI for Easy Test", June 20, 1983
Japanese edition, pages 123 to 133, and Iwanami Shoten Iwanami Course
Information Science 4 "The Logic of Information and Codes", 143-155
page)

[0003]

In the above-mentioned conventional self-test circuit, it is necessary to provide a counter for automatically stopping the execution of the test, and a plurality of counters corresponding to a plurality of test circuits are required. Need to be provided. Therefore, there is a problem that the ratio of the area of the self-test circuit to the circuit under test built in the IC device increases.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a self-test circuit capable of reducing the area ratio of an IC device.

[0005]

A self-test circuit according to the present invention comprises an n-bit (n; positive integer) linear feedback shift register for generating input data to the circuit under test, and an output of the circuit under test. in self-test circuit that includes a signature register for data compression data, i-th among the data series of the up to the period of the input data ^{(2 n -1) (i;} 1 to the 2 ⁿ -1 positive integer ) Storing means for storing arbitrary data, comparing means for comparing the arbitrary data with the input data, and stopping the operation of the linear feedback shift register and the signature register based on the comparison result of the comparing means. And a braking means for controlling the braking.

[0006]

Operation: Linear feedback shift register (LFS
R) is pseudo-random and all different (2 ⁿ -1) if a primitive polynomial is selected as the generator polynomial of the data.
It is possible to generate 100% data. However, data in which all bits are 0 is excluded. As described above, since the data series generated by the LFSR are all different data until (2 ⁿ -1) data are generated, (2 ⁿ −
1) The data generated up to the first will appear differently from all the data generated so far. The comparison means is the i-th (i; 1 to 2 ⁿ −) stored in the storage means.
Arbitrary data (a positive integer of 1) is compared with the input data to the circuit under test. Then, when the arbitrary data and the input data match, the braking means determines the LFSR and the signature register (MISR) based on the comparison result.
Stop the operation of. This allows the test execution to be stopped automatically.

According to this embodiment, the operations of the LFSR and the MISR are stopped based on the comparison result of the comparing means, so that the conventional counter for judging the stop of the test execution can be eliminated. Therefore, the ratio of the area of the self-test circuit to the circuit under test built in the IC device can be reduced.

In the present invention, the circuit under test can be tested by comparing the test result based on the output of the LFSR with the expected value as a signature after data compression by MISR.

[0009]

Embodiments of the present invention will now be described with reference to the accompanying drawings.

FIG. 1 is a block diagram showing a self-test circuit according to the first embodiment of the present invention. The LFSR 4 generates test input data (pseudo random number) 7 and inputs it to the circuit under test 5. The MISR 6 receives the test result data 8 output from the circuit under test 5, compresses it, and outputs it. The data comparison circuit 1 inputs the output of the LFSR 4 and the comparison data 2, compares them, and outputs a test end signal 3 based on the comparison result. That is, the plurality of EXOR gates 9 inputs the output of the LFSR 4 and the comparison data 2 and outputs the exclusive OR of both.
The OR gate 16 inputs the outputs of the plurality of EXOR gates 9, takes the OR of these and outputs them. Inverter 10
Inputs the output of the OR gate 16 and inverts it to output the test end signal 3. This test end signal 3 is LF
It is supplied to SR4 and MISR6.

In the self-test circuit configured as described above, the output of the LFSR 4 is input to the circuit under test 5 as the test input data 7, and the test input data 7 is output.
The test result data 8 of the circuit under test 5 based on
Input to R6. Then, the MISR 6 compresses the test result data 8 and then compares this with the expected value as a signature. In this case, all the circuits under test 5 are tested, but the test end signal 3 for ending the test.
Needs to be generated. That is, the data comparison circuit 1 is LF
The output of SR4 and the comparison data 2 are compared, and when both match completely, the test end signal 3 becomes "1".
Based on this test end signal 3, LFSR 4 and MI
The operation of SR6 stops. This will automatically stop the test execution.

According to the present embodiment, the data comparison circuit 1 is compared with the conventional counter for comparing the count values.
Since the circuit configuration is simple, the ratio of the area of the self-test circuit to the circuit under test 5 built in the IC device can be reduced.

FIG. 2 is a block diagram showing a self-test circuit according to the second embodiment of the present invention. In this embodiment, the structure of the data comparison circuit 1 in the first embodiment is different and the comparison data 2 is not necessary. Therefore, in FIG. 2, the same parts as those in FIG. Detailed description of the parts is omitted.

In the first embodiment, the EXOR gate is used for data comparison, but in the second embodiment, the data comparison circuit 1 includes the comparison data. That is, the same data as the test input data 7 to the circuit under test 5 is input to the data comparison circuit 1. The NMOS transistors 11 and 17 are connected in series between the ground terminal and the output end of the test end signal 3. The clock signal 15 is input to the gate of the NMOS transistor 17.
If the bit of the last data (data to be stored in the comparison data 2 in the first embodiment) of the data sequence generated by the LFSR4 is 1, the output terminal of the LFSR 4 and the NMOS.
An inverter 14 is connected in series with the gate of the transistor 11, and if the last data bit is 0, LFS is set.
The output end of R4 and the gate of the NMOS transistor 11 are directly connected. The PMOS transistor 12 is connected between the power supply terminal and the output end of the test end signal 3,
The clock signal 13 is input to the gate.

In the self-test circuit configured as described above, when the last data of the data series generated by the LFSR 4 is input to the data comparison circuit 1, it is synonymous with that data comparison is performed. 3 can be generated. That is, if the data match, the test end signal 3 becomes “1” based on the clock signal 15, and if the data does not match, the test end signal 3 becomes “0” based on the clock signal 15. In addition, NMO
The S-transistor 17 is in an off state while the test end signal 3 is precharged through the PMOS transistor 12 based on the clock signal 13, and becomes active only at the timing of the clock signal 15. Therefore, the test end signal 3 is valid only at the timing of the clock signal 15.

According to this embodiment, the number of circuits in the data comparison circuit 1 is extremely small, and the number of gates can be reduced to about 50% or less of the case where a counter is used. For this reason,
The ratio of the area of the self-test circuit to the circuit under test 5 built in the IC device can be reduced.

[0017]

As described above, according to the present invention, the comparison means compares arbitrary data stored in the storage means with the input data to the circuit under test, and the braking means compares the comparison result of the comparison means. Since the operation of the linear feedback shift register and the signature register is stopped based on the above, the test execution can be automatically stopped.
The ratio of the area of the self-test circuit to the circuit under test built in the C device can be reduced as compared with the conventional case.

[Brief description of drawings]

FIG. 1 is a block diagram showing a self-test circuit according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a self-test circuit according to a second embodiment of the present invention.

[Explanation of symbols]

 1; data comparison circuit 2; comparison data 3; test end signal 4; linear feedback shift register (LFSR) 5; circuit under test 6; signature register (MISR) 7; test input data 8; test result data 9; EXOR gate 10 , 14; Inverter 11, 17; NMOS transistor 12; PMOS transistor 13, 15; Clock signal 16; OR gate

Claims (1)

[Claims] 1. A self-test comprising an n-bit (n; positive integer) linear feedback shift register for generating input data to a circuit under test, and a signature register for compressing output data of the circuit under test. In the circuit, a storage means for storing an i-th (i; positive integer of 1 to 2 ⁿ -1) arbitrary data in the data series up to the longest period (2 ⁿ -1) of the input data; Comparing means for comparing arbitrary data with the input data,
A self-test circuit comprising: a braking means for stopping the operations of the linear feedback shift register and the signature register based on a comparison result of the comparison means.