KR100528450B1 - Synchronous memory device - Google Patents

Abstract

The synchronous memory device according to the present invention provides a second address counter and a comparison circuit, which second latches the last column address of the burst length in advance. The comparison circuit compares the burst column address sequentially counted with an externally input column address and a column address latched by the second address counter to generate a comparison signal when the two addresses match. . Finally, the burst stop signal generator receiving the comparison signal generates a burst stop signal to deactivate the first and second address counters. This eliminates the need for the counter to operate every clock, thus reducing current consumption.

Description

Synchronous Memory Device {SYNCHRONOUS MEMORY DEVICE}

The present invention relates to a semiconductor memory device, and more particularly, to a synchronous memory device capable of burst operation.

In a semiconductor memory device, particularly a dynamic random access memory (DRAM) device, a clock, which is information outside the DRAM, is used as a synchronous signal to improve the operation speed during continuous data fetch. In a synchronous DRAM for transmitting, one memory cell is selected by an arbitrary column address while one word line is activated by an arbitrary row address, and data is written to / from the selected memory cell. / Will be read.

In this case, when data is continuously read / written by a predetermined burst length (BL), an externally input column address CAi (where i is a positive integer) corresponds to one burst length. The corresponding data is read / written from / to a memory cell selected by each burst column address while continuously increasing the column address.

Here, the burst length (BL) is determined by a Mode Register Set (MRS) which is well known to those who have acquired the general knowledge in this field, and BL = 1, 2, 4, 8, and Full can be set. Do. In order to sequentially increase the column address CAi in synchronization with every clock, there must be an internal counter for counting the burst length BL.

1 is a block diagram illustrating a configuration of a synchronous memory device according to the prior art.

Referring to FIG. 1, a synchronous memory device includes a column address buffer circuit 100, an address counter 120, a column address decoder 140, a burst length counter 160, and a burst stop signal generator 180. The column address buffer 100 receives an address Ai, a column address strobe signal CASB, and a clock signal CLOCK, and outputs a column address CAi. The address counter 120 sequentially counts the column address CAi as the burst column address CAj using the column address CAi as an initial input value, and the counted column address CAj is again an address counter. It becomes input of (CAj).

This sequential operation continues until the burst stop signal BS generated by the burst stop signal generator 180 is delivered. The burst length counter 160 uses the column address strobe signal CASB and the clock signal CLOCK as external inputs, and the burst stop signal generated by inputting the BL information generated by the MRS and the output of the burst length counter ( Deactivated by BS).

According to the prior art as described above, in order to increase the column address by the burst length BL by using an externally input arbitrary column address CAi as an initial value, the burst length counter 160 for detecting the burst length is provided. It must exist. In addition, since the counter 160 must operate synchronously every clock, the counter 160 continuously consumes a certain amount of current (for example, an amount corresponding to the burst length).

It is therefore an object of the present invention to provide a synchronous memory device capable of reducing the current consumed during a burst operation.

(Configuration)

According to one aspect of the present invention for achieving the above object, a synchronous dynamic random access memory device performing a burst operation in synchronization with a clock signal, comprising: a column address buffer circuit for receiving a column address from the outside; ; A column address counter for sequentially counting the column address in accordance with the clock signal in response to a column address provided from the column address buffer circuit during the burst operation; Means for lowering a column address provided from said column address buffer circuit to a column address corresponding to a burst length and maintaining said downed column address during said burst operation; A comparator for outputting a comparison signal comparing the column address counter and the output of the means; Generating a burst stop signal for stopping the burst operation in response to the comparison signal output from the comparator, generating the burst stop signal when the output of the column address counter and the output of the means are the same; And a burst stop signal generation circuit for deactivating the column address counter.

In this embodiment, the means comprises a down counter for one bit down the column address provided from the column address buffer.

In this embodiment, the down counter is operated on the clock signal but counts only once on the first clock signal to which the column address is input.

According to another aspect of the present invention, a synchronous dynamic random access memory device which performs a burst operation in synchronization with a clock signal, comprising: a column address buffer circuit for receiving a column address from the outside; A first address counter for sequentially counting the column address in accordance with the clock signal in response to a column address provided from the column address buffer circuit during the burst operation; During the burst operation, a second address counter for lowering a column address provided from the column address buffer circuit to a column address corresponding to a burst length and holding the downed column address; Means for accepting the outputs of the first and second column address counters and generating a burst stop signal to deactivate the first and second column address counters when the two outputs match.

In this embodiment, the means comprises: comparing circuitry for accepting the outputs of the first and second column address counters and for comparing the two outputs; The comparison circuit generates a comparison signal when the two outputs match; And a burst stop signal generation circuit for generating the burst stop signal for stopping the burst operation in response to the comparison signal generated from the comparison circuit.

In this embodiment, the second column address counter includes a down counter for one bit down the column address provided from the column address buffer.

(Action)

Such an apparatus can generate a burst stop signal for latching the last address of the burst column address generated by the address counter and deactivating the address counter when the latched address and the burst column address coincide.

(Example)

Hereinafter, the present invention will be described in detail with reference to FIG. 2. In FIG. 2, the same reference numerals are given together about the components which have the same function as the component of FIG.

In the following description, specific details are set forth by way of example and in detail in order to provide a more thorough understanding of the present invention. However, for those skilled in the art, the present invention may be practiced only by the above description without these details.

Referring to FIG. 2, the novel synchronous memory device of the present invention provides a second address counter 200 and a comparison circuit 220, the second address counter 200 being the last column address (CAk) of burst length. ), Where k is a positive integer. In addition, the comparison circuit 220 may sequentially count the burst column address CAj and the column address CAk latched by the second address counter 200 using the externally input column address CAi as an initial value. Is compared to generate a comparison signal COMP when the two addresses CAj and CAk coincide. Finally, the burst stop signal generator 180 receiving the comparison signal COMP generates the burst stop signal BS to deactivate the first and second address counters 120 and 200. This eliminates the need for the counter to operate every clock, thus reducing current consumption.

Referring back to FIG. 2, there is shown a block diagram showing the configuration of a synchronous memory device according to the present invention. The synchronous memory device of the present invention includes a column address buffer circuit 100, a first address counter 120, a column address decoding circuit 140, and a burst. A stop stop signal generating circuit 180, a second address counter 200, and a comparison circuit 220.

The configuration of the present invention can be largely divided into three parts. First, the column address buffer 횔 100 is formed by an externally input column address strobe signal CASB, a clock signal CLOCK, and a column address Ai. In synchronization with the clock signal, an address is input to generate an arbitrary column address CAi. The first and second address counters 120 and 200 input CAi as an output of the column address buffer circuit 100 to count the column addresses CAi, respectively. The comparison circuit 220 detects the burst length by comparing the two column addresses CAj and CAk counted by the counters 120 and 200. Here, the first address counter 120 is an increment counter and the second address counter 200 is configured as a down counter.

The column address CAi generated by the external address Ai by the column address buffer circuit 100 is inputted to the first address counter 120 and the second address counter 200 of the address counter as counter initial values, respectively, to the clock. In synchronization, the address is incremented by one bit for every clock, and this operation must proceed by the burst length. The column address CAi input to the second address counter 200 outputs an address CAk having a decrease of 1 bit, and the address CAk is a burst length BL with the column address CAi as an initial value. It becomes the same as the last address when the address is increased. The second address counter 200 does not need to operate every clock, but only once and latches the reduced address CAk.

The comparison circuit 220 generates an address CAj generated by the second address counter 200 and increased by 1 bit for every clock by the latched address CAk and the first address counter 120. When the addresses generated by the first address counter 120 continue to increase while matching with the addresses generated by the second address counter 200 and latched, the burst stop signal BS bursts. Is generated from the signal generator 180. The burst stop signal BS deactivates the first and second address counters 120 and 200, thereby ending the burst operation.

According to the present invention described above, the burst stop signal (when the last address of the burst length is pre-latched and compared with the outputs CAj and CAk through the address counters 120 and 200 is matched. By generating the BS, the burst operation is completed, which eliminates the need for the counter to run every clock, thus reducing current consumption.

In the above, the configuration and operation of the circuit according to the present invention are shown in accordance with the above description and drawings, but this is merely an example, and various changes and modifications can be made without departing from the spirit and scope of the present invention. Of course.

As described above, it is possible to reduce the amount of current consumed while the burst operation is performed.

1 is a block diagram showing a configuration of a synchronous memory device according to the prior art;

2 is a block diagram showing a configuration of a synchronous memory device according to the present invention;

* Explanation of symbols on the main parts of the drawings

100: column address buffer 120: address counter

140: column address decoder 160: burst length counter

180: burst stop signal generator 200: second address counter

220: comparator

Claims (6)

A synchronous dynamic random access memory device which performs a burst operation in synchronization with a clock signal, A column address buffer; A column address counter for sequentially counting the column address in accordance with the clock signal in response to a column address provided from the column address buffer during the burst operation; Means for lowering a column address provided from the column address buffer to a column address corresponding to a burst length and maintaining the downd column address during the burst operation; A comparator for outputting a comparison signal comparing the column address counter and the output of the means; Generating a burst stop signal for stopping the burst operation in response to the comparison signal output from the comparator, generating the burst stop signal when the output of the column address counter and the output of the means are the same; And a burst stop signal generation circuit for deactivating the column address counter. The method of claim 1, And said means comprises a down counter for one bit down a column address provided from said column address buffer. The method of claim 2, And said down counter operates on said clock signal but counts only once by said first clock signal to which said column address is input. A synchronous dynamic random access memory device which performs a burst operation in synchronization with a clock signal, A column address buffer; A first address counter for sequentially counting the column address in accordance with the clock signal in response to a column address provided from the column address buffer during the burst operation; During the burst operation, a second address counter for lowering a column address provided from the column address buffer to a column address corresponding to a burst length and maintaining the downd column address; Means for accepting the outputs of the first and second column address counters and generating a burst stop signal to deactivate the first and second column address counters when the two outputs match. Memory device. The method of claim 4, wherein The means for receiving an output of the first and second column address counters and for comparing the two outputs; The comparison circuit generates a comparison signal when the two outputs match; And a burst stop signal generation circuit for generating the burst stop signal for stopping the burst operation in response to the comparison signal generated from the comparison circuit. The method of claim 5, And the second column address counter comprises a down counter for one-bit down the column address provided from the column address buffer.

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