JPH0560135B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to an input circuit for a plurality of asynchronous signals and a processing device using the same. The present invention relates to an asynchronous signal input circuit suitable for inputting a generated interrupt request signal and a processing device using the same.

[Background of the invention]

A conventional example of a logic device that activates internal processing using a combination of multiple asynchronous signals is the 16-bit microcomputer MC68000 manufactured by Motorola, USA. This microcomputer is designed to receive signals DTACK and BERR given from an external storage device to report the completion of asynchronous bus transfer. The input circuit of this microcomputer can receive only one of the signals DTACK and BERR at the same time. That is, the signal when finished successfully
DTACK is asserted, and signal BERR is asserted in case of abnormal termination (bus error). Now, if the external storage device reports a bus error, signal BERR is asserted before asserting signal DTACK.
needs to be asserted. Therefore, it is necessary to confirm that there is no bus error before DTACK.
Unable to assert pin.

Furthermore, as this type of input circuit, U.S. Patent No.
There is a circuit shown in FIG. 11 of No. 4349873.

Therefore, it may be desirable to output the signal DTACK first and output the signal BERR later.
Furthermore, in general, even if a plurality of signals are supplied to a microcomputer at the same time, due to circuit variations, the plurality of signals may actually be generated with a slight time lag.
Therefore, it is considered desirable for a microcomputer that receives these signals to be able to receive them in such a way that even if multiple signals are applied asynchronously to the microcomputer's clock, they can be detected correctly. . Furthermore, it is desirable that accurate detection be possible in the same way even when only one of the signals is provided, as in the prior art.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a processing device that can process a plurality of asynchronously applied signals even if the signals are applied with a time lag.

[Summary of the invention]

A processing device according to an exemplary embodiment of the present invention includes a first latching means 101 and a second latching means 1.
The first latch means 101, the second latch means 102, the third latch means 103, and the fourth latch means 104 are connected to each other. Each of the latch means 104 of 4 has a signal input terminal D, a signal output terminal Q, and a control input terminal C, and when the control input terminal C is in a first state, the signal of the signal input terminal D is transferred to the signal output terminal. Q, each of which is configured to hold the signal at the signal output terminal Q when the control input terminal C is in a second state different from the first state, indicating that the data transfer has ended abnormally; The first latch means 101 outputs the first signal BERR which is an error signal.
A first clock signal φ 1 is applied to the signal input terminal D of the first latch means 101, a first clock signal φ ₁ is applied to the control input terminal C of the first latch means 101, and the signal output terminal Q of the first latch means 101 is A second clock signal φ ₂ different from the first clock signal φ ₁ is applied to the control input terminal C of the second latching means 102 . , the second above
The signal output terminal Q of the latch means 102 is connected to the signal input terminal D of the third latch means 103, and the first clock signal φ ₁ is connected to the control input terminal C of the third latch means 103. The third latch means 1 is applied with an inverted signal of
03 is connected to the signal input terminal D of the fourth latch means 104, and the control input terminal C of the fourth latch means 104 is connected to the signal output terminal Q of the fourth latch means 104.
a first detection method for applying an inverted signal of the second clock signal φ ₂ to the fourth latch means 104, and outputting a detection output signal indicating the presence or absence of input of the first signal BERR from the signal output terminal Q of the fourth latch means 104; means 100
and a fifth latch means 121, a sixth latch means 122, a seventh latch means 123, and an eighth latch means 124, the number of which is equal to the number of slave connections of the latch means of the first detection means 100. The fifth latch means 121, the sixth latch means 122, the seventh latch means 123, and the eighth latch means 124 have a signal input terminal D and a signal output terminal, respectively. Q and a control input terminal C, and when the control input terminal C is in the first state, the signal input terminal D
data indicating that the data transfer has been completed; The second signal DTACK, which is a transfer acknowledge signal, is applied to the signal input terminal D of the fifth latch means 121.
and the first clock signal φ ₁ is applied to the control input terminal C of the fifth latch means 121.
is applied to the signal output terminal Q of the fifth latch means 121 to the sixth latch means 122.
The second clock signal φ ₂ is applied to the control input terminal C of the sixth latch means 122, and the signal output terminal Q of the sixth latch means 122 is connected to the signal input terminal D of the sixth latch means 122. The clock is connected to the signal input terminal D of the seventh latch means 123, and an inverted signal of the first clock signal _φ1 is applied to the control input terminal C of the seventh latch means 123. Latch means 12
The signal output terminal Q of No. 3 is connected to the signal input terminal D of the eighth latch means 124, and the inverted signal of the second clock signal φ ₂ is connected to the control input terminal C of the eighth latch means 124. a second detection means 120 which outputs a detection output signal indicating the presence or absence of input of the second signal DTACK from the signal output terminal Q of the eighth latch means 124;
and at least constituted by a subordinate connection of a ninth latch means 112, a tenth latch means 113, and an eleventh latch means 114, each of which has a smaller number of subordinate connections than the number of subordinate connections of the latch means of the first detection means 100. The ninth latch means 112 and the tenth latch means 112
the latch means 113 and the eleventh latch means 11
4 are signal input terminal D and signal output terminal Q, respectively.
and a control input terminal C, the control input terminal C
transmits the signal at the signal input terminal D to the signal output terminal Q when is in the first state, and holds the signal at the signal output terminal Q when the control input terminal C is in the second state. is configured, and the first signal BERR is connected to the ninth latch means 11.
The signal is applied to the signal input terminal D of No. 2, and the signal is applied to the signal input terminal D of No.
The second clock signal φ ₂ is applied to the control input terminal C of the latch means 112 of the ninth clock.
The signal output terminal Q of the latch means 112 is connected to the signal input terminal D of the tenth latch means 113, and the first clock signal φ 1 is connected to the control input terminal C of the tenth latch means ₁₁₃ . applying an inverted signal to the tenth latch means 1.
The signal output terminal Q of No. 13 is connected to the signal input terminal D of the eleventh latch means 114, and the control input terminal C of the eleventh latch means 114 is connected to the signal output terminal Q of the eleventh latch means 114.
a third detection method for applying an inverted signal of the second clock signal φ ₂ to the signal output terminal Q of the eleventh latch means 114 to output a detection output signal indicating the presence or absence of the input of the first signal BERR; Means 110
and a first circuit means 161 for obtaining an OR signal of the detection output of the first detection means 100 and the detection output of the second detection means 120, and the detection output of the third detection means 110 and the above. a second circuit means 162 for obtaining an AND signal with the output of the first circuit means 161, extracting the bus cycle end signal 431 from the output of the first circuit means 161, It is characterized in that a bus cycle retry signal 433 is extracted from the output of the circuit means 162.

As a result, the first signal BERR indicating a bus error
and a second signal indicating a data transfer acknowledgement.
DTACK, whichever is input first, the presence of the signal input first is detected by the first detection means 100 or the second detection means 120,
The logical sum of the first circuit means 161 allows the bus cycle end signal 431 to be output.

Further, when the first signal BERR indicating a bus error is input, the input of the first signal BERR is detected at high speed by the third detection means 110 having a small number of cascade connections of latch means. On the other hand, after the bus cycle end signal 431 is output from the first circuit means 161 as described above, the third detection means 11
Outputting a bus cycle retry signal 433 from the output of the second circuit means 162 which performs a logical product of the high speed detection output 135 of the first signal BERR of 0 and the bus cycle end signal 431 from the first circuit means 161. I can do it.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 is a system configuration diagram of a data processing device having an asynchronous transfer bus.

It consists of a processing device 400 and a storage device 500, both of which are connected via a bus 300.

The bus 600 is an asynchronous transfer bus, and includes an address signal 601 indicating the address of data to be accessed, and an address strobe signal (AS) 602 indicating that the address signal 601 indicates a valid value and a bus cycle is being executed. A data line 603 that transfers data and a data transfer acknowledge signal (DTACK) 6 that indicates that data transfer has completed normally.
04, and a bus error signal (BERR) 605 indicating that the transfer has ended abnormally.

The processing device 400 includes an instruction execution unit 410 that executes programs in synchronization with clocks φ ₁ , φ ₂ , ₁ , _{2 .}
and a bus control circuit 42 that controls the asynchronous transfer bus.
It consists of 0. The bus control circuit 420 outputs the address signal 601 and asserts the AS signal 602 to indicate the execution of a bus cycle, and the bus control signal output circuit 421 indicates the end of the asynchronous transfer.
An input circuit 422 receives the DTACK signal 604 and the BERR signal 605 in synchronization with the internal timing clock of the processing device 400, and outputs a bus cycle end signal 431 and a bus cycle retry signal 433 at the time of normal termination or abnormal termination. End detection circuit 4
It consists of 23. The storage device 500 includes a memory circuit 510 and a memory control circuit 5 that controls it.
It consists of 20 pieces.

FIG. 8 shows the internal circuit of the bus control signal output circuit 421. Latch 440 holds the address and read/write instruction signals to be accessed while processor 400 is using bus 600. The latch 440 is activated by the address 411 and the R/W signal 4 by the bus cycle start instruction signal 413.
12 and outputs an address 601 and an R/W signal 606. The flip-flop 441 is
Bus cycle start instruction 413 or retry instruction 4
33 is asserted, and the address strobe (AS) signal 602 is asserted. When the bus cycle end instruction 431 is asserted, it is reset and the AS signal 602 is negated. 443
is a delay circuit, and 442 is an OR circuit.

The internal circuit of memory control circuit 520 is shown in FIG. When the AS signal 602 indicating that a bus cycle is being executed is asserted, the memory control circuit 520 outputs a memory read instruction to the memory via the AND gate 522 if the read/write instruction signal R/W 606 is asserted (read mode). circuit 510
If the R/W signal 606 is negated, the memory write instruction is output to the AND gate 521.
The output signal is output to the memory circuit 510. On the other hand, the delay circuit DL524 delays the AS signal 602 by the time required to read or write data in the memory circuit and generates a data transfer completion report signal (DTACK).
Generate 4. AND circuit 525 connects data transfer end report signal (DTACK) 604 and memory circuit 51
The bus cycle abnormal end report signal (BERR) 6 is triggered by the parity error detection signal detected by 0.
Generate 05.

One bus cycle consists of an address strobe signal indicating that the address is being output validly.
It is defined by the period in which AS is asserted.
In other words, the start of a bus cycle is initiated by processor 400.
The processor 400 reports the end of the bus cycle to the memory control circuit 520 by asserting the address strobe AS, and the processor 400 receives the end report signal DTACK signal as a response signal from the memory control circuit 520, thereby asserting the address strobe signal AS. Negate and display.

Here, when a bus cycle ends abnormally, it is possible to retry the bus cycle.
That is, the transfer end detection circuit 423 first
When the input circuit 422 detects the assertion of at least one of the DTACK signal and the BERR signal, it outputs a bus cycle end instruction 431 to the bus control signal output circuit 421, and outputs the address strobe signal.
Negate AS to complete the current bus cycle, then scan whether the input circuit 423 detects the BERR signal again, determine whether the termination is normal or abnormal, and terminate normally. In this case, a normal completion signal 432 is sent to the instruction execution unit 410,
If the abnormal termination occurs, a retry signal 433 is sent to the bus control signal output circuit 4 in order to retry the same bus cycle as the one that terminated due to the abnormal termination.
21, and causes the signal AS to be output again.

Next, the operation of the asynchronous transfer bus of this embodiment will be explained in detail.

FIG. 3 is a time chart showing the operation of the bus signals when the transfer of data read from the storage device 500 is normally completed. First, the instruction execution unit 410 receives the address 411 and the read/write identification signal (R/
W) 412, and bus cycle start instruction signal 41
Outputs 3. Bus control signal output circuit 421 outputs address signal 601. After the address 601 is determined, the AS signal 602 is asserted to indicate the execution of the bus cycle. The storage device 500 reads the corresponding data from the memory circuit 501 and outputs it to the read data line 603. On the other hand, the memory control circuit 52
0 asserts DTACK 604 as a reservation signal without waiting for data 603 to be finalized. Thereafter, the value of the data 603 is determined, it is confirmed that there is no abnormality such as a parity error, and the BERR signal 605 is negated to report that the transfer has completed normally.
The input circuit 422 receives this DTACK signal 604, outputs the bus cycle end instruction signal 431 from the end detection circuit 423, and outputs the bus cycle end instruction signal 431 to the bus control signal output circuit 4.
The AS signal 602 and address signal 601 of 21 are sequentially negated. On the other hand, a normal completion report 432 is output to the instruction execution unit 410.

Next, with reference to FIG. 4, the operation when an abnormality occurs in the transfer of reading data from the storage device 500 will be described. The process up to the point where the corresponding data is read from the memory circuit 501 and outputted to the read data line 603 is the same as in the normal transfer described above. At this time, it is assumed that a parity error is detected in the memory circuit 501. The memory control circuit 502
The BERR signal 605 is asserted to report to the processing device 400 that an abnormality has occurred during transfer. Input circuit 422 receives this BERR signal 605 and outputs bus cycle end instruction signal 431 and bus cycle retry instruction signal 433. The bus control signal output circuit 421 outputs a retry instruction signal 4.
33, the transfer is started again using the same address as in the previous bus cycle, and the bus cycle is retried.

FIG. 1 is a concrete logic diagram of a response signal input circuit 422 and an end detection circuit 423 for reporting the end of transfer on the asynchronous transfer bus. When the transfer ends normally, the DTACK signal 604 is asserted, and when the transfer ends abnormally, the BERR signal 605 is asserted. Also, DTACK signal 604 and BERR
If the signal 605 is asserted at the same time, the process ends abnormally. The input circuit 422 has three input circuits 1
It consists of 00, 110, 120. Input circuit 100
samples the signal input from the BERR input terminal 140 at the tailing edge of clock _φ1 ,
This is an asynchronous signal synchronization input circuit that outputs an internal signal that becomes valid at the tailing edge of _φ2 . Similarly, the input circuit 120 is a circuit that synchronizes and inputs the asynchronous signal input from the DTACK input terminal 150. This circuit is the same as the one disclosed in the patent application filed on December 26, 1980, ``Asynchronous Signal Synchronization Circuit.'' Input circuit 110 is BERR input terminal 1
This is a synchronous signal input circuit which regards the signal input from 40 as a synchronous signal and samples it at the tailing edge of clock _φ2 . Further, the end report detection circuit 423 detects the end of the bus cycle according to the states of the output signals of the input circuits 100, 110, and 120.
and a normal transfer end 432 bus retry 433 is output.

Block 101, 102, 103, 104, 1
12, 113, 114, 121, 122, 12
3,124 is a flip-flop with control signal input C
It is a latch means that transmits input data D to an output terminal Q when is asserted, and holds and outputs an output signal Q when it is negated. FIG. 5 shows an example of the configuration of these flip-flops.
The logic gate 200 outputs an inverted signal of the input signal D when the control signal C is asserted, and the output becomes a high impedance state when the control signal C is negated. Also,
Conversely, when the control signal C is negated, the logic gate 201 outputs an inverted signal of the output signal Q of the flip-flop 100, and when asserted, the output becomes a high impedance state. The above two types of logic gates 200 and 210 and the inverter 220 are connected to the fifth
When connected as shown in the figure, a flip-flop 230 which latches input data D by control signal C can be constructed.

FIG. 6 shows an example of the circuit configuration of flip-flop 230. Circuit elements 301, 302, 311,
312 and 321 are P channel MOSFETs,
Circuit elements 303, 304, 313, 314, 32
2 is an N-channel MOSFET. MOSFET3
01, 302, 303, 304 constitute the logic gate 200 in FIG.
Similarly, 312, 313, 314 are logic gates 21
It constitutes 0. Also, MOSFET321,3
22 constitutes an inverter 220. The operation of flip-flop 100 will be explained using FIG. First, when the control signal C is asserted (High), the circuit elements 302 and 303 are turned on, and the logic gate 200 functions like an inverter and outputs an inverted signal of the input signal D. On the other hand, since the circuit elements 312 and 313 of the logic gate 210 are in the OFF state, the output is high impedance. Therefore, the signal line 330 becomes an inverted signal of the input signal D, is inverted again by the inverter 220, and transmits the input signal D to the output terminal Q.

Next, when the control signal C is negated (low), the circuit elements 302 and 303 are turned off, and the output becomes high impedance. On the other hand, logic gate 2
10, circuit elements 312 and 313 are turned on and function in the same way as an inverter, outputting an inverted signal of the output signal Q. Therefore, the signal line 330 becomes an inverted signal of the output signal Q, which is inverted again by the inverter 220, outputs the output signal Q, and maintains its value.

The above is a description of the flip-flop 230.
Next, the operation of the asynchronous signal input circuit 120 shown in FIG. 1 will be explained using the time chart shown in FIG. 7. An input signal 151 inputted from the DTACK input terminal 150 is latched into the flip-flop 121 by the timing clock _φ1 , and a signal 152 is output. Since the flip-flop 121 passes through the signal 152 while the clock φ ₁ is high, the output value during this period varies depending on the input signal 151 and is undefined. Signal 152 is relatched to flip-flop 122 by timing clock φ ₂ which is 90° out of phase with clock φ ₁ and outputs signal 153 . The output signal 154 obtained by latching this signal 153 by the inverted signal of the clock _φ1 becomes a signal that holds its value for one cycle of the clock _φ1 , as shown in the time chart. However, signal 154
is unstable at the tailing edge of clock φ ₁ . In other words, since there is a gate delay due to the flip-flops 122 and 123 in the second and third stages, the signal ₁ at the tailing edge of the clock φ1
This is because even if 52 is determined, it takes time until the signal 154 is determined.

Therefore, when the signal 154 is latched again with the inverted signal of the clock φ ₂ , the output signal 155 retains its value for one cycle of the clock φ ₂ and becomes valid from the tailing edge of the clock φ ₂ , as shown in the time chart. It is possible to output a value.

As explained above, block 120 can sample an asynchronous signal on the tailing edge of clock φ ₁ and enable an internal signal on the tailing edge of clock φ ₂ . In other words,
Synchronize asynchronous signals in 1/4 of a clock cycle
It can be done in an amount of time.

Next, the synchronization signal input circuit 110 will be explained. Input circuit 110 includes flip-flops 112 and 11 that respond to clock φ ₂ , an inverted clock of clock φ ₁ , and an inverted clock of clock φ ₂ , respectively.
3,114, and an input circuit 120
Similar to signal 154 in _FIG . Here, if the input signal 141 is a synchronization signal having a value determined at the tailing edge of the clock φ ₂ , the input circuit 110 inputs a synchronization signal that outputs a value valid for one cycle from the tailing edge of the clock φ ₂ to the output line 135 . It becomes a circuit.

In other words, it stipulates that the skew of each input signal is within the phase difference between clocks φ ₁ and φ ₂ , and as described later, the input data sampled by clock φ ₂ is input when the input data sampled by clock φ ₁ is asserted. If it is treated as a signal that is valid only for , then sampling by clock φ ₂ can be regarded as sampling for a synchronous signal. Therefore, the input circuit 110 is a first input circuit 100 or 12 for sampling an asynchronous signal.
Compared to 0, a simple circuit with a small circuit scale (in this example, there is one less flip-flop) is sufficient;
Moreover, since there is no time delay required for synchronization, effective signals can be extracted at high speed.

On the other hand, the logic circuit 423 uses a signal 145 obtained by sampling the BERR input 141 at the tailing edge of φ ₁ , a signal 135 sampled at the tailing edge of φ ₂ , and a signal 155 obtained by sampling the DTACK input 151 at the tailing edge of φ ₁ to determine the end of the asynchronous bus transfer. This is a circuit that determines OK/NG. That is, DTACK input 151 or
When the BERR input 141 is asserted, the bus cycle end instruction signal 431 is connected to the detection signal 145 and 1
55 is input, orage art 161 outputs,
When signal 431 is asserted and BERR input 141 is negated, signal 431
A flip-flop 168 (which has the same structure as other flip-flops) latches the output of the AND gate ₁₆₂ to which the inverted signal of 435 and the signal 135 are input, and outputs the normal completion report signal 432.
output, and when BERR input 141 is asserted with signal 431 asserted,
AND gate 1 to which signals 431 and 135 are input
A flip-flop 167 which latches the output of 62 with clock φ ₂ outputs a retry instruction signal 433.

According to the above embodiment, when a bus error occurs,
Even if the BERR signal 605 is asserted at the same time as the DTACK signal 604, it is possible to reliably detect a bus error. Furthermore, as shown in FIG. 7, if the phase difference between clocks φ ₁ and φ ₂ is within the range,
Even if the BERR signal 605 is asserted later than the DTACK signal 604, it is possible to reliably detect a bus error.

Therefore, the memory control circuit 520 receives the DTACK signal 6.
04 can be used as a transfer end reservation signal and can be responded to before the data 603 is finalized, so one bus cycle can be completed in a short time.
Bus throughput can be improved.

Furthermore, the memory control circuit 520 of this embodiment
A circuit system that does not output the DTACK signal 604 as a reserved signal in advance, that is, in the event of an abnormal termination.
Even if the system outputs only the BERR signal 605, if the input system of the present invention is used, it is possible to correctly synchronize the BERR signal 605 with a tailing edge of ₁ and accept a bus error, as shown in FIG. At this time, the input circuit 422 and completion report detection circuit 423 can use the circuit shown in FIG.
It can be used for general purpose regardless of the response method of 5.

In this embodiment, a termination report input circuit for an asynchronous transfer bus has been described, but the present invention can also be applied to other input circuits encoded by priority, such as an interrupt request input circuit.

FIG. 11 is an example of an input circuit that synchronizes and receives input encoded into 3 bits. Signal lines 701, 702, 703 are input signals, signal line 72
1,722,723 are inputs 701, 70 respectively
2,703 is a synchronization signal that is sampled at the tailing edge of clock _φ1 and becomes a valid value at the leading edge of clock _2. Blocks 711, 712, and 713 are the synchronization circuits, and are similar to block 100 in FIG. They have the same configuration. signal 7
41, 742, 743 are inputs 701, 702, 7
03 is sampled at the tailing edge of φ ₂ and becomes a valid value from the leading edge of φ ₂ . Blocks 731, 732, and 733 are its input circuits, which are the same as block 110 in FIG. Signals 721 to 723 are logically summed by OR gate 770, and the result is output to AND gates 781 to 781, each of which receives signals 741 to 743 as the other input.
783 is given as one input. The outputs of AND gates 781-783 are latched by flip-flops 761-763, respectively, in synchronization with clock _φ1 . Signal 751, 752, 753
is the output result of synchronizing the 3-bit encoded signal and is processed by a device not shown. Flip-flops 761, 762, and 763 are latches of the same construction as flip-flop 230 of the previous embodiment.

An example of the operation of this input circuit is shown in a time chart in FIG. Input 701 at the tailing edge of _φ1 ,
When all the outputs 702 and 703 are negated, the outputs 751, 752, and 753 are all negated even if the input 701 is asserted at the tailing edge of φ ₂ . On the other hand, input 701 at the tailing edge of φ ₁ ,
If any one of 702 and 703 is asserted, the input signal is sampled again at the tailing edge of _φ2 and the result is output 75.
Output to 1,752,753.

For example, in a processing device that inputs a 7-level interrupt request as three encoded signals, if this input circuit is used, even if the interrupt request is input asynchronously to the timing clock inside the processing device, the clock φ ₁ and the period of phase shift of φ ₂ ,
Since skew in the input signal can be tolerated, the encoded signal can be captured accurately.

Note that without using the method of the present invention, the input circuit 71
If the above input signals are synchronized with only 1,712,713, the signals 721, 722, 7 in FIG.
23, it is clear that in the second machine cycle, values different from those of the inputs 701, 702, and 703 are used as the synchronization signal. Therefore, three input signals 701, 702, 70
3 cannot be input as a completely asynchronous signal. Note that the output of the OR gate 770 is also input to the input 70.
It can be used by a device (not shown) as a signal indicating that 1 to 703 have been input.

〔Effect of the invention〕

According to the invention, the first signal indicating a bus error
Even if either BERR or the second signal DTACK indicating the data transfer acknowledgement is input first, the first
detection means 100 or second detection means 120
The presence of the previously input signal is detected by the first circuit means 161, and the bus cycle end signal 431 can be outputted by the logical sum of the first circuit means 161.

Further, when the first signal BERR indicating a bus error is input, the input of the first signal BERR is detected at high speed by the third detection means 110 having a small number of cascade connections of latch means. On the other hand, after the bus cycle end signal 431 is output from the first circuit means 161 as described above, the third detection means 11
Outputting a bus cycle retry signal 433 from the output of the second circuit means 162 which performs a logical product of the high speed detection output 135 of the first signal BERR of 0 and the bus cycle end signal 431 from the first circuit means 161. I can do it.

[Brief explanation of the drawing]

Figure 1 is a logic diagram of the asynchronous transfer bus termination report signal input circuit, Figure 2 is a system configuration diagram with an asynchronous transfer bus, and Figure 3 is a diagram of when data transfer is performed normally in the system shown in Figure 2. Figure 4 is a time chart when data transfer ends abnormally, Figure 5 is a logic diagram of the flip-flop used in Figure 1, and Figure 6 is a circuit diagram of the flip-flop used in Figure 5. , Figure 7 is a time chart of the operation of the input circuit in Figure 1, Figure 8 is an example of the configuration of the bus control signal output circuit, Figure 9 is an example of the configuration of the memory control circuit, and Figure 10 is a time chart of the operation of the input circuit in Figure 1. An example of the operation of a system that responds to a signal alone,
FIG. 11 is an input circuit that receives three encoded asynchronous input signals, and FIG. 12 is a time chart showing an example of its operation. 100, 120...Asynchronous signal synchronization input circuit, 110...Synchronization signal input circuit, 140, 15
0...Input terminal, 160...End state determination circuit,
161,171,172,220...Inverter, 162,163...AND gate, 164...
...OR gate, 301, 302, 311, 31
2,321...P channel MOSFET, 303,
304, 313, 314, 322...N channel
MOSFET.

Claims (1)

[Claims] 1. A first latching means, a second latching means, and a third latching means.
The first latch means, the second latch means, the third latch means, and the fourth latch means each have a signal input terminal. has a signal output terminal and a control input terminal, and transmits a signal from the signal input terminal to the signal output terminal when the control input terminal is in the first state, and when the control input terminal is in the first state. Each of them is configured to hold the signal of the signal output terminal when in a different second state, and the first signal, which is a bus error signal indicating that the data transfer has ended abnormally, is transmitted to the first signal output terminal.
applying it to the signal input terminal of the latching means;
A first latching means is connected to the control input terminal of the first latching means.
applying a clock signal of said first latching means, said signal output terminal of said first latching means being connected to said signal input terminal of said second latching means, and said clock signal of said first latching means being applied to said control input terminal of said second latching means. applying a second clock signal different from the clock signal, connecting the signal output terminal of the second latching means to the signal input terminal of the third latching means, and controlling the control input of the third latching means. an inverted signal of the first clock signal is applied to a terminal, the signal output terminal of the third latch means is connected to the signal input terminal of the fourth latch means, and the signal output terminal of the third latch means is connected to the signal input terminal of the fourth latch means; a first detection means for applying an inverted signal of the second clock signal to a control input terminal and outputting a detection output signal indicating the presence or absence of input of the first signal from the signal output terminal of the fourth latch means; , at least by the cascade connections of the fifth latching means, the sixth latching means, the seventh latching means, and the eighth latching means, the number of cascading connections being equal to the number of cascading connections of the latching means of the first detection means. configured,
The fifth latch means, the sixth latch means, the seventh latch means, and the eighth latch means each have a signal input terminal, a signal output terminal, and a control input terminal, and the control input terminal is Each of them is configured to transmit the signal of the signal input terminal to the signal output terminal when the control input terminal is in the first state, and hold the signal of the signal output terminal when the control input terminal is in the second state. A second signal, which is a data transfer acknowledge signal indicating that the transfer has been completed, is applied to the signal input terminal of the fifth latch means, and the first clock signal is applied to the control input terminal of the fifth latch means. applying a signal, connecting the signal output terminal of the fifth latching means to the signal input terminal of the sixth latching means, and applying the second clock signal to the control input terminal of the sixth latching means. is applied, and the signal output terminal of the sixth latch means is connected to the seventh
connected to the signal input terminal of the latch means of
An inverted signal of the first clock signal is applied to the control input terminal of the seventh latch means, and the signal output terminal of the seventh latch means is connected to the signal input terminal of the eighth latch means. an inverted signal of the second clock signal is applied to the control input terminal of the eighth latch means, and a detection output of whether or not the second signal is input is output from the signal output terminal of the eighth latch means; a second detection means for outputting a signal, and a ninth latch means, a tenth latch means, and an eleventh latch means each having a smaller number of cascade connections than the number of cascade connections of the latching means of the first detection means. The ninth latching means, the tenth latching means, and the eleventh latching means each have a signal input terminal, a signal output terminal, and a control input terminal, and the control input terminal are each configured to transmit the signal at the signal input terminal to the signal output terminal when the control input terminal is in the first state, and to hold the signal at the signal output terminal when the control input terminal is in the second state; applying said first signal to said signal input terminal of said ninth latching means, applying said second clock signal to said control input terminal of said ninth latching means, and applying said second clock signal to said control input terminal of said ninth latching means; Connect the above signal output terminal to the above 10th
connected to the signal input terminal of the latch means of
An inverted signal of the first clock signal is applied to the control input terminal of the tenth latch means, and the signal output terminal of the tenth latch means is applied to the control input terminal of the tenth latch means.
the clock signal is connected to the signal input terminal of the eleventh latch means, an inverted signal of the second clock signal is applied to the control input terminal of the eleventh latch means, and the clock signal is connected to the signal output terminal of the eleventh latch means. a third detection means for outputting a detection output signal indicating whether or not the first signal is input; a first detection means for obtaining a logical sum signal of the detection output of the first detection means and the detection output of the second detection means; and second circuit means for obtaining an AND signal of the detection output of the third detection means and the output of the first circuit means, and an output of the first circuit means. A processing device characterized in that: a bus cycle end signal is extracted from the output of the second circuit means; and a bus cycle retry signal is extracted from the output of the second circuit means. 2. The processing device according to claim 1, wherein the first signal and the second signal are output from an external storage device. 3. The processing device according to claim 1 or 2, wherein the processing device is a microcomputer.