GB2225460A - Asynchronous interrupt arbitrator - Google Patents

Abstract

An asynchronous interrupt arbitrator buffers the occurrences of multiple interrupts so as to permit an asynchronous host to reliably determine which interrupt request lines have been activated. The technique responds to activities on any interrupt request line, but multiple requests on the same line between host responses may not be enumerated. An arbitration circuit and a buffering scheme eliminate the possibility of missed interrupt requests or erroneous multiple triggering of a single request event. In a particular embodiment, a source of interrupts is synchronized to a clock ICLK. The host processing element asynchronously responds to interrupt requests by sensing an interrupt request signal and then reading a status register 44, 46, 48 to identify the source of the interrupt request. <IMAGE>

Description

ASYCH?NOUS INTERRUPT ARFITkT Background of the Invention The present invention relates generally to peripheral circuits for use with a data-processing element, such as a microprocessor or microcomputer. More specifically, the invention relates to the processing of interrupt requests and host responses particularly in those applications in which the requests and responses could occur asynchronflusly.

Most computer systems are partitioned into subcircuits which are designed to perform specific tasks. These subcircuits are sometimes called peripheral circuits because they surround the central processing element. The peripheral circuits may have clocked operations which operate asychronously with respect to the central processor clock timing. Especially in these cases, an interrupt request by a peripheral device may be missed or erroneously sensed more than once because of the asynchronous nature of the response timing to the interrupt source timing.

It is an object of the present invention to provide an interrupt arbitrator that prevents these incorrect operations from occurring.

It is a further object of the invention to provide an interrupt arbitrator that operates in an asynchronous manner.

Summary of the Invention The present invention provides a reliable interface between the sources of interrupt requests and the asynchronous responses to those requests by a host processing element. An arbitration circuit and a buffering scheme eliminate the possibility of missed interrupt requests or erroneous multiple triggering of a single request event. In a particular embodiment of the invention, there is provided a source of interrupts synchronized to a clock. The host processing element asynchronously responds to interrupt requests by sensing an interrupt request signal and then reading a status register to identify the source of the interrupt request.

Brief Description of the Drawing To the accomplishment cf the.above and to such other objects as may hereinafter appear, the present invention relates to an asynchronous interrupt arbitrator substantially as defined in the appended claims and as described in the following specification, as considered with the accompanying drawing in which the single figure is a schematic diagram of an asynchronous interrupt arbitrator in accordance with the invention.

Detailed Description of the Drawing In the following description of the invention it will be understood that the computer system is intended to respond to interrupt requests from a peripheral circuit subsection.

Referring now specifically to the figure, there is shown an asynchronous interrupt arbitrator intended to be part of the interface between a host processing element and its peripheral subcircuits. The circuit schematically illustrated in the figure receives a plurality of interrupt request inputs at the three interrupt request input lines IREQO, IREQ1, and IREQ2. These signals are respectively applied to an input of OR gates 10, 12, and 14. A corresponding multiplicity of status outputs is produced at the three interrupt status output lines ISTATO, ISTAT1, and ISTAT2 and appear at the three-state output drivers 16, 18, and 20, respectively. A synchronizing clock ICLK is received from the peripheral subcircuit and is applied to the clock inputs of flip-flops 22, 24, 26, 28, 30, and 32.

An input RESET applied to NOR gate 34 and to flip-flop 30 is a high-active signal that initializes the state of the arbitrator circuit. Input STATRD applied to the clock input of flip-flop 36 and to drivers 16, 18, and 20 is a low-active signal that enables the ISTATO, ISTAT1, and ISTAT2 signals to be read by the host processorfollowing an interrupt signal on the INTERRUPT output. The output INTERRUPT developed at the output of OR gate 38 is active high whenever any of the interrupt status output registers holds an active high flag. The trailing (rising) edge of the STATRD input signals the end of the host's interrupt status read operation Rising-edge triggered flip-flops, 22, 24 and 26 form holding registers used to accumulate any activity on the interrupt request inputs.OR gates 10, 12, and 14 are the corresponding two-input positive-logic OR function gates that recirculate the active value of a holding latch back into the input so that prior requests are remembered as well as newly active requests. OR gate 34 is a two-input positive-logic NOR function gate that cot##nts the external RESET signal with the internally generated STST status strobe. When either signal is active high, the output of OR gate 34 - FLUSH - goes active low causing the interrupt request holding registers or flip-flops 22, 24, and 26 to be cleared. The q terminal of flip-flops 22, 24, and 26 are applied to the inputs of OR gate 40, which is a three-input, positive-logic OR function gate that detects activity on any of the interrupt request holding registers.The output of gate 40 - ACTIVE - is active high when any of the signals HOLDO, HOLD1, or HOLD2 are active high. The output of gate 40 is applied to an input of a NAND gate 42.

The q outputs of flip-flops 22, 24, and 26 are respectively connected to the d terminals of flip-flops 44, 46, and 48, which are rising-edge triggered flip-flops used to store the interrupt output status. These flip-flops are clocked by the status strobe STST and cleared by the low-active signal CLRSTN. The outputs of flip-flops 44, 46, and 48 are applied to the inputs of OR gate 38, which is a three-input, positive-logic OR function gate that detects activity on any of the interrupt status output registers.

The output of gate 38 - INTERRUPT - is active high when any of the signals ISR2, ISR1, or ISRO are active high. The q terminals of flip-flops 44, 46, and 48 are respectively applied to the output drivers 20, 18, and 16 which are used to gate the interrupt status output onto the host processor's data bus. The three-state output drivers 16, 18, 20 are all enabled by the lowactive state of the status read signal STATRD.

The rising-edge triggered flip-flop 36 is used to detect the trailing (rising) edge of the status read signal STATRD. It is cleared by the low-active signal CLRSTN. Rising-edge triggered flip-flops 28 and 30 are used to resynchronize the detected trailing edge of the STATRD signal so that metastable states are avoided. Flip-flops 28 and 30 are clocked by the ICLK input, and flip-flop 28 is cleared by the low-active signal CLRSTN. The input RESET is used to preset the state of flip-flop 30. Risingedge triggered flip-flop 32, which is used to hold the readiness state of the arbitrator, is clocked by ICLK and cleared by the low-active signal STSTN.

The q outputs of flip-flops 30 and 32 are applied to the inputs of a two-input, positive-logic OR function gate 50 that recirculates the ARMED state of flip-flop 32 back into the d input of that flip-flop. The output of OR gate 40 - ACTIVE - and the q output of flip-flop 32 are applied to the inputs of twoinput positive-logic OR function gate 52 that detects the unarmed and inactive status to complete the self-timed loop. The outputs of NAND gate 42 and OR gate 52 are applied respectively to the inputs of two-input positive-logic NAND function gates 54, 56 that together form a set-reset latch used in the selftiming circuit. Two-input positive-logic NAND function gate 42 combines the ARMED state of the arbitrator with the ACTIVE status of the request holding register to trigger the transfer of data from the holding registers to the interrupt status output registers.Positive-logic inverter 58 generates STSTN, which is the complement of the status strobe signal STST. The inverter 58 is used instead of the output of NAND gate 56 to ensure predictable behavior of the self-timed circuitry.

The trailing (rising) edge of the status read signal STATRD initiates a chain of events. First, the end of the status read operation indication is resynchronized and the interrupt status output registers are then cleared. On the next edge of ICLK, the interrupt response circuit is armed. If, or when, any of the interrupt holding registers contains an active flag, the current contents of the interrupt holding registers are transferred to the interrupt status output registers. Then the holding registers are cleared in preparation for any active interrupt requests on the next ICLK cycle.

The operation of the circuit of the invention as described above is now explained by taking the circuit through a typical sequence of events. After the circuit has been energized and the clock signal ICLK is toggling, the input signal RESET should be brought active high to initialize the state of the circuit. When RESET is high, the output of NOR gate 34 is forced high causing the three flip-flops, 22, 24 and 26, to be cleared to an inactive low output state.

For simplicity of description, it is assumed that the three interrupt request inputs IREQO, IREQ1, and IREQ2 are all inactive low. The high active RESET input also directly presets the output of flip-flop 30 such that node N13 at one input of OR gate 50 is high and signal CLRSTN is low. When CLRSTN is low, flipflops 36 and 28 are both cleared causing nodes Nll and N12, respectively, to go low. Again for simplicity, it is assumed that input status read signal STATRD is inactive high. Another consequence of CLRSTN being low is that the interrupt output status registers 48, 46, and 44 are all cleared to their inactive states causing ISRO, ISR1, and ISR2, respectively, to be inactive low.When ISRO, ISRI, and ISR2 are all inactive low, the output of OR gate 38 also goes inactive low signaling to the processor that there are no active interrupt requests pending.

Since node N13 is now high, the output of OR gate 50 HA is also high. The RESET signal needs to be active high for only a brief period of time sufficient for the four flip-flops 26, 24, 22, and 30 to respond. After the RESET signal returns to the low inactive state, the first rising edge of ICLK transfers the high signal HA from the d input of flip-flop 32 to the q output causing the ARMED SIGNAL to become high active. On the same rising edge, the q output of flip-flop 28, labeled N12, is transferred from the d input of flip-flop 30 to the q output, causing N13 to go low, and CLRSTN to go high inactive. When CLRSTN is high inactive, flip-flops 36 and 28 are released and ready to accept a STATRD edge sequence. While the q output of flip-flop 32 is high, the signal ARMED is active. The ARMED signal is recirculated through OR gate 50 back to the d input of flip-flop 32.Thus the circuit remains armed for interrupt activity.

Signals HOLDO, HOLD1, and HOLD2 will stay low inactive until there is activity on one of the inputs IREQO, IREQ1, or IREQ2.

While all three signals HOLDO, HOLD1, and HOLD2 are low, the output of OR gate 50 -- ACTIVE -- will also be low. With ARMED high and ACTIVE low, the output of NAND gate 42 --N17 -- will be high, and the output of OR gate 52 -- N18 -- will also be high.

To understand the remaining circuit operation, it is necessary to know the state of the bistable set-reset latch formed by the cross-coupled connections of NAND gates 54 and 56.

To determine the current state, each of the two possible initial states prior to or during the activity of the RESET signal can be assumed. For the first case, if N21 is low, the output of NAND gate 54 is forced high, which causes the output of NOR gate 34 to go low forcing all three flip-flops 26, 24, and 22 to go low.

These three signals being low causes the output of OR gate 40 also to be low. STST being high also causes the output of inverter 58 to be low, which forces flip-flop 32 to be asynchronously cleared, making the ARMED signal low. When the ACTIVE and ARMED signals are both low, the output of NAND gate 42 -- N17 -- must be high, and the output of OR gate 52 -- N18 -must be low. If N18 is low, then the output of NAND gate 56 must go high. Since N17 is already high, the output of NAND gate 54 goes low. With STST low, the output of NAND gate 56 -- N21 -- is maintained high, and STSTN also goes high. This is now a stable state that will not be disrupted until the output of NAND gate 42 goes low, which can only happen when both the ACTIVE and ARMED signals are high. Returning to the other case -- assuming that N21 started out high -- then STST must be either high or low.If STST is high, then FLUSH must be active and ACTIVE must therefore be low. STSTN must also be low active clearing flip-flop 32 and causing ARMED to be low. With ARMED and ACTIVE both low, N18 must be low, and N17 must be high. But if N17 and N21 are oth high, then STST must go low, which is a return to the stable case achieved before.

For the last situation, it is assumed that N21 is high and STST is low. For STST to be low, N17 must be high, which occurs when either ARMED or ACTIVE is low. This is a stable configuration so long as N17 remains high. Thus it is always known that after a RESET pulse and before any activity on IREQO, IREQ1, IREQ2, and STATRD, the state of the arbitrator must be ARMED active high, ACTIVE inactive low, STST inactive low, and INTERRUPT inactive low. All other initial state values are low including N11, N12, N13, HOLDO, HOLD1, HOLD2, ISRO, ISR1, and ISR2.

After initializatior > ,~one of the interrupt request inputs IREQO, IREQ1, or IREQ2 should eventually go active high. Let us assume that IREQ1 has gone high causing the output of OR gate 12 to go high. The next rising edge of ICLK clocks this value from the d input of flip-flop 24 to the q output causing the signal HOLD1 to go active high. As long as HOLD1 is high, the output of OR gate 12 will remain high and the event of IREQ1 going high will be remembered even if IREQ1 subsequently goes low. When HOLD1 goes high it causes ACTIVE to be active high. Since ARMED was already high from the initialization, the output of NAND gate 42 must go low, which causes STST to go high briefly.The rising edge of the STST signal clocks the data from the HOLDO, HOLD1, and HOLD2 signals into the interrupt output status latches 48, 46, and 44, respectivelj, where the values are now available as signals ISRO, ISR1, and ISR2, respectively. After the rising edge of STST, the output of NOR gate 34 goes low which clears all of the interrupt request holding flip-flops 26, 24, and 22. STST will stay active high until two events reach completion: ACTIVE must go low, and ARMED must also go low. ACTIVE will go low only after all of the interrupt holding latches 26, 24, and 22 are cleared so that the output of OR gate 40 will go low. ARMED will go low when the high active STST causes STSTN to go low active which clears flip-flop 32 causing ARMED to go low. Only when both of these signals are low will the output of OR gate 52 be low which will cause N21 to go high. N17 must now be high because both of its inputs are low. This means that the output of NAND gate 54 must now go low. This self-timed sequence applies as long as the rising edge of STST clocks the data into flip-flops 48, 46, and 44 before the signal FLUSH clears flipflops 26, 24, and 22. All flip-flops 32, 26, 24, and 22 are guaranteed to be cleared by the requirement that both ACTIVE and ARMED be low to complete the self-timed cycle.

While the INTERRUPT signal is active high, the interrupt holding registers are available to store any new request activity during the processor latency period. When the processor does sense the active INTERRUPT line, it should initiate an interrupt status read cycle by bringing STATRD low. This gates the contents of the interrupt output status register onto a data bus that can be read by the processor. After the processor has read the status to determine the cause(s) of the interrupt request, STATRD returns to its high inactive state. The trailing rising edge of STATRD is detected by flip-flop 36, which clocks the constant high logic value from its d input to its q output - N11.Since in general N11 could go high asynchronously with respect to the activity gated by ICLK, the two flip-flops 28 and 30 are used to resynchronize the interrupt status read flag Nll.

The two flip-flops prevent metastable behavior of the arbitrator.

N12 will go high after the second rising edge of ICLK. When N13 goes high, CLRSTN will go low clearing the interrupt output status register in preparation for the next interrupt cycle.

Flip-flops 36 and 28 are also cleared in preparation for the next cycle. On the third rising edge of ICLK, the high value of N13, through OR gate 50, is clocked from the d input of flip-flop 32 to the q output, causing ARMED to go high active again. At the same time, the low value of N12 is clocked into flip-flop 30 causing N13 to go low and CLRSTN to go high inactive. The arbitrator is now fully armed and ready to respond to any new or pending interrupt requests. If any of the signals HOLDO, HOLD1, or HOLD2 are active, then a self-time cycle would be immediately triggered because both the ACTIVE and ARMED signals would be high.

For proper operation of the circuit, the host should never generate an active low STATRD signal unless the INTERRUPT signal has gone active high. The interrupt requests are double buffered so that during the latency period between the time that the first group of interrupt requests are transferred to the interrupt output status register, until the processor responds and the circuit rearms itself, all of the different interrupt request lines are monitored for activity. Activity will be correctly detected on any or all of the interrupt request lines. The number of times that a particular interrupt request line goes active will not be tracked by the circuit of the invention as described herein.To enumerate the number of occurrences of each interrupt request during the latency period, each of the holding latches 26, 24, and 22 would have to be replaced with counter circuits enabled by their respective interrupt request lines IREQO, IREQ1, and IREQ2. The interrupt output status registers 48, 46, and 44 would have to be replaced by multiple-bit registers to store the counter states. This additional functionality is easy to achieve, but it is usually unnecessary in a typical system.

After the host processing element has been notified of a pending interrupt and has responded by reading the status register, the circuit resets itself by means of a self-timed sequence and is armed to accept future interrupt requests for processing. Thus, the inventive asynchronous interrupt arbitrator satisfies the objects set forth above in that it provides a reliable solution to the problem of safely resolving multiple asynchronous interrupt sources with the host processor interface. Although the invention has been described in detail in connection with a single embodiment, various modifications will be readily apparent to those of ordinary skill in the art.

Such modifications are within the spirit and scope of the invention which is limited and defined only by the appended claims.

Claims (15)

What Is Claimed Is:

1. An asynchronous interrupt arbitrator adapted to store the active state of a plurality of interrupt request inputs and capable of responding to interrogation by an asynchronous host regarding the status of the interrupt request activity, said interrupt arbitrator comprising an interrupt request holding register, an interrupt status output register, and a sequential control circuit operatively connected between said request holding register and said interrupt status output register for controlling the transfer of data between said interrupt request holding register and said interrupt status output register.

2. The asychronous interrupt arbitrator according to Claim 1, wherein said interrupt request holding register comprises storage elements for counting or registering the occurrence of interrupt request activity and for storing such count or other indication until it is transferred to said interrupt status output register.

3. The asynchronous interrupt arbitrator according to Claim 2, wherein said interrupt status output register comprises storage elements for holding said count or other indication until said count or other indication is read by a host processing element.

4. The asynchronous interrupt arbitrator according to Claim 1, wherein said control circuit further includes means for initializing both of said registers.

5. The asynchronous interrupt arbitrtator according to Claim 4, wherein said control circuit comprises a signal synchronizing section and a self-timed sequencer.

6. The asynchronous interrupt arbitrator according to Claim 5, wherein said signal synchronizing section comprises at least one edge-triggered flip-flop.

7. The asynchronous interrupt arbitrator according to Claim 6, wherein said self-timed sequencer comprises at least one set-reset element for directing the transfer of data between register subsections.

8. The asynchronous interrupt arbitrator according to Claim 7, wherein said self-timed sequencer further comprises at least one flip-flop (not necessarily a set-reset), element used to store the armed state of the control section.

9. The asynchronous interrupt arbitrator according to Claim 7, wherein said set-reset element is triggered according to the following logical formula: TRIGGER = ACTIVE * ARMED where TRIGGER is the logical signal that initiates the self-timed sequence; ACTIVE is the signal that indicates that one or more of the interrupt request holding registers contains an indication of interrupt request activity; ARMED is the logical signal that indicates that the control section is ready to respond to an interrupt request; and * is a logical AND operation.

10. The asynchronous interrupt arbitrator according to Claim 9, wherein said set-reset element is deactivated according to the following logical formula: COMPLETE = (-ACTIVE) * (-ARMED) where COMPLETE is the logical signal that deactivates the set-reset element at the completion of the self-timed sequence; ACTIVE is the signal that indicates that one or more of the interrupt request holding registers contains an indication of interrupt request activity; ARMED is the logical signal that indicates that the control section is ready to respond to an interrupt request; - is a logical NOT or complement operation; and * is a logical AND operation.

11. The asynchronous interrupt arbitrator according to Claim 10, wherein a logical signal output is provided to indicate that one or more of the interrupt output status registers contain an active interrupt indication.

12. The asynchronouslinterrupt arbitrator according to Claim 11, further comprising means for transferring the information contained in the interrupt status output register to the host processing element during a status read operation.

13. The asynchronous interrupt arbitrator according to Claim 12, further comprising means effective following a status read operation to clear the interrupt status output register and to arm the arbitrator in preparation for the next occurrence of an interrupt request.

14. An interrupt controller having an interrupt input means and an interrupt output means, an interrupt signal provided to the output means being stored by it until it is read by an interrupt receiving device, and an interrupt signal received by the input means being stored by it until it is provided to the output means.

15. Signal handling apparatus substantially as herein described with respect to the accompanying drawing.