JPH0555532A - Gate array - Google Patents

Abstract

PURPOSE:To test the function of logic circuits without using a lot of test input signal terminals in a built-in test circuit. CONSTITUTION:The mode select output terminals Q1 to Qn of a shift registor SR are connected with the select input terminals S of multiplexers M1 to Mn, and a test input signal STi is inputted into the logic circuit C2 to be tested only when the i-th mode select signal SQi is 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gate array, and more particularly to a test mode setting circuit for an internal digital logic circuit.

[0002]

2. Description of the Related Art In a relatively small-scale gate array digital logic circuit, in order to improve the testability of the circuit, which has not been severely saved in timing, the degree of freedom in controlling the circuit has been improved in order to improve the degree of freedom of control. There is a method of inserting a multiplexer between the circuit blocks (for example, see John W. Reed, translated by Harada, “Gate Array Design and Application” p.271, Keigaku Shuppan).

In FIG. 3A, the multiplexer M
Outputs the input data DA which enters the data input end A to the data output end Y when the signal SS of the select input end S is "0", and outputs the data input end B when the select signal SS is "1".
The input data DB of is output to the data output Y. The output terminal O1 of the pre-stage circuit C1a is connected to the data input terminal A of the multiplexer M, and the test signal input terminal T is connected via the input buffer B to the data input terminal B of the multiplexer M.
, And the mode select signal input terminal TS via the input buffer BS to the select input terminal S of the multiplexer M.
And the data output terminal Y of the multiplexer M is connected to the input I1 of the logic circuit under test C2a.

Normally, a "0" level is input as the test mode select signal SM to the mode select signal input terminal TS, and the output terminal O1 of the preceding circuit C1a is connected to the multiplexer M.
Is connected to the input I1 of the logic circuit under test C2a via.

In the test mode, a "1" level is input as the mode select signal SM to the mode select signal input terminal TS, and the test input signal ST from the test signal input terminal T is passed through the multiplexer M to the logic circuit under test C2a.
Of the logic circuit under test C2a to test the control operation.

FIG. 3B shows an example in which n circuits of the test signal input terminal T and the multiplexer M shown in FIG. 3A are provided. Normally, the mode select signal input terminals TS1 to TS / are provided.
"0" as the mode select signals SM1 to SM1n in n
And the outputs O1 to On of the preceding circuit C1 are connected to the inputs I1 to In of the logic circuit under test C2 via the multiplexers M11 to M1n, respectively.

In the test mode, the mode select signals SM1 to S are input to the mode select signal input terminals TS1 to TS / n.
Input "1" as Mn, and input the test signal T1
1, test input signals ST1 to STn from T1n are input to input terminals I1 to In of a logic circuit under test C2 via multiplexers M11 to M1n, respectively, and the logic circuit under test C2 is tested.
Test the control function of.

[0008]

The above gate array is limited in the number of terminals when testing an internal logic circuit to be tested, especially in a relatively small gate array.
It is difficult to increase the number of input terminals in the circuit of FIG. 3 (a) as it is, and in the circuit of FIG. 3 (b), it is necessary to input in consideration of the timing of all test input signals in the test mode. When disconnecting the connection between a plurality of circuit blocks and performing the control operation of the circuit under test in the subsequent stage, the control of the controllability is large, because the timing control becomes complicated as the number of test terminals increases. There was a problem.

[0009]

A gate array according to the present invention includes a pre-stage circuit which receives input signals from a plurality of external signal input terminals corresponding to a plurality of data input terminals and outputs data signals from a plurality of output terminals. The data signal corresponding to the data input terminal is input or the test signal is input to the test signal input terminal, and the mode select signal input to the select terminal outputs the data signal in the normal mode and the test signal in the test mode. In a gate array having a plurality of multiplexers that are input and supplied from an output terminal to a corresponding input terminal of a logic circuit under test, the test mode signal and the clock signal respectively input to external terminals are input and the mode select is performed. A shift register having a plurality of output terminals for outputting signals is added.

[0010]

The present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of the first embodiment of the present invention.
The gate array receives the input signals from the n external signal input terminals TD1 to TDn corresponding to the n data input terminals I11 to I1n and receives the data signal D1 from the n output terminals O1 to On.
A front-end circuit C1 that outputs A to DnA and a data input terminal A
The data signal DiA corresponding to or the test signal STi to the test signal input terminal B,
The data signal DiA is input in the normal mode and the test signal STi is input from the test signal input terminals TT1 to TTn in the test mode by the mode select signal SQi input to the output terminal Y and the corresponding input terminal of the logic circuit under test C2 is input. Negative multiplexors M1 to M supplied to Ii
n, and the mode select signal SQ1 by inputting the test mode signal Si and the clock signal SC input to the test mode signal input terminal T1 and the clock signal terminal T2.
Includes a shift register SR having n output terminals Q1 to Qn for outputting .about.SQn.

The data terminal A of the i-th multiplexer MOi is connected to the output terminal i of the logic circuit under test C2, and the test terminal B is connected to the output terminal Qi of the shift register to select the test mode signal Si. It can be observed from the output terminal TOi by inputting it to the terminal S and switching between the test output signal SOi and the mode select signal SQj. Where i
Is an arbitrary number from 1 to n.

Next, the operation of the block shown in FIG. 1 will be described. Before the start of normal operation, the test mode signal input terminal T1 is supplied with “0 symbol level, clock input terminal T2 as the input signal Si.
When the clock signal SC is input to the shift register SR to set all the mode select output terminals Q1 to Qn of the shift register SR to "0" level, the data output terminals O1 to On of the preceding circuit C1 are tested via the multiplexers M1 to Mn, respectively. Logic circuit C
The two input terminals I1 to In are connected to enable normal operation.

In the test mode, the i-th input terminal Ii of the logic circuit under test C2 is determined, and the output terminal Qi of the shift register SR connected to the select input terminal S of the multiplexer Mi connected thereto is set to "1" level. Then, the test input signal STi is input from the corresponding input terminal TTi to test the function of the logic circuit under test C2.

When a "0" level is input to the test mode input terminal T1, the outputs O1 to O1 of the logic circuit block C2 to be tested.
When On inputs a "1" level to the select signal input terminal T1 again, the output terminals Q1 to Qn of the shift register SR
Can be observed from the output terminals TO1 to TOn, respectively.

In the present embodiment, only the output terminal Qi of the shift register SR corresponding to the i-th input terminal Ii of the logic circuit under test C2 is set to "1" level and the test input signal STi is passed through the multiplexer Mi to the logic circuit C2. Input to the input terminal Ii, and the remaining output terminals Qj (j ≠ i) are set to the “0” level to connect the output terminals Oj (j ≠ j of the normal preceding circuit C1.
i) The connection with the test mode signal terminal TT can be maintained.
Even if the number of 1 to TTn is reduced from n in the conventional case to two, that is, T1 and T2, the control function of the logic circuit C2 can be tested under the condition close to the normal operation.

FIG. 2 is a block diagram of the second embodiment of the present invention. When the demultiplexer DM inputs a "0" level from the test mode input terminal TTM to the gate input terminal G, the data inputs D1 to D1 to the data output terminals A1 to A1n, respectively.
The data of 1n and the "0" level are output to the data output terminals B1 to B1n.

When a "1" level is input to the gate input terminal G, the data input terminals D are connected to the data output terminals B1 to B1n, respectively.
1 to D1n data, and data output terminals A1 to A1
It has a switch function for outputting a "0" level to n.

Input terminals T1 to T1 used for the test in this embodiment
All of TDn are connected to the demultiplexer DM via the input buffers B1 to BDn, and the other configurations are the same as those of the first embodiment, but the input terminals TD1 to TD are used in the test mode.
Since Dn also serves as the test terminal, the test signal input terminal T
It is possible to test without providing 11 to T1n exclusively, and there is an advantage that the improvement effect is particularly large in a relatively small-scale gate array having a large number of terminals.

[0019]

As described above, according to the present invention, by using the shift register, only three or less input terminals for the test mode are provided and the internal logic circuit of the internal logic circuit is operated under the condition close to the normal operation. It has an effect that the control function can be tested.

[Brief description of drawings]

FIG. 1 is a block diagram of a first embodiment of the present invention.

FIG. 2 is a block diagram of a second embodiment of the present invention.

FIG. 3 is a block diagram of an example of a conventional gate array.

[Explanation of symbols]

B1, B2, BD1 to BDn, BT1 to BTn input buffer B21 to B2n output buffer C1 pre-stage circuit C2 logic circuit under test DM demultiplexer M1 to Mn input multiplexer MO1 to MOn output multiplexer SR shift register T1 test mode signal input terminal T2 clock Input terminal TT1 to TTn test signal input terminal TD1 to TDn signal input terminal TO1 to TOn output terminal TTM test mode input terminal

Claims (1)

[Claims] 1. A pre-stage circuit that receives input signals from a plurality of external signal input terminals corresponding to a plurality of data input terminals and outputs data signals from a plurality of output terminals, and inputs the data signals corresponding to the data input terminals. Or a test signal is input to the test signal input terminal, and the data signal is normally input by the mode select signal input to the select terminal, and the test signal is input in the test mode to output the test signal from the output terminal of the logic circuit under test. In a gate array having a plurality of multiplexers to be supplied to corresponding input terminals, it has a plurality of output terminals for receiving a test mode signal and a clock signal respectively input to external terminals and outputting the mode select signal. A gate array characterized by adding a shift register.