KR20070055850A - Boundary scan test cell and boundary scan test device - Google Patents

Abstract

The present invention relates to a scan test apparatus.

According to the present invention, a boundary scan test unit which receives a signal and tests input and output of a corresponding pin, and whether or not the input and output test of the pin corresponding to the boundary scan test unit are required may be performed. It provides a boundary scan test cell comprising a multiplexer for selecting and outputting one signal from the tested signals of the boundary scan test unit.

Therefore, according to the present invention, since the boundary test apparatus does not have to be implemented separately for each pin, it is easy to implement and the possibility of error can be greatly reduced.

Boundary scan test

Description

Boundary scan test cell and boundary scan test device

1 is a structural diagram of a conventional boundary scan test apparatus

2 is a boundary scan test cell in accordance with the present invention.

3 is a boundary scan test apparatus according to the present invention.

* Explanation of symbols for main parts of drawings *

10: multiplexer 20: third multiplexer

30: second boundary scan test unit 40: second multiplexer

50: first boundary scan test unit 60: first multiplexer

100: dual boundary cell 200: fourth multiplexer

200: control unit

The present invention relates to a test chip, and more particularly, to a test chip for selectively performing a boundary scan test of the pins to be tested among the pins of the chip.

In recent years, chip designs are becoming more and more complicated. Furthermore, the introduction of a system on a chip (SoC) requires consideration of not only hardware but also software elements. Therefore, there are many elements in one chip, and the technique for testing them becomes more complicated.

Among other things, the boundary scan test is a test of the chip's in / out pins and follows the JTAG standard. However, as the integration of the chip described above and the complexity of the test increase, boundary scan test is also required to be applied in various forms.

1 illustrates a conventional pin selective boundary scan test chip.

Referring to FIG. 1, for example, suppose a chip includes three elements A, B, and C. Referring to FIG. In some specific applications, if A is not needed, and only B and C are required, then no boundary scan test is required for the pin corresponding to A. In addition, if the A counter's pin counter is large, there is no need to spend unnecessary test time. In this case, it is necessary to enable boundary scan test of only the B and C modules without changing the core logic and pins of the chip.

Conventionally, in this case, it could be implemented by glue logic. However, if the pin count is large, it is difficult to implement it by following the corresponding pin one by one, and there is a possibility that an error may occur.

Figure 1 shows the boundary scan test structure of the conventional method. That is, when only the first and third pins are tested and the second and second pins are excluded from the test, the separate multiplexer 10 and the corresponding control logic should be put into operation. In other words, depending on whether or not pin 2 is included in the boundary scan test, the mux control signal should be put differently. In this case, you have to decide whether to add mux for each pin, and you have to deal with different processing for each pin. This greatly increases the possibility of error occurrence.

The present invention is to solve the above problems, an object of the present invention is to provide a test chip that reduces the overall test time by selectively pinning, and the boundary scan test for it.

In order to achieve the above object, the present invention is due to the boundary scan test unit for receiving a signal to test the input and output of the corresponding pin, the input or output test of the pin corresponding to the boundary scan test unit, It provides a boundary scan test cell, characterized in that it comprises a multiplexer for selecting and outputting one signal from the received signal or the tested signal of the boundary scan test unit.

According to another embodiment of the present invention, the present invention provides a first boundary scan test unit for receiving a signal and testing input and output of a corresponding pin, and an input and output test of a pin corresponding to the first boundary scan test unit. According to the request, a first multiplexer for selecting and outputting one signal from the input signal or the tested signal of the first boundary scan test unit, and receives input and output of a corresponding pin. The second boundary scan test unit to be tested, the input of the pin corresponding to the second boundary scan test unit, the output of the input signal, or from the tested signal of the second boundary scan test unit based on whether A second multiplexer for selecting and outputting one signal; an external output unit of the first boundary scan test unit And a third multiplexer for selecting and outputting an output value or an output value of an external output unit of the second boundary scan test unit.

According to still another embodiment of the present invention, the present invention provides a first boundary scan test unit for receiving a signal and testing input / output of a corresponding pin and an input / output test of a pin corresponding to the first boundary scan test unit. Depending on whether or not, the first channel formed by the first multiplexer for selecting and outputting a signal from the received signal as it is or the signal tested by the first boundary scan test unit, the corresponding pin receives the corresponding pin The second boundary scan test unit for testing the input and output of the input signal and the second boundary scan test based on whether the input and output test of the pin corresponding to the second boundary scan test unit is required. A second channel formed by a second multiplexer for selecting and outputting one signal among negative tested signals, and At least one dual boundary scan forming a dual line including a third multiplexer for selecting and outputting one output value from an output value of an external output unit of the first boundary scan test unit or an output value of the external output unit of the second boundary scan test unit. And a fourth multiplexer for selecting one output value from a cell, an output value of a first channel or a second channel of a dual line of the dual boundary scan cell, and a controller for controlling the dual boundary scan cell and the fourth multiplexer as a whole. .

Therefore, according to the present invention, since the boundary test apparatus does not have to be implemented separately for each pin, it is easy to implement and the possibility of error can be greatly reduced.

Hereinafter, with reference to the accompanying drawings, preferred embodiments of the present invention that can specifically realize the above object will be described.

2 illustrates a boundary scan test cell in accordance with the present invention.

Referring to FIG. 2, the boundary scan test cell receives a signal based on a boundary scan test unit configured to test input / output of a corresponding pin, and whether an input / output test of a pin corresponding to the boundary scan test unit is required. And a multiplexer for selecting and outputting one signal from the received signal or the tested signal of the boundary scan test unit.

It also offers dual-line boundary scan test cells with two boundary scan tests. The dual line boundary scan test cell is based on whether a first boundary scan test unit which receives a signal and tests input and output of a corresponding pin, and whether an input / output test of a pin corresponding to the first boundary scan test unit is required. A first multiplexer for selecting and outputting one signal from the received signal or the tested signal of the first boundary scan test unit, and a second input and output test signal of a corresponding pin. Depending on whether an input / output test of a pin corresponding to the second boundary scan test unit or the second boundary scan test unit is required, one signal is output from the received signal or the tested signal of the second boundary scan test unit. A second multiplexer for selecting and outputting an output of an external output unit of the first boundary scan test unit; Or it consists of the group 3 multiplexer for selecting and outputting the second boundary scan test output external output section portion.

A first embodiment according to the present invention provides a boundary scan test cell having one boundary scan test unit, and the second embodiment provides a dual line boundary scan test cell having two boundary scan test units.

The boundary scan test cell is connected at one end to a corresponding pin for testing and at the other end to an external circuit diagram.

The boundary scan test unit includes a Pi unit connected to a corresponding pin, a Po unit which is an external output unit, a Si unit which is a signal input unit that receives a boundary scan test output value of a preceding pin of a corresponding pin, and a boundary of a corresponding pin. It includes a So unit that is a signal output unit for outputting a scan test value.

When the input and output test of the pin corresponding to the boundary scan test unit is required, a signal line passing through the boundary scan test unit is formed, and when not required, a signal line passing the boundary scan test unit is formed. do.

As two boundary scan test units, a boundary scan test cell forming a dual line will be described with reference to FIG. 2.

The dual scan test cell 100 includes a first boundary scan test unit 50, a first multiplexer 60, a second boundary scan test unit 30, a second multiplexer 40, and a third multiplexer 20. It is composed of

Po, which is an external output unit of the first boundary scan test unit, and Po, which is an external output unit of the second boundary scan test unit, are connected to the third multiplexer.

The boundary scan test cell is formed of a first channel formed by the first boundary scan test unit and the first multiplexer, and a second channel formed by the second boundary scan test unit and the second multiplexer. That is, by configuring the scan cells to have two separate scan chain structures, there is no need to apply a scheme differently according to the pins of FIG. 1. It is divided into a scan chain 1 consisting of the first boundary scan test unit 50 and the first multiplexer 60, and a scan chain 2 consisting of the second boundary scan test unit 30 and the second multiplexer 40, If necessary, select the required scan chain from the two chains. The third multiplexer 20 selects the selection of the scan chain.

When the structure is described in detail, the actual signal connected to the pin is connected to Pi or Po, and the signal connected to Pi is respectively connected to Pi of the first boundary scan test unit 50 or Pi of the second boundary scan test unit 30. Connected. In the case of including this pin in scan chain 1, the sel2 signal may be selected to receive the so signal of the first boundary scan test unit. If you want to remove this pin from scan chain 2, you can select the sel3 signal so that sib is the input of the second multiplexer. Therefore, when applying boundary scan cells presented here, two separate scan chains can be used, and in each scan chain, the inclusion of a pin can be simply implemented by using a mux selection signal. have.

3 illustrates a boundary scan test apparatus to which a new scan cell is applied. The boundary scan test apparatus may receive a signal based on whether a first boundary scan test unit which receives a signal and tests input / output of a corresponding pin and whether an input / output test of a pin corresponding to the first boundary scan test unit is required. A first channel formed by a first multiplexer that selects and outputs one signal from an input signal or a tested signal of the first boundary scan test unit, and receives an input signal and tests input / output of a corresponding pin One of the input signal or the tested signal of the second boundary scan test unit, depending on whether an input / output test of a pin corresponding to the second boundary scan test unit and the second boundary scan test unit is required. A second channel formed by a second multiplexer for selecting and outputting the first boundary; At least one or more dual boundary scan cells forming a dual line, including a third multiplexer for selecting and outputting one output value from an output value of an external output unit of the test unit or an output value of the second boundary scan unit of the test unit, and the dual boundary scan And a fourth multiplexer for selecting one output value from among output values of the first channel or the second channel of the dual line of the cell, and a controller for controlling the dual boundary scan cell and the fourth multiplexer as a whole.

That is, the dual boundary cells 100 connected to each pin are serially connected to form a boundary scan test device of the entire chip, and finally, the fourth multiplexer 200 at the final stage determines which scan chain to select. The decision is made by the control.

The output value of the boundary scan test cell 100 is input to the boundary scan test cell 100 of a subsequent pin of the corresponding pin. The boundary scan test cell has one side connected to a corresponding pin, and the other side connected to an external circuit diagram.

The boundary scan test cell 100 and the fourth multiplexer 200 are entirely controlled by the controller 300.

The present invention is not limited to the above-described embodiments, and can be modified by those skilled in the art as can be seen from the appended claims, and such modifications are within the scope of the present invention. .

The effect of the boundary scan test apparatus according to the present invention described above is as follows.

According to the present invention, since the boundary test device does not have to be implemented separately for each pin, it is easy to implement and the possibility of error can be greatly reduced.

Claims (12)

A boundary scan test unit configured to receive a signal and test input / output of a corresponding pin; And a multiplexer for selecting and outputting one signal from the received signal or the tested signal of the boundary scan test unit based on whether an input / output test of a pin corresponding to the boundary scan test unit is required. Boundary scan test cell. A first boundary scan test unit configured to receive a signal and test an input / output of a corresponding pin; A first signal that selects and outputs one signal from the received signal or the tested signal of the first boundary scan test unit based on whether an input / output test of the pin corresponding to the first boundary scan test unit is required 1 multiplexer; A second boundary scan test unit configured to receive a signal and test an input / output of a corresponding pin; A signal for selecting and outputting one signal from the received signal or the tested signal of the second boundary scan test unit based on whether an input / output test of the pin corresponding to the second boundary scan test unit is required; Two multiplexing groups; And a third multiplexer configured to select and output an output value of the external output unit of the first boundary scan test unit or an output value of the external output unit of the second boundary scan test unit. The method according to claim 1 or 2, The boundary scan test unit includes a Pi unit connected to a corresponding pin and a Po unit as an external output unit. The method according to claim 1 or 2, The boundary scan test unit may include a Si unit that receives a boundary scan test output value of a corresponding pin of a corresponding pin, and an So unit that outputs a boundary scan test value of a corresponding pin. Boundary scan test cell. The method according to claim 1 or 2, When the input and output test of the pin corresponding to the boundary scan test unit is required, forming a signal line passing through the boundary scan test unit, if not required, forming a signal line passing the boundary scan test unit Boundary scan test cell, characterized in that. The method of claim 2, A boundary scan test cell, wherein the Po is an external output of the first boundary scan test unit and a Po unit of an external output of the second boundary scan test unit is connected to the third multiplexer. The method of claim 2, A first channel formed by a first boundary scan test unit and a first multiplexer; A boundary scan test cell comprising a second boundary scan test unit and a second channel formed by a second multiplexer.  The first boundary scan test unit for receiving the signal and testing the input and output of the corresponding pin, and whether the input and output test of the pin corresponding to the first boundary scan test unit is required or not, the received signal as it is. Alternatively, a first channel formed by a first multiplexer for selecting and outputting one signal among the tested signals of the first boundary scan test unit, and a second boundary scan test unit configured to test an input and an output of a corresponding pin by receiving a signal And selecting one signal from the received signal or the tested signal of the second boundary scan test unit based on whether an input / output test of the pin corresponding to the second boundary scan test unit is required. A second channel formed by a second multiplexer, an external output of the first boundary scan test unit At least one or more dual boundary scan cells forming a dual line including a third multiplexer for selecting and outputting one output value from an output value or an output value of an external output unit of the second boundary scan test unit; A fourth multiplexer for selecting one output value from an output value of a first channel or a second channel of a dual line of the dual boundary scan cell; Boundary scan test device including a control unit for controlling the dual boundary scan cell and the fourth multiplexer as a whole. The method of claim 8, The boundary scan test unit includes a Pi unit connected to a corresponding pin and a Po unit as an external output unit. The method of claim 8, The boundary scan test unit may include a Si unit that receives a boundary scan test output value of a corresponding pin of a corresponding pin, and an So unit that outputs a boundary scan test value of a corresponding pin. Boundary scan test device. The method of claim 8, The boundary scan test apparatus, wherein the output value of the boundary scan test cell is input to the boundary scan test cell of a subsequent pin of the corresponding pin. The method of claim 8, The boundary scan test cell is a boundary scan test device, characterized in that one side is connected to the corresponding pin, the other side is connected to an external circuit diagram.

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