JPH0555360A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH0555360A JPH0555360A JP21353491A JP21353491A JPH0555360A JP H0555360 A JPH0555360 A JP H0555360A JP 21353491 A JP21353491 A JP 21353491A JP 21353491 A JP21353491 A JP 21353491A JP H0555360 A JPH0555360 A JP H0555360A
- Authority
- JP
- Japan
- Prior art keywords
- trench
- film
- sio
- bpsg
- opening width
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
Description
【０００１】[0001]
【産業上の利用分野】この発明は半導体装置の製造方法
に関し、更に詳しくは、サブミクロンデバイスの素子分
離技術に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a technique for isolating submicron devices.
【０００２】[0002]
【従来の技術】従来のこの種の方法はＬＯＣＯＳ方或い
はＢＯＸ法にて行われていた。2. Description of the Related Art A conventional method of this kind is performed by the LOCOS method or the BOX method.
【０００３】[0003]
【発明が解決しようとする課題】しかし、上記従来法で
は、トレンチ内をＣＶＤ−ＳｉＯ2 膜等で埋め込む場
合、開口径が０．３〜１．０μｍの微細なトレンチで
は、アスペクト比が大となり、トレンチ内を均一に埋め
込めない。また、ＢＰＳＧ／ＣＶＤ−ＳｉＯ2 のエッチ
バックの際ドライエッチングを行う場合に均一性、選択
性が十分でなく、またウェットエッチングを行った場合
でもトレンチのエッジ部で段差を生じる。However, in the above conventional method, when the trench is filled with a CVD-SiO 2 film or the like, the aspect ratio becomes large in a fine trench having an opening diameter of 0.3 to 1.0 μm. , The trench cannot be filled uniformly. Further, uniformity and selectivity are not sufficient when dry etching is performed during etch back of BPSG / CVD-SiO 2 , and even when wet etching is performed, a step is formed at the edge portion of the trench.
【０００４】[0004]
【課題を解決するための手段及び作用】この発明は、開
口幅の狭いトレンチと開口幅の広いトレンチを有する半
導体基板内に、(a) その基板の表面全面を酸化した後そ
の酸化膜の全面にＰｏｌｙ−Ｓｉ膜を堆積後エッチバッ
クして開口幅の狭いトレンチ内にＰｏｌｙ−Ｓｉ膜を残
存させる工程と、(b) トレンチを含む半導体基板上の全
面にＳｉ3 Ｎ4 膜を堆積する工程と、(c) 少なくともト
レンチ内が埋設されるようにガラス層に対して非溶解性
のＳｉＯ2 膜を形成後その上にＳｉＯ2 に対して良溶融
性のガラス層を積層する工程と、(d) 高温アニール後平
坦化し、Ｓｉ3 Ｎ4 膜が露出するまでドライエッチング
或いは、ウエットエッチングを行ってトレンチに非溶解
性のＳｉＯ 2 膜を埋め込むことで素子分離領域を形成す
るに際して、開口幅の広いトレンチ内に埋め込まれる非
溶解性のＳｉＯ2 膜の段差がなくなるまで上記(c) 、
(d) 工程を順次少なくとも１回以上繰り返し、それによ
ってトレンチ内を埋め込むようにする工程とからなる半
導体装置の製造方法である。すなわち、この発明では、
Ｓｉ3 Ｎ4 膜を、非溶解性のＳｉＯ2 膜を形成後その上
に良溶融性のガラス層を積層してこれらをエッチバック
して非溶解性のＳｉＯ2 膜をトレンチ内に埋設する際の
ストッパーとして用いる。また、素子分離領域形成後ト
レンチ内に埋め込んだ非溶解性のＳｉＯ2 膜の表面をＳ
ｉ基板の表面よりも高く配置する。更にはＳｉ3 Ｎ4 膜
の介在によって良溶融性のガラスを積層して高温アニー
ルで平坦化する際、Ｓｉ3 Ｎ4 膜の介在によって良溶融
性のガラスからの不純物のオート・ドーピングを防止で
きるようにしたものである。SUMMARY OF THE INVENTION
Half with narrow mouth trench and wide opening trench
Inside the conductor board, (a) oxidize the entire surface of the board and then
After depositing a Poly-Si film on the entire surface of the oxide film of
And leave the Poly-Si film in the trench with a narrow opening.
And (b) the entire surface of the semiconductor substrate including the trench.
Si on the surface3NFourDepositing the film, and (c) at least
Insoluble in the glass layer so that the inside of the wrench is embedded
SiO2After forming a film, SiO on it2Good melting against
The process of laminating a transparent glass layer, and (d) flattening after high temperature annealing.
TAN, Si3NFourDry etching until the film is exposed
Alternatively, wet etching is performed to dissolve into the trench
SiO 2Element isolation region is formed by embedding a film
When filling the trench with a wide opening,
Soluble SiO2Until the step of the film disappears (c),
(d) Repeat steps at least once more,
The process of filling the trench
It is a manufacturing method of a conductor device. That is, in this invention,
Si3NFourThe film is made of non-dissolving SiO2After forming the film
Laminate a glass layer with good melting property on these and etch back these
And insoluble SiO2When burying the film in the trench
Used as a stopper. In addition, after forming the element isolation region,
Insoluble SiO embedded in a wrench2S on the surface of the membrane
It is arranged higher than the surface of the i substrate. Furthermore, Si3NFourfilm
High-temperature annealing by laminating good melting glass
When flattening with3NFourGood melting due to the inclusion of a film
Of auto-doping of impurities from organic glass
It was made possible.
【０００５】[0005]
【実施例】まず、図１に示すように、Ｓｉ基板１に開口
幅（開口径）0.5 μｍ、深さ0.6μｍの、幅の狭いトレ
ンチ２を形成する。そして、トレンチ２内を酸化して膜
厚Ａが500 ÅのＳｉＯ2 膜３を形成し、その後、Ｐｏｌ
ｙ−Ｓｉ膜４を膜厚Ｂが6000Åに堆積する。一方、図２
は図１と同時工程で作成される幅広のトレンチ22の領域
を示す。次に、トレンチ２,22 におけるＰｏｌｙ−Ｓｉ
膜４をＲＩＥによりエッチバックする（図３、図４参
照）。この時、狭いトレンチ２（図３参照）では、トレ
ンチ内にＰｏｌｙ−Ｓｉ膜４ａが2000〜3000Å程度残る
ようにエッチバックする。一方、幅広のトレンチ22内で
はトレンチ内の側壁部以外はＰｏｌｙ−Ｓｉ膜が残存す
ることなく除去される（図４参照）。次に、トレンチ内
にＳｉ3 Ｎ4 膜５をＣＶＤ法により500 Å堆積する（図
３、図４参照）。次に、図５、図６に示すように非溶融
性のガラス、例えば、ＣＶＤ−ＳｉＯ2 膜６を6000Å厚
積層し、その上に良溶融性のガラス、例えば、ＢＰＳＧ
膜７を6000Å積層し、続いて900 〜1000℃の高温アニー
ルで平坦化する。この際、Ｓｉ3 Ｎ4 膜５の介在によっ
てＢＰＳＧ膜７からのボロン、リンのオート・ドーピン
グを防止できる 次にＢＨＦにより、Ｓｉ3 Ｎ4 膜５が露出するまでエッ
チバックして各トレンチ２,22 内にＣＶＤ−ＳｉＯ2 膜
６を残存させる（図７、図８参照）。この時、幅広のト
レンチ22（図８参照）では、エッジ部で段差８が生じ
る。このため、図９、図10に示すようにさらに（ｉ）Ｃ
ＶＤ−ＳｉＯ2 膜９及びＢＰＳＧ膜10を順次積層する工
程と、（ii）上記と同じ高温アニール工程と、さらに
（iii ）ＳｉＯ2 膜９、ＢＰＳＧ膜10のエッチバックの
工程をトレンチ22内で、ＣＶＤ−ＳｉＯ2 膜の段差が生
じないように（図12参照）、かつ均一で平坦な表面を有
するようになるまで再度繰り返すことにより、ＣＶＤ−
ＳｉＯ2 膜９を埋め込むことができる（図11、図12参
照）。最後に、図１３、図１４に示すようにトレンチ
２,22 内に存在しているＳｉ3 Ｎ4 膜５とＳｉＯ2 膜３
のみを残して、Ｓｉ3 Ｎ4 膜５と、ＳｉＯ2 膜３を順次
削除することにより素子分離領域が完成する。この際、
狭いトレンチ２では、図５でＰｏｌｙ−Ｓｉ膜４ａを残
すことで埋め込まれたＣＶＤ−ＳｉＯ2 膜６のかさあげ
を行うことができ、それによってトレンチ内のアスペク
ト比（深さ／開口幅）を低減でき、狭いトレンチ内にも
均一性良くＣＶＤ−ＳｉＯ2 膜を埋め込むことができ
る。このように本実施例では、Ｓｉ3 Ｎ4 膜５をＢＰＳ
Ｇ／ＣＶＤ−ＳｉＯ2 のエッチバックの際のストッパー
として用いることができる。また、素子分離領域形成後
トレンチ内に埋め込んだＣＶＤ−ＳｉＯ2 膜の表面をＳ
ｉ基板１の表面よりも高く配置することができる。更に
良溶融性のガラス、例えば、ＢＰＳＧ膜７を積層し、続
いて高温アニールで平坦化する際にＳｉ3 Ｎ4 膜５の介
在によってＢＰＳＧ膜７からのボロン、リンのオート・
ドーピングを防止できる。EXAMPLE First, as shown in FIG. 1, a narrow trench 2 having an opening width (opening diameter) of 0.5 μm and a depth of 0.6 μm is formed in a Si substrate 1. Then, the inside of the trench 2 is oxidized to form a SiO 2 film 3 having a film thickness A of 500 Å.
The y-Si film 4 is deposited to a film thickness B of 6000Å. On the other hand, FIG.
Shows a region of the wide trench 22 formed in the same step as FIG. Next, Poly-Si in the trenches 2 and 22
The film 4 is etched back by RIE (see FIGS. 3 and 4). At this time, in the narrow trench 2 (see FIG. 3), etching back is performed so that the Poly-Si film 4a remains in the trench by about 2000 to 3000 Å. On the other hand, in the wide trench 22, the Poly-Si film is removed without remaining except the sidewall portion in the trench (see FIG. 4). Next, the Si 3 N 4 film 5 is deposited in the trench by CVD to a thickness of 500 Å (see FIGS. 3 and 4). Next, as shown in FIGS. 5 and 6, a non-melting glass, for example, a CVD-SiO 2 film 6 is laminated to a thickness of 6000Å, and a good melting glass, for example, BPSG
The film 7 is laminated by 6000Å and then flattened by high temperature annealing at 900 to 1000 ° C. At this time, the Si 3 N 4 film 5 can prevent the auto-doping of boron and phosphorus from the BPSG film 7. Next, BHF is used to etch back until the Si 3 N 4 film 5 is exposed. The CVD-SiO 2 film 6 is left inside the film 22 (see FIGS. 7 and 8). At this time, in the wide trench 22 (see FIG. 8), the step 8 is formed at the edge portion. Therefore, as shown in FIG. 9 and FIG.
In the trench 22, the VD-SiO 2 film 9 and the BPSG film 10 are sequentially laminated, (ii) the same high temperature annealing process as described above, and (iii) the etch back process of the SiO 2 film 9 and the BPSG film 10 in the trench 22. , CVD-SiO 2 film so as not to cause a step difference (see FIG. 12), and by repeating until a uniform and flat surface is obtained, CVD-
The SiO 2 film 9 can be embedded (see FIGS. 11 and 12). Finally, as shown in FIGS. 13 and 14, the Si 3 N 4 film 5 and the SiO 2 film 3 existing in the trenches 2 and 22 are formed.
The element isolation region is completed by sequentially removing the Si 3 N 4 film 5 and the SiO 2 film 3, leaving only this. On this occasion,
In the narrow trench 2, the buried CVD-SiO 2 film 6 can be bulged by leaving the Poly-Si film 4a in FIG. 5, thereby increasing the aspect ratio (depth / opening width) in the trench. The CVD-SiO 2 film can be embedded in the narrow trench with good uniformity. As described above, in this embodiment, the Si 3 N 4 film 5 is formed by BPS.
It can be used as a stopper when etching back G / CVD-SiO 2 . In addition, after forming the element isolation region, the surface of the CVD-SiO 2 film embedded in the trench is
It can be arranged higher than the surface of the i substrate 1. Further, when a glass having a good melting property, for example, a BPSG film 7 is laminated and subsequently flattened by high temperature annealing, the Si 3 N 4 film 5 intervenes so that boron and phosphorus from the BPSG film 7 can be automatically removed.
Doping can be prevented.
【０００６】[0006]
【発明の効果】以上のようにこの発明によれば、簡便か
つ低コストで、微細なトレンチから比較的広い幅のトレ
ンチまで非溶融性ガラスを均一性良く埋め込めることが
できる。また、パターン密度にも依存しないため、高集
積の半導体装置を製造することができる。As described above, according to the present invention, it is possible to easily and inexpensively fill non-melting glass from a fine trench to a trench having a relatively wide width with good uniformity. Further, since it does not depend on the pattern density, a highly integrated semiconductor device can be manufactured.
【図１】この発明の一実施例の狭い開口幅のトレンチに
おける製造工程の第１ステップを示す構成説明図であ
る。FIG. 1 is a structural explanatory view showing a first step of a manufacturing process in a trench having a narrow opening width according to an embodiment of the present invention.
【図２】上記実施例の広い開口幅のトレンチにおける製
造工程の第１ステップを示す構成説明図である。FIG. 2 is a structural explanatory view showing a first step of a manufacturing process in a trench having a wide opening width of the above-mentioned embodiment.
【図３】上記実施例の狭い開口幅トレンチにおける製造
工程の第２ステップを示す構成説明図である。FIG. 3 is a structural explanatory view showing a second step of the manufacturing process in the narrow opening width trench of the above embodiment.
【図４】上記実施例の広い開口幅のトレンチにおける製
造工程の第２ステップを示す構成説明図である。FIG. 4 is a structural explanatory view showing a second step of the manufacturing process in the trench having the wide opening width of the above-mentioned embodiment.
【図５】上記実施例の狭い開口幅のトレンチにおける製
造工程の第３ステップを示す構成説明図である。FIG. 5 is a structural explanatory view showing a third step of the manufacturing process in the trench having the narrow opening width of the above-mentioned embodiment.
【図６】上記実施例の広い開口幅のトレンチにおける製
造工程の第３ステップを示す構成説明図である。FIG. 6 is a structural explanatory view showing a third step of the manufacturing process in the trench having the wide opening width of the above-mentioned embodiment.
【図７】上記実施例の狭い開口幅のトレンチにおける製
造工程の第４ステップを示す構成説明図である。FIG. 7 is a structural explanatory view showing a fourth step of the manufacturing process for the trench having the narrow opening width in the above-mentioned embodiment.
【図８】上記実施例の広い開口幅のトレンチにおける製
造工程の第４ステップを示す構成説明図である。FIG. 8 is a structural explanatory view showing a fourth step of the manufacturing process for the trench having the wide opening width of the above-mentioned embodiment.
【図９】上記実施例の狭い開口幅のトレンチにおける製
造工程の第５ステップを示す構成説明図である。FIG. 9 is a structural explanatory view showing a fifth step of the manufacturing process of the trench having the narrow opening width of the above-mentioned embodiment.
【図１０】上記実施例の広い開口幅のトレンチにおける
製造工程の第５ステップを示す構成説明図である。FIG. 10 is a structural explanatory view showing a fifth step of the manufacturing process in the trench having the wide opening width of the above-mentioned embodiment.
【図１１】上記実施例の狭い開口幅のトレンチにおける
製造工程の第６ステップを示す構成説明図である。FIG. 11 is a structural explanatory view showing a sixth step of the manufacturing process in the trench having the narrow opening width of the above-mentioned embodiment.
【図１２】上記実施例の広い開口幅のトレンチにおける
製造工程の第６ステップを示す構成説明図である。FIG. 12 is a structural explanatory view showing a sixth step of the manufacturing process in the trench having the wide opening width of the above-mentioned embodiment.
【図１３】上記実施例の狭い開口幅のトレンチにおける
製造工程の第７ステップを示す構成説明図である。FIG. 13 is a structural explanatory view showing a seventh step of the manufacturing process in the trench having the narrow opening width of the above-mentioned embodiment.
【図１４】上記実施例の広い開口幅のトレンチにおける
製造工程の第７ステップを示す構成説明図である。FIG. 14 is a structural explanatory view showing a seventh step of the manufacturing process in the trench having the wide opening width of the above-mentioned embodiment.
１ Ｓｉ基板 ２ 狭い幅のトレンチ ３ 熱酸化によるＳｉＯ2 膜 ４ ポリシリコン膜 ４ａ 狭い幅のトレンチに残存したポリシリコン膜 ５ Ｓｉ3 Ｎ4 膜 ６, ９ ＣＶＤ−ＳｉＯ2 膜 ７, 10 ＢＰＳＧ膜 22 広い幅のトレンチ1 Si Substrate 2 Narrow Width Trench 3 SiO 2 Film 4 by Thermal Oxidation 4 Polysilicon Film 4 a Polysilicon Film Remaining in Narrow Width Trench 5 Si 3 N 4 Film 6, 9 CVD-SiO 2 Film 7, 10 BPSG Film 22 Wide trench
Claims (3)
レンチを有する半導体基板内に、 (a) その基板の表面全面を酸化した後その酸化膜の全面
にＰｏｌｙ−Ｓｉ膜を堆積後エッチバックして開口幅の
狭いトレンチ内にＰｏｌｙ−Ｓｉ膜を残存させる工程
と、 (b) トレンチを含む半導体基板上の全面にＳｉ3 Ｎ4 膜
を堆積する工程と、 (c) 少なくともトレンチ内が埋設されるようにガラス層
に対して非溶解性のＳｉＯ2 膜を形成後その上にＳｉＯ
2 に対して良溶融性のガラス層を積層する工程と、 (d) 高温アニール後平坦化し、Ｓｉ3 Ｎ4 膜が露出する
までドライエッチング或いは、ウエットエッチングを行
ってトレンチに非溶解性のＳｉＯ2 膜を埋め込むことで
素子分離領域を形成するに際して、 開口幅の広いトレンチ内に埋め込まれる非溶解性のＳｉ
Ｏ2 膜の段差がなくなるまで上記(c) 、(d) 工程を順次
少なくとも１回以上繰り返し、それによってトレンチ内
を埋め込むようにする工程とからなる半導体装置の製造
方法。1. In a semiconductor substrate having a trench with a narrow opening width and a trench with a wide opening width, (a) the entire surface of the substrate is oxidized, and then a Poly-Si film is deposited on the entire surface of the oxide film and then etched back. And leaving the Poly-Si film in the trench having a narrow opening width, (b) depositing the Si 3 N 4 film on the entire surface of the semiconductor substrate including the trench, and (c) at least filling the trench. As described above, after forming a non-dissolving SiO 2 film on the glass layer,
2. A step of laminating a glass layer having a good melting property on (2), and (d) flattening after high temperature annealing and performing dry etching or wet etching until the Si 3 N 4 film is exposed to form a non-soluble SiO in the trench. 2 When forming an element isolation region by embedding two films, a non-soluble Si embedded in a trench with a wide opening
A method of manufacturing a semiconductor device, comprising the steps of (c) and (d) are sequentially repeated at least once until the step of the O 2 film is eliminated, thereby filling the trench.
レンチのアスペクト比を低減しうるＰｏｌｙ−Ｓｉ膜を
有する請求項１による半導体装置の製造方法。2. The method of manufacturing a semiconductor device according to claim 1, wherein the trench having a narrow opening has a Poly-Si film capable of reducing an aspect ratio of the trench at a bottom thereof.
ＳＧ層又はＰＳＧ層である請求項１による半導体装置の
製造方法。3. The good-melting glass layer is a BPSG layer, B
The method for manufacturing a semiconductor device according to claim 1, wherein the method is an SG layer or a PSG layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21353491A JP2815255B2 (en) | 1991-08-26 | 1991-08-26 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21353491A JP2815255B2 (en) | 1991-08-26 | 1991-08-26 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0555360A true JPH0555360A (en) | 1993-03-05 |
| JP2815255B2 JP2815255B2 (en) | 1998-10-27 |
Family
ID=16640782
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21353491A Expired - Fee Related JP2815255B2 (en) | 1991-08-26 | 1991-08-26 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2815255B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0532361A2 (en) * | 1991-09-13 | 1993-03-17 | Nec Corporation | Method of manufacturing semiconductor device |
| US6265281B1 (en) * | 1997-08-18 | 2001-07-24 | Micron Technology, Inc. | Method for forming dielectric within a recess |
| US6872631B2 (en) | 2000-09-21 | 2005-03-29 | Nec Electronics Corporation | Method of forming a trench isolation |
-
1991
- 1991-08-26 JP JP21353491A patent/JP2815255B2/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0532361A2 (en) * | 1991-09-13 | 1993-03-17 | Nec Corporation | Method of manufacturing semiconductor device |
| EP0532361A3 (en) * | 1991-09-13 | 1995-03-22 | Nippon Electric Co | |
| US6265281B1 (en) * | 1997-08-18 | 2001-07-24 | Micron Technology, Inc. | Method for forming dielectric within a recess |
| US6872631B2 (en) | 2000-09-21 | 2005-03-29 | Nec Electronics Corporation | Method of forming a trench isolation |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2815255B2 (en) | 1998-10-27 |
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