JPH0554693A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To prevent a reduction in the yield caused by an increased power consumption due to a short-circuit between a bit line and a word line. CONSTITUTION:When a power supply is turned on, a redundant decision signal YR and a failure address A30 are generated from a failure address decision circuit 30. A Y address decoder 24 decodes the failure address A30 from an address selecting circuit 31 and the decoded results are given to a transfer gate 23 and a redundant latch circuit 32. By this arrangement, the redundant latch circuits 32, which are provided to failed bit line pairs BL1a, BL1b,..., are selected and switches 33a and 33b are turned off by the redundant latch circuit 32 while the power supply is turned on. Therefore, the leak current, which flows from an equalizer 21 to a word line WL1 through the failed bit line pair BL1a, BL1b,... and a memory cell-1, is shut off.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a dynamic RAM.
Semiconductor memory devices such as (random access memory),
In particular, the present invention relates to a semiconductor memory device that suppresses an increase in power consumption during standby (waiting period) caused by a short circuit between a word line and a bit line.

[0002]

2. Description of the Related Art Conventionally, as a semiconductor memory device of this type, for example, there is one as shown in FIG. The configuration will be described below with reference to the drawings. FIG. 2 is a circuit diagram of a main part showing a configuration example of a conventional semiconductor memory device, for example, a dynamic RAM.

This semiconductor memory device has a row address
, WLn activated by a control signal such as a strobe signal, and a plurality of bit line pairs BL1a, BL1 crossed with the word lines WL1, WL2 ,.
, b, ... And a plurality of memory cells 1-1, 1-2 ,. In each of the memory cells 1-1 to 1-n, the drain or the source and the gate have a bit line pair BL1a, BL1b, ...
And a field effect transistor (FET) 1a connected to the word lines WL1 to WLn, a source or a drain of the FET 1a, and a reference potential VR (for example, a power supply potential VCC.
Of the capacitor 1b connected to
Each is configured.

In this semiconductor memory device, word lines WL1, WL2, ..., W are decoded by decoding an access X address.
An X address decoder 10 for selecting Ln is provided. On the output side of the X address decoder 10,
Based on the output, word lines WL1, WL2, ..., WLn
Is connected to the word line triber 11 for selecting and driving the signal line and the signal inversion inverters 12-1 to 12-n. The gates of the FETs 13-1 to 13-n connected between the word lines WL1 to WLn and the ground potential VSS are connected to the output sides of the inverters 12-1 to 12-n, respectively.

.. are connected to one end of each bit line pair BL1a, BL1b, ... For equalizing (equalizing) FETs 20 which are turned on and off by an equalizing signal EQ1. The other end of each bit line pair BL1a, BL1b, ... Is activated by an equalize signal EQ2 to set the bit line pair BL1a, BL1b, .. to a reference potential VR (eg, 1 / 2.VCC of the power supply potential VCC). Equalizers 21 for charging are connected to each other. Each equalizer 21 is composed of FETs 21a and 21b connected in series between each bit line pair BL1a, BL1b ,.
The connection points of the FETs 21a and 21b are connected to the reference potential VR, and their gates are commonly connected to the equalize signal EQ2.

Further, each bit line pair BL1a, BL1b,
A sense amplifier 22 which is activated by the sensor amplifier activation signals SAN and SAP and detects and amplifies a potential difference on the bit line pair is connected to the ... And a transfer gate 23 is connected to. Transfer gate 23
Is output from the Y address decoder 24 that decodes the access Y address, so that each bit line pair BL1a, BL1
.. 1b, ... and the complementary data lines DBa, DBb are cut off.
It is a circuit for connection. Further, the transfer gate 23 has a function of disconnecting each bit line pair BL1a, BL1b, ... And the data lines DBa, DBb when the logic "H" or "L" redundancy judgment signal YR is input. AN
It is composed of a D gate and a FET.

Next, the operation will be described. For example, a read operation of the data “1” stored in the memory cell 1-1 will be described.

In the standby mode, since the equalizing signals EQ1 and EQ2 are "H", the equalizing FET 20 is turned on and the bit lines BL1a and B1.
Conductivity with L1b, and F in the equalizer 21
ETs 21a and 21b are turned on, and bit line pair BL
The reference potential VR is applied to 1a and BL1b, and the bit line pair BL1a and BL1b is set to the initial state.

The reason for performing this initialization is that if the equalizing signal EQ1 is set to "H" and the equalizing FET 20 is turned on, even if the potentials of the bit lines BL1a and BL1b become equal, the bit will be affected by parasitic capacitance or the like. Since the line potential may deviate from the reference potential VR, the reference potential VR is applied by the equalizing signal EQ2 to correct the deviation.

When the equalizing signals EQ1 and EQ2 fall to "L", the equalizing FETs 20 and 21a and 21 are provided.
b is turned off, and the bit lines BL1a and BL1b are separated. After that, the output of the X address decoder 10 turns off the FET 13-1 and the word line driver 11 causes the word line WL1 to rise to "H".

When the word line WL1 rises, the FETs in the memory cells 1-1, ... Connected to the word line WL1.
1a is turned on, the data "1" stored in the capacitor 1b is output onto the bit lines BL1a, ..., And a minute potential difference is generated between the bit line pair BL1a, BL1b ,.
Then, in the sense amplifier 22 activated by the sense amplifier activation signals SAN and SAP, the bit lines BL1b, ...
Of the bit line BL1a, ...
The potential of is raised.

When the potential difference between the bit line pair BL1a, BL1b, ... Is amplified by the amplifying operation of the sense amplifier 22 as described above, the Y address decoder 24 operates, and the output thereof causes the transfer gate 23 to perform a selective operation, so that the bit The line pair BL1a, BL1b is connected to the data lines DBa, DBb, and the amplified potential difference on the bit line pair BL1a, BL1b is output to the data lines DBa, DBb.
Data is read.

After that, the equalizing signal EQ1 becomes "H", the FET 20 is turned on, and the bit line BL1a.
And BL1b are connected to have the same potential. At this time, FET
If only 20 is turned on, bit lines BL1a and B1
Even if the potential of L1b becomes equal, it may deviate from the reference potential VR. Therefore, in order to correct the deviation,
The equalize signal EQ2 also becomes "H" for a short time in synchronization with the rise of the equalize signal EQ1, and the bit lines BL1a,
The reference potential VR is applied to BL1b.

[0014]

However, the apparatus having the above structure has the following problems. In the standby state, the equalizing signals EQ1 and EQ2 are "H", and the bit line pair BL1a, BL1b, ... Is set to the reference potential VR by the equalizing FET 20 and the equalizer 21. Therefore, for example, when the word line WL1 and the bit line BL1a are short-circuited, as shown by the alternate long and short dash line in FIG. 2, the reference potential VR → the equalizer 21 → the bit line B.
L1a → word line WL1 → FET 13-1 → ground potential V
The current I flows from the reference potential VR to the ground potential VSS through the path SS, which increases power consumption during standby.

In this way, the bit line BL1a and the word line W are
When a short circuit occurs between L1, the memory cells 1-1, ... Connected thereto become defective memory cells, and accurate data access cannot be performed. Therefore, normally, in order to relieve such a defective memory cell, a plurality of redundant bit line pairs and redundant memory cells are provided in advance, and when the defective bit line pair BL1a, BL1b, ... Is selected, the redundant bit line is selected. Select a pair and select the defective bit line pair BL1a, BL
1b, ... And the redundant bit line pair are both sensed, but the defective bit line pair BL1a, BL1b ,.
Reading of data to b is prohibited, and data of the redundant bit line pair is read instead.

However, the bit line BL1a and the word line W
When a short circuit occurs between L1, the defective bit line pair B
Since it does not regulate the operation of L1a and BL1b,
Usually, it causes an increase in power consumption of about 200 μA to 1 mA. Such a short between the word line and the bit line is a defect that is relatively easy to occur.
The frequency of occurrence tends to increase as the integration degree of the dynamic RAM such as it increases. Therefore, if multiple shorts occur due to the improvement in integration,
Standard value of current consumption during standby (for example, about 1
mA), the semiconductor memory device itself becomes a defective product, and the yield decreases.

In order to prevent such a decrease in yield,
Even if the redundant bit line pair and the redundant memory cell as described above are provided and the defective bit line pair is relieved, the current I
The route of remains. Therefore, even if the redundant circuit takes measures to repair the defective bit line pair and the memory cell itself does not become defective, the short circuit causes the current consumption to exceed the standard value and the semiconductor memory device itself is treated as a defective product. Therefore, there is a problem that the yield decreases, and it is difficult to solve it.

The present invention provides a semiconductor memory device which solves the problem that the prior art has, that the yield decreases due to an increase in power consumption due to a short circuit between a bit line and a word line. is there.

[0019]

In order to solve the above-mentioned problems, the present invention provides a plurality of word lines and a plurality of pairs of bit lines which are arranged so as to cross each other, and an intersection of each of the word lines and the pair of bit lines. A plurality of memory cells connected to each other,
A semiconductor memory device comprising: a plurality of equalizers for precharging each bit line pair to a reference potential by an equalize signal; and an address decoder for decoding an access address to select the bit line pair,
The following means are provided.

That is, according to the present invention, a defective address determination circuit that outputs a redundancy determination signal and a defective address when power is turned on, based on previously stored defective address data, and the defective address instead of the access address when the power is turned on. An address selection circuit for selecting an address and supplying the defective address to the address decoder in a form capable of being decoded is provided. Further, a plurality of redundant latch circuits which are selected based on the redundancy determination signal and the output of the address decoder and output a latch signal during a power-on period, and each bit line between each equalizer and a memory cell based on the latch signal. A plurality of switches for disconnecting each pair are provided.

[0021]

According to the present invention, since the semiconductor memory device is configured as described above, the defective bit line pair is detected in advance by a test of the semiconductor memory device and the defective address data is stored in the defective address determination circuit. .. Then, when the power is turned on, the defective address determination circuit outputs the redundant determination signal to the redundant latch circuit and the defective address to the address selection circuit based on the stored defective address data. In the address selection circuit, when the power is turned on,
A defective address is selected in place of the normal access address, and the defective address is supplied to the address decoder in a decodable form.

The address decoder decodes the defective address and supplies the decoding result to the redundant latch circuit. Then, the redundant latch circuit provided in the defective bit line pair is selected, and the redundant latch circuit outputs the latch signal during the power-on period. Therefore, the switch provided in the defective bit line pair is turned off by the latch signal, the defective bit line pair between the equalizer and the memory cell is cut off, and the equalizer flows to the memory cell through the defective bit line pair. The leakage current is cut off, and it is possible to prevent an increase in unnecessary current consumption during the power-on period.
Therefore, the above problem can be solved.

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a circuit diagram of a main part of a semiconductor memory device, for example, a dynamic RAM showing an embodiment of the present invention.
Common reference numerals are given to elements common to the conventional elements in FIG.

In this semiconductor memory device, the conventional device of FIG. 2 is provided with a defective address determination circuit 30 and an address selection circuit 31, and each bit line pair BL1a, BL1.
1b, ... Redundant latch circuit 32 and FE for switch
T33a and T33b are added respectively.

The defective address determination circuit 30 stores defective address data detected by a test of the semiconductor memory device in advance, and inputs the defective address generation signal A of "H" or "L" generated at power-on. , The redundancy judgment signal YR of “H” or “L” based on the defective address data is transferred to the transfer gate 23 and each redundancy latch circuit 3.
It is a circuit that outputs the defective address A30 to the address selection circuit 31 while outputting the defective address A30 to the address selection circuit 31. The address selection circuit 31 operates according to the defective address generation signal A,
The defective address A30 input at power-on is converted into a code that can be decoded by the Y address decoder 24,
This circuit supplies the address decoder 24 with the Y address YAD which is supplied to the Y address decoder 24 during normal access.

The redundant latch circuit 32 provided for each bit line pair BL1a, BL1b, ... Has its input side connected to the output side of the redundancy judgment signal YR and Y address decoder 24, and the redundancy judgment signals YR and Y address. Decoder 24
It is a circuit which is selectively driven based on the output of and outputs the latch signal L32 during the power-on period. Also, each bit line pair B
FE for switches provided for each of L1a, BL1b, ...
T33a, 33b, ... Are each bit line pair B between each equalizer 21 and memory cell 1-1, 1-2, ..., 1-n.
, L1a, BL1b, ... Based on the latch signal L32, each equalizer 21 and the memory cells 1-1 to 1-n.
It has a function of disconnecting each bit line pair BL1a, BL1b, ... Between them.

Next, the operation will be described. For example, assume that the word line WL1 and the bit line BL1a are short-circuited. This short-circuited portion is detected in advance by a test of the semiconductor memory device, and its defective address data is stored in the defective address determination circuit 30 in advance.

The operation of reading the data "1" stored in the memory cell 1-1 will be described below.

When the semiconductor memory device is powered on for reading data, the defective address generation signal A is input to the defective address determination circuit 30 and the address selection circuit 31 by a circuit (not shown) when the power is turned on. In the defective address determination circuit 30, when the defective address generation signal A is input, the redundancy determination signal YR and the defective address A30 are generated based on the defective address data stored in advance, and the redundancy determination signal YR is supplied to each bit line. The voltage is supplied to the redundant latch circuit 32 provided for each pair and also to the address selection circuit 31.

The address selection circuit 31 operates by the input of the defective address generation signal A, converts the defective address A30 from the defective address determination circuit 30 into a code which can be decoded by the Y address decoder 24, and the code is converted into the Y code. It is sent to the address decoder 24. Y address decoder 2
4 decodes the code from the address selection circuit 31 and selects the redundant latch circuit 32 provided in the defective bit line pair BL1a, BL1b. Then, the redundant latch circuit 3 provided in the defective bit line pair BL1a, BL1b.
2 outputs the latch signal L32 and F
The ETs 33a and 33b are turned off. As a result, the defective bit line pair BL1a, BL1b is cut off, and the equalizer 21 causes the memory cell 1-1, the word line WL1, and F to be disconnected.
A leak current I flowing to the ground potential VSS via the ET 13-1 is prevented, and an increase in power consumption due to the short circuit is suppressed.

When the defective address generation signal A is input to the defective address determination circuit 30 and the redundancy determination signal YR is output from the defective address determination circuit 30 as described above, the redundancy determination signal YR is used to generate a redundancy not shown. The redundant bit line pair in the circuit is selected, and the data "1" in the redundant memory cell corresponding to the memory cell 1-1 is read.

At the time of normal access, X address XAD
Is supplied to the X address decoder 10, the Y address YAD is supplied to the address selection circuit 31, the X address XAD is decoded by the X address decoder 10, and the word line driver 1 is based on the decoding result.
1 selects and drives one of the word lines WL1, WL2, ..., WLn. At the same time, the Y address YAD is selected by the address selection circuit 31 and the Y address decoder 2 is selected.
., And any one of the bit line pairs BL1a, BL1b, ... Is selected by the Y address decoder 24, and the selected bit line pair BL1a, BL1b ,.
The read data detected and amplified by the upper sensor amplifier 22 is transferred via the transfer gate 23 to the data line DBa,
It is output to DBb.

As described above, in this embodiment, when the power is turned on, the redundant latch circuit 32 provided in the defective bit line pair BL1a, BL1b, ... Is selected by the output of the redundancy judgment signal YR and the Y address decoder 24. During the power-on period, the redundant latch circuit 32 outputs the latch signal L32 to turn off the FETs 33a and 33b to cut off the defective bit line pair BL1a and BL1b. As a result, the bit lines BL1a, BL1 in which the short-circuited portion has occurred
The leak current I from b, ... To the word lines WL1 to WLn can be cut off, an increase in current consumption caused by a short circuit between the word lines and the bit lines can be suppressed, and the yield can be improved.

The present invention is not limited to the above embodiment,
Various modifications are possible. Examples of such modifications include the following. (A) In the address selection circuit 31 of FIG. 1, after converting the defective address A30 from the defective address determination circuit 30 into a code that can be decoded by the Y address decoder 24,
The configuration is such that the Y address decoder 24 is supplied to the Y address decoder 24.
The coded defective address A30 that can be decoded by (3) may be output and supplied to the address selection circuit 31, and the address selection circuit 31 may simply select the defective address A30 and supply it to the Y address decoder 24.

The address selection circuit 31 inputs the defective address generation signal A to perform the switching operation. However, when the defective address A30 is input, the defective address A30 is selected and supplied to the Y address decoder 24. The configuration may be changed.

(B) The FETs 33a, 33b, ... Which cut off the defective bit line pair may be composed of switches using other transistors or the like.

(C) In FIG. 1, all are configured to operate in positive logic, but by changing the polarity of the transistor or the polarity of the power supply, the circuit configuration of negative logic or a combination of positive logic and negative logic is used. Even with the circuit configuration described above, the same operation and effect as in the above embodiment can be obtained. In addition, the memory cell 1-
1, 1-2, ..., 1-n are composed of cells of one-transistor type, but they may be composed of other circuits such as two-transistor type.

[0038]

As described in detail above, when power is turned on, the redundant latch circuit provided in the defective bit line pair is selected based on the defective address data stored in advance in the defective address determination circuit, and the power is turned on. During the period, the defective bit line pair is cut off by a switch. for that reason,
When a short circuit occurs between a word line and a bit line, it is possible to prevent a leak current flowing from the equalizer to the word line via the defective bit line pair and the memory cell, and to properly prevent the occurrence of a defect due to the standard value of power consumption during standby. Therefore, it is possible to provide a semiconductor memory device with a high yield in which defective products are suppressed.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a main part of a semiconductor memory device showing an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a main part of a conventional semiconductor memory device.

[Explanation of symbols]

1-1, 1-2, ..., 1-n Memory cell 10 X address decoder 21 Equalizer 22 Sense amplifier 23 Transfer gate 24 Y address decoder 30 Defective address determination circuit 31 Address selection circuit 32 Redundant latch circuit 33a, 33b FET (switch) ) BL1a, BL1b bit line WL1 to WLn word line EQ1, EQ2 equalize signal A defective address generation signal A30 defective address XAD X address YAD Y address YR redundancy determination signal

Claims (1)

[Claims] 1. A plurality of word lines and a plurality of pairs of bit lines which are arranged to intersect each other, a plurality of memory cells which are respectively connected to the intersections of the word lines and the pair of bit lines, and each of which is formed by an equalizing signal. In a semiconductor memory device including a plurality of equalizers for precharging bit line pairs to a reference potential and an address decoder for decoding an access address to select the bit line pairs, defective address data stored in advance A defective address determination circuit that outputs a redundancy determination signal and a defective address when the power is turned on; and the address decoder that can select the defective address instead of the access address when the power is turned on and decode the defective address. An address selection circuit for supplying the redundancy judgment signal and the address decoder A plurality of redundant latch circuits that are selected based on the output and output a latch signal during the power-on period; and a plurality of switches that disconnect each bit line pair between each equalizer and the memory cell based on the latch signal A semiconductor memory device characterized by the above.