JP2002279793A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory in which a time required for activation of address buffer output to selection of a word line. SOLUTION: This device is a semiconductor memory consisting of a plurality of memory cells arranged along a row and a column, word lines connected to all rows are pre-charged (standby state) based on specification of a row address externally specified, that is, activation of address buffer output, simultaneously, redundancy discrimination operation and address decoding operation are started in parallel. In accordance with the redundancy discrimination result, a word line corresponding to a redundant row or a word line selected by address decoding operation is discharged selectively (activation state).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device such as a DRAM, and more particularly to a semiconductor memory device including a redundant row.

[0002]

2. Description of the Related Art With the recent increase in the size of semiconductor memory devices, redundant memory cells are prepared in addition to regular memory cells, and when a memory cell has a defect, the defective cell is replaced with a redundant cell. A method for relieving a defective chip is widely used. FIG. 1 is a circuit diagram of a conventional semiconductor memory device including a redundant row.

Here, the conventional semiconductor memory device 10 includes a plurality of memory cells 312 <0, 0> to 312 <n, m> (hereinafter abbreviated as 312) and redundant memory cells 312 <0, R> to 312 <. n, R> are arranged in a matrix in a memory array 300 <0> to 300 <j>
Main word lines / MWL0 to / MW controlled to be in standby (precharge) or activated (discharge) state based on external row address information
Ln (hereinafter abbreviated as / MWL) and a redundant main word line activated (discharged) when accessing a redundant cell
A row decoder 200 having / RMWL and a column decoder 100 having column lines CL0 <0> to CLn <j> (hereinafter abbreviated as column lines CL) controlled to be in a standby or activated state based on external column address information. Is done. Here, a device called a row or column decoder decodes an external address and selects a control line (word line) connected to a corresponding memory cell from among memory cells arranged along an actual row or column. Means for providing selection means for making data accessible. The memory array 300 includes a plurality of bit line pairs 313 <0> to 313 <n> (hereinafter, bit line pairs 313 <0> to 313 <n>).
And the word line WL0 <
0> to WLm <0> (hereinafter abbreviated as WL), redundant word line RWL <0>
(Hereinafter abbreviated as RWL), a memory cell 312 connected to the intersection of one of the bit line pairs 313 and WL and RWL to store information, and a memory cell 31 connected to each bit line pair 313 and storing information.
Sense amplifiers 311 <0> to 311 <n> that detect and amplify small signals of stored information from 2 (hereinafter abbreviated as sense amplifier 311)
And the column switches 310 <0> through 310 that are selected by the column line CL and connect the bit line pair 313 to the data buses DB and / DB.
310 <n> (hereinafter abbreviated as column switch 310). WL and RWL receive the outputs / MWL and / RMWL of the row decoder as inputs, and have inverters 314 <0> to P-MOS301 each having a source connected to Vpp and an N-MOS302 having a source grounded.
314 <m> and 314 <R> (hereinafter abbreviated as inverter 314). Vpp is used to maximize the amount of information stored in the memory cell at a boosted potential slightly higher than Vdd by the threshold value of the N-MOS.

FIG. 2 shows a detailed circuit of a row decoder 200 included in the conventional semiconductor integrated circuit 10 of FIG.
Here, the row decoder 200 is a complementary signal at the output of the address buffer for detecting and amplifying the external row address.
0, AX0 to / AXn, Decoder 201 <0> whose output is selectively controlled based on information of AXn (hereinafter referred to as / AX, AX)
And 201 <m> (hereinafter abbreviated as 201), a redundancy determination circuit 205 for storing address information of a defective cell, comparing the stored address information with external row address information, and determining whether or not to replace the defective cell. A decoder activation circuit 204 for controlling activation of the decoder 201 based on output information of the redundancy judgment circuit 205; a redundancy decoder 206 whose output is controlled based on output information of the redundancy judgment circuit 205; Level shifters 202 <0> to 202 <m> and 202 <R> (hereinafter abbreviated as level shifter 202) for converting the output level of the redundant decoder 206 from Vdd to Vpp level; Are composed of drive stages 203 <0> to 203 <m> and 203 <R> connected to / MWL and / RMWL.

[0005] The decoder 201 has N-MOSs 11, 12 and 1 having / AX and AX as inputs and having a source and a drain connected in series to each other.
3, a P-MOS 14 that precharges the output 17 to Vdd by a precharge signal / PR (hereinafter abbreviated as / PR), and a P-MO that forms an H level potential holding circuit that holds a precharge potential.
It consists of S15 and inverter 16. The source of N-MOS11 is
The output of the decoder activation circuit 204 is connected to a redundant decoder precharge signal / XDE (hereinafter abbreviated as / XDE), and the drain of the N-MOS 13 is connected to the output 17.

The redundancy judgment circuit 205 includes fuses 54 to 59 for storing address information of defective cells, an N-MOS 61 having a drain connected to one terminal of the fuse, a gate connected to / AX, AX and a source grounded. To 66, a P-MOS 51 for precharging a redundancy judgment signal RE (hereinafter abbreviated as RE), which is its own output, to Vdd by / PR, and a P-MOS for crossing an H level potential holding circuit for holding a precharge potential. It comprises a MOS 52 and an inverter 53. The other terminals of the fuses 54 to 59 are commonly connected to RE. The defective address is stored by cutting the fuses 54 to 59 corresponding to each bit of the defective address, that is, electrically opening the fuses. This example shows a state in which the fuses 54, 56, and 58 are cut and the fuses 55, 57, and 59 are connected.

The decoder activating circuit 204 includes an inverter 45 having RE as an input, an N-MOS 44 having an output of the inverter 45 as a gate input, a drain connected to / XDE, and a source grounded. It comprises a P-MOS 41 for precharging XDE to Vdd, a P-MOS 42 and an inverter 43 constituting an H level potential holding circuit for holding a precharge potential.

The redundancy decoder 206 has an OR gate 78 having / AXn and AXn as inputs, an output of the OR gate as an input of a buffer 76 via a delay circuit 77, an output of the buffer 76 as a gate input, and a source grounded. N-MOS75 and source N-MOS
An N-MOS 74 connected to the drain of the transistor 75 and having a drain connected to the output 79 and a gate connected to the RE; a P-MOS 71 for precharging the output 79 to Vdd by / PR; and an H for holding the precharge potential. P-MO that constitutes the level potential holding circuit
It comprises S72 and an inverter 73.

The level shifter 202 is a P-MO having a source connected to Vpp and a drain and a gate cross-coupled to each other.
S21, S22, output 17 of decoder 201 and redundant decoder 206
An N-MOS 24 having an output 79 as a gate input, an inverter 25 having its own input connected to the gate of the N-MOS 24, and an N-MOS 23 having an output of the inverter 25 as a gate input. N
The drain of -MOS23 is connected to the drain of P-MOS21, and the source is grounded. The drain of the N-MOS 24 is connected to the output 26 together with the drain of the P-MOS 22, and the source is grounded.

The driving stage 203 is composed of an inverter composed of a P-MOS 31 and an N-MOS 32 which receives the output 26 of the level shifter 202 and supplies power from Vpp. The drains of the P-MOS 31 and the N-MOS 32 are commonly connected to / MWL and / RMWL. The operation of the semiconductor memory device 10 configured as described above and shown in FIG. 1 will be described. When an external row address is detected and amplified by an address buffer and its output / AX, AX is input to the redundancy judgment circuit 205, it is compared with defective address information stored in advance. Here, when a normal address, for example, an external address corresponding to / MWLl is input, the address buffer output is L level only for / AX0, H level for / AX1 to / AXn, A level
Only X0 transitions to the H level, and AX1 to AXn transition to the L level,
The N-MOSs 62, 63 and 65 are turned on, and the N-MOSs 61, 64 and 66 are turned off.
Therefore, the potential of RE is discharged to the ground via the fuse 55 and the N-MOS 62, that is, the state where the redundancy judgment is denied. Hereinafter, this state is referred to as normal access.

On the other hand, if information corresponding to the defective address is input to the external row address, for example, information corresponding to / MW0 is input, all of / AX0 to / AXn are at H level, and all of AX0 to AXn are at L level.
Level, N-MOS61, 63, 65 are on, N-MOS62, 64, 66
Turns off. Therefore, since RE and ground are electrically separated, RE precharged to Vdd level by / PR in advance
Is maintained at the H level, that is, the state where the redundancy judgment is recognized. Hereinafter, this state is referred to as redundant access.

FIGS. 3 and 4 show the row decoder 200 of FIG.
2 shows a time chart of each signal. FIG. 3 shows the case of normal access, and FIG. 4 shows the case of redundant access. Note that t1 indicates the total period of the redundancy judgment operation and the address decoding operation starting from the input of the information of / AX and AX. In the case of normal access, t2 indicates the main word line after the output of the decoder 201 is selected. Indicates a period until the redundant main word line is selected after the output of the redundant decoder 206 is selected in the case of the redundant access.

First, the operation at the time of normal access will be described. As shown in FIG. 3, when the output of the address buffer is activated, RE changes from H to L level. In response, the RE input to the decoder activation circuit 204 is
And the N-MOS 44 is turned on, so that / XDE precharged to Vdd level by / PR is discharged to L level. At this time, at the selected decoder 201 <1>, N-
Since the MOSs 11, 12, and 13 are all on, the output 17 precharged to the Vdd level by / PR is discharged to the L level. The N-MOS 24 is turned off in the level shifter 202 <1> to which the output 17 of the decoder 201 <1> is input. On the other hand, since the output 17 is inverted by the inverter 25 and input to the N-MOS 23, the N-MOS 23 is turned on to pull down the gate of the P-MOS 22 to the L level, and at the same time the P-MOS 26 is turned on and the output 26 of the level shifter is turned on. Transition from L to H level. Level shifter 2
The output 26 of 02 <1> is inverted from the driving stage 203 <1> and its own output / MWL0 transitions from H level to L level, and the inverter in each memory array which receives this main word line as input WLl <0> which is the output of 314 <0> through 314 <m>
WLl <n> also transitions from the L level to the H level and is activated.

On the other hand, in the redundant decoder 206, its output 79 maintains the H level. Because / AXn and AXn
Is activated, the output of the OR gate 78 becomes H level to turn on the N-MOS 75 via the delay circuit 77 and the buffer 76. However, since RE is L level and the N-MOS 74 is off, the redundant decoder The output 79 is electrically separated from the ground, and is for maintaining the H level precharged with / PR.

After the / AX and AX are activated and input to the redundancy judgment circuit 205, the delay circuit 77 compares the stored defective address information with the input address information to determine the level of RE. The delay time is set at an appropriate time and the output 79
Are provided so as not to be erroneously discharged from H level to L level. Since the next circuit block after the output 79 for maintaining the H level does not operate, the inverter 31 in each memory array to which / RMWL and this redundant main word line are input is used.
RWL <0> to RWL <j>, which are outputs of 4 <R>, are all maintained at L level and are not activated. When WLl <0> to WLl <n> are activated, the following memory read operation starts in each memory array 300. Information stored in the memory cells 312 corresponding to these word lines is read onto the bit line pair 313, activated at a predetermined timing, and amplified by the sense amplifier 310. Next, the output of the column decoder 100, for example, CL0 <0> is activated based on the external column address information, and the data on the bit line is transferred to the data buses DB and / DB via the column switch 310 <0>.

The operation at the time of redundant access in FIG. 4 will be described. At the time of redundant access, RE maintains the H level even if the address buffer output is activated. Therefore, RE
Decoder 201 <0>, level shifter 202 <0>, drive stage 20 to be selected corresponding to / MWL0 after / XDE
3 <0> is not activated at all / MWL0 maintains H level,
WL0 <0> to WL0 <n> of each memory array driven by the main word line also maintain the L level. On the other hand, in the redundant decoder 206, its output 79 transitions from H to L level. Because RE is H level and N-MOS74
Is on, and when / AXn and AXn are activated, the output of the OR gate 78 goes high and the delay circuit 77 and buffer
This is because the output 79 is discharged from the H level to the L level since the N-MOS 75 is turned on via the line 76. When / RMWL is activated via the next level shifter 202 <R> and the driving stage 203 <R>, RWL <0> to RWL <n> in each memory array driven by this redundant main word line are also Be activated. Each memory array 30 after the redundant word line is activated
The memory read operation in “0” is the same as in the normal access.

As described above, in the conventional semiconductor memory device, since the address decoding operation is started after the redundancy judgment by the redundancy judgment operation is determined, the word line is selected after the address buffer output is activated. There was a problem that the time until was long. Here, the redundancy judgment operation is an operation of comparing the defective address information in the redundancy judgment circuit with the information of the address buffer to determine the signal level of the redundancy judgment signal. The address decoding operation is
This is an operation of selecting one corresponding output line group from among the output line groups of the decoder based on the information of the address buffer input to the decoder after the decoder activation signal transitions to the L level.

[0018]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor memory device which reduces the time from activation of an address buffer output to selection of a word line.

[0019]

A semiconductor memory device according to the present invention is a semiconductor memory device comprising a plurality of memory cells arranged along rows and columns, wherein the rows correspond to externally designated addresses. Address holding means for holding a defective address corresponding to a row including a defective memory cell, the defective address holding means comprising a plurality of rows to be deleted and at least one of redundant rows not corresponding to the address; A redundancy determining means for determining whether or not the address matches the defective row address, a designated row selecting means for selecting a row corresponding to the address when the address is designated, and a designated row selecting means for selecting the row corresponding to the address. Redundant row selecting means for selecting a redundant row; and word line activating means for setting a word line for each row in a standby state or an activated state for controlling access of the memory cell in units of a row. , Triggered by the designation of the address,
A word line activation circuit that puts all of the word lines in a standby state, activates a word line corresponding to the selected row after waiting for a result of a mismatch determination by the redundancy determination unit and a result of row selection by the designated row selection unit. And a redundant word line activating means for setting a word line for each redundant row in a standby state or an activated state for controlling access to the memory cell in a row unit. The designation of the address causes the word line to be activated. In a standby state, and waits for a match determination result by the redundancy determination means and a redundancy row selection result by the redundancy row selection means to activate a word line corresponding to the selected redundancy row. Means.

[0020]

Embodiments of the present invention will be described in detail with reference to the accompanying drawings. Components having substantially the same function are denoted by the same reference numerals. FIG. 5 shows an embodiment of the present invention, and shows a configuration of the row decoder 290 of the semiconductor memory device 10 of the present invention. The configuration itself of the semiconductor memory device 10 is the same as that of the conventional example of FIG. 1, and the conventional row decoder 200 is replaced by a row decoder 290 according to the present invention. The row decoder 290 includes a plurality of decoders 201, a plurality of level shifters 202, a redundancy determination circuit 205, a main word activation circuit 207, a decoder activation circuit 208, a redundancy decoder 209, and a plurality of driving stages 213.
It is composed of Here, the plurality of decoders 201, the plurality of level shifters 202, and the redundancy judgment circuit 205 have the same configuration as the conventional example of FIG.

The main word activating circuit 207 receives RE as an input and outputs its own main word activating signal MWDE (hereinafter referred to as MWDE).
MWDE), / AXn, AXn
Gate 84 with the input as the input and a delay circuit with the output of the OR gate
83 and its own input via transfer gate 82,
The output comprises a buffer 85 connected to a redundant main word activation signal RMWDE (hereinafter abbreviated as RMWDE). The conduction of the transfer gate 82 is controlled by RE and MWDE, and one terminal is connected to the output of the delay circuit 83 and the other terminal is connected to the input of the buffer 85. The input of the buffer 85 has MWDE as a gate input and is connected to the drain of the N-MOS 86 whose source is grounded. After the activation of / AX and AX, the delay time is set to the time necessary for the level of RE to be determined in the redundancy judgment circuit 205, and the transfer gate 82 is set to the H level of the OR gate 84. Latch the output of RMWD
It is provided that E is not activated instantaneously.

The decoder activating circuit 208 is constituted by an inverter 46 having / PR as an input, and its output is connected to / XDE. The redundant decoder 209 has / AXn and AXn as gate inputs, each source is commonly connected to the output of the inverter 93 having / PR as input, and each drain is output.
N-MOSs 91 and 92 commonly connected to 79, a P-MOS 71 for precharging the output 79 to Vdd by / PR, a P-MOS 72 and an inverter 73 constituting an H-level current holding circuit for holding a precharge potential, Consists of The output of the inverter 93 is connected to a redundancy decoder activation signal / RXDE (hereinafter abbreviated as / RXDE).

The driving stage 213 uses the output 26 of the level shifter 202 as a gate input, connects the source to Vpp, and connects the drain to / MWL.
P-MOS31 connected to / RMWL and MWDE as their gate inputs via N-MOS34, the source is grounded, and the drain is
N-MOS32 connected to / MWL and / RMWL, and / MWL and / R
MWL as gate input, source grounded, drain N
-It is composed of an N-MOS 33 connected to the gate of the MOS 32, and P-MOSs 35 and 36 and an N-MOS 37 constituting an H level potential holding circuit. The conduction of the N-MOS 34 is controlled by the output 26 of the level shifter 202, and one terminal is connected to the MWDE and the other terminal is connected to the gate of the N-MOS 32. N-MOS33 is the output of level shifter 202
26 is at the L level, that is, provided that the gate potential of the N-MOS 32 is electrically floating when the N-MOS 34 is off, and that the N-MOS 32 is turned on and a DC current flows from Vpp to the ground. When / MWL and / RMWL are precharged to the H level and the N-MOS 34 is off, the gate potential of the N-MOS 32 is clamped to the L level. When the P-MOS31 and the N-MOS32 are both in the off state for a long time, the H-level potential holding circuit lowers the H level of / MWL and / RMWL, which are the outputs of the circuit, due to junction capacitance or transistor leak current. It is provided for the purpose of preventing such a situation.

FIGS. 6 and 7 show the operation of the row decoder of this embodiment. FIG. 6 shows a normal access, and FIG. 7 shows a redundant access. Note that t3 is / AX, A
The operation period of the address decoding starting from the input of the X information is shown. First, the operation at the time of normal access will be described with reference to FIG. As shown in FIG. 6, unlike the conventional example, / XDE immediately goes to L level when / PR transitions to H level, and the decoder 201 is activated. After this / AX, A
When X is activated, in the decoder 201 <1> selected by the designation of the external address, all the N-MOSs 11, 12, and 13 are turned on, and the output 17 of the decoder 201 <1> precharged to Vdd in advance is at the L level. To be discharged. Therefore, the output 26 of the level shifter 202 <1> becomes H level and the output stage 213 <
In 1>, the P-MOS 31 is turned off, but / MWLl is maintained at H level by the H level potential holding circuit. At this time, N-MOS34
Also transitions from off to on. On the other hand, redundancy judgment is performed by the redundancy judgment circuit 205 in parallel with the above-described decoder operation, and R
Since E changes to L level and is input to the main word line activation circuit 207, MWDE changes from L to H level. By the way, / AXn and AXn are activated and the output of the OR gate 84 becomes H
After the delay time set by the delay circuit 83, the input of the transfer gate 82 is set to the H level. Before that, the transfer gate 82 changes from the conductive state to the non-conductive state, and the output of the delay circuit 83 and the buffer 85 Input is electrically isolated. At the same time, N-MOS8 with H level MWDE as input
6 turns on and the input of the buffer 86 is maintained at L level, so that RMWD also maintains L level. The activated MWDE turns on the N-MOS 32 via the N-MOS 34 of the driving stage 213 <1>,
/ MWLl is pulled down from H to L level, that is, activated.

On the other hand, in the redundant decoder 209, / PR
Goes high, / RXDE goes low, and the redundant decoder 209 is activated. Thereafter, when / AX and AX are activated, the N-MOS 92 is turned on and the output 79 of the redundant decoder 209 precharged to Vdd is discharged to L level. Therefore, the output 26 of the level shifter 202 <R> becomes H level, and the P-MOS 31 is turned off in the output stage 213 <R>. At this time, the N-MOS 34 also transitions from off to on, but RMWDE is at L level, that is, since the redundant main word activation signal is off, the N-MOS 32 is kept off and / RMWL is at H level by the H level potential holding circuit. , Ie, the redundant main word line is not activated.

Next, the operation at the time of redundant access will be described with reference to FIG.
This will be described with reference to FIG. In this case, as shown in FIG.
In the main word activation circuit 207 to which RE is input because the signal is maintained at the level, the MWDE maintains the L level.
At this time, the transfer gate 82 is conductive and the N-MOS 8
6 is off and then / AX, AX is activated and OR gate 84
Becomes high, the output of the OR gate 84 is propagated through the delay circuit 83, the transfer gate 83, and the buffer 85, and changes the RMWDE from L to H level. On the other hand, / MW
In response to L0, the decoder 201 <0> and the level shifter 202 <0> are selected, and the N-MOS 34 in the driving stage 213 <0> transitions from off to on, but since the MWDE is at the L level, the N-MOS 34 Maintain the OFF state and maintain H level at / MWL0 by the H level potential holding circuit. On the other hand, with respect to / RMWL, the redundancy decoder and level shifter 202 <R> are activated and the N-MOS 34 transitions from off to on in the drive stage 213 <R> as described in the normal access. In this case, since RMWDE is at H level, that is, the redundant main word activation signal is on, the N-MOS 32 is turned on and / RMWL is pulled down from H to L level, that is, the redundant main word line is activated.

As described above, according to this embodiment, since the redundancy judgment operation and the address decoding operation are started in parallel in the row decoder, the operation from the activation of the address buffer output to the selection of the word line is performed. The time can be reduced as compared with the conventional case, and an improvement in access time of the semiconductor memory device can be expected. FIG. 8 shows a configuration of a first modification of the present invention.

Here, the row decoder 290 includes a plurality of decoders 201, a decoder activating circuit 218, and a redundant decoder 21.
9. It includes a plurality of level shifters 202 (not shown), a plurality of driving stages 213 (not shown), and a main word activation circuit 207 (not shown). Decoder activation circuit 218
Is a transfer gate 50 whose conduction state is controlled by an output obtained by inverting RMWDE and RMWDE by an inverter 48;
An N-MOS 49 that clamps one terminal of the transfer gate 50 to the ground level when WDE is at the H level,
An inverter 46 whose input is connected to the drain of
Buffer whose own input is connected to the input of inverter 46
47. One terminal of the transfer gate 50 is connected to / PR, and the other terminal is connected to the input of the buffer 47. The output of inverter 46 is connected to / XDE. The output of the buffer 47 is the decoder precharge signal /
Connected to PRX (hereinafter abbreviated as / PRX). Redundant decoder
219 is a transfer gate 95 whose conduction state is controlled by MWDE and an output obtained by inverting MWDE by an inverter 96,
An N-MOS 94 that clamps one terminal of the transfer gate 95 to the ground level when MWDE is at an H level;
An inverter 93 whose input is connected to the drain of
A buffer whose own input is connected to the input of the inverter 93
98, / AXn and AXn are each gate input, each source is commonly connected to / RXDE, and each drain is output 79
N-MOSs 91 and 92 and output 79 are connected to redundant decoder precharge signal / PRRX (hereinafter abbreviated as / PRRX).
It comprises a P-MOS 71 for precharging to Vdd, an H-level potential holding circuit composed of a P-MOS 72 and an inverter 73 and holding a precharge potential. One terminal of the transfer gate 95 is connected to / PR, and the other terminal is connected to the input of the buffer 98. The output of inverter 93 is connected to / RXDE. The output of buffer 98 is connected to / PRRX.

In the decoder 201, / PRX is connected to the gate of the P-MOS 14 for precharging the output 17 to Vdd.
FIGS. 9 and 10 show the operation of the row decoder in the first modification shown in FIG. FIG. 9 shows a normal access, and FIG. 10 shows a redundant access.

As shown in FIG. 9, during normal access, RMWDE is always at L level, and transfer gate 50 in decoder activation circuit 218 is always conductive.
Since / XDE and / PRX are always controlled by / PR and input to the decoder 201, the operation of the decoder 201 <1> is the same as the operation at the time of normal access in the embodiment of FIG. Therefore, the operation thereof will be described below focusing on the redundant decoder 219.

Until / AX, AX is activated and MWDE transitions to the H level, the transfer gate 95 is in a conductive state, so that / RXDE and / PRRX are controlled by / PR and the output 79
Is precharged to Vdd. When / PR changes to the H level, / PRRX changes to the H level and / RXDE changes to the L level to activate the redundant decoder. Thereafter, when / AXn and AXn are activated, the N-MOS 92 is turned on and the output 79 precharged to Vdd is discharged to the L level. After the redundancy judgment, when the WDE transitions to the H level, the transfer gate 95
Becomes non-conductive, electrically isolates / PR from the input of the buffer 98, and simultaneously pulls down the input of the inverter 93 to the ground level by the N-MOS 94. Receiving this / RXDE
Transitions to the H level and / PRRX transitions to the L level, so that the output 79 is precharged to Vdd. Therefore, the P-MOS 31 in the drive stage 213 <R> controlled by the output 79 is turned off once to interrupt the precharge of / RMWL, but is turned on again after the redundancy judgment to restart the precharge. Holds H level of RMWL.

Next, as shown in FIG. 10, in the case of the redundant access, the MWDE is always at the L level, the transfer gate 95 in the redundant decoder 219 is always conductive, and / RXDE and / PRRX are always Since the operation of the redundant decoder is controlled by / PR, the operation of the redundant decoder is the same as the operation at the time of the redundant access in the embodiment of FIG. 5, so the following focuses on the degoder 201 <0> selected with reference to FIG. The operation will be described below.

Until / AX and AX are activated and RMWDE transitions to the H level, the transfer gate 50 of the decoder activation circuit 218 is in a conductive state. Output of each decoder is V
Precharged to dd. When / PR transitions to H level
/ PRX becomes H level and / XDE becomes L level, and the decoder 201 is activated. Thereafter, when / AX and AX are activated, the N-MOSs 11, 12, and 13 in the decoder 201 <0> are turned on, and the output 17 precharged to Vdd is discharged to the L level. After the redundancy judgment, when RMWDE transitions to the H level, the transfer gate 50 of the decoder activation circuit 218 becomes non-conductive, and the input of the inverter 46 is grounded by the N-MOS 49 at the same time as the / PR and the input of the buffer 47 are electrically separated. Pull down to level. In response to this /
Since XDE transitions to the H level and / PRX transitions to the L level, the output 17 is precharged to Vdd. Therefore, in the driving stage 213 <0> controlled by the output of the decoder 201 <0>.
The P-MOS 31 is turned off once to interrupt the precharge of / MWL0, but after the redundancy judgment, it is turned on again to restart the precharge and keep the H level of / MWL0.

As described above, according to the modification shown in FIG. 8, after the address buffer output is activated, the once activated decoder and redundant decoder are used, and after the redundancy judgment, the decoder and the normal access are used in response to normal access or redundant access. Since either one can be made inactive, the H level potential holding circuit in the driving stage 213 is not required. Therefore, the number of circuit elements constituting the row decoder can be reduced to about the same level as in the conventional example of FIG. 2, and the chip area of the semiconductor memory device formed on silicon can be reduced.
The access time can be expected to be improved while maintaining the same level as in the conventional example.

FIG. 11 shows a configuration of the row decoder of the second modification. Here, the row decoder 290 is
11, a redundant decoder 229, a plurality of level shifters 212,
It comprises a decoder activating circuit 208, a plurality of driving stages 213 (not shown), and a main word activating circuit 207 (not shown). The decoder 211 has N-MOSs 11, 1 having / AX and AX as inputs and having a source and a drain connected in series to each other.
The source of the N-MOS 11 is connected to / XDE, and the drain of the N-MOS 13 is connected to the output 17.

The redundant decoder 229 has / AXn and AXn as gate inputs, each source is commonly connected to the output of the inverter 93 having / PR as input, and each drain is output.
The output of the inverter 93 is connected to / RXDE. Level shifter 212
N has gates of P-MOSs 21 and 22 whose sources are connected to Vpp and whose drains and gates are cross-coupled to each other, and the output 17 of the decoder 211 and the output 79 of the redundant decoder 229 are gate input
A drain of each of the N-MOSs 24 and 27 is commonly connected to an output 26 together with a drain of the P-MOS 22, and each of the sources is grounded. The drain of the P-MOS 21 is connected to the gate of the N-MOS 27.

Hereinafter, the operation of the second modification of FIG. 11 will be described. When / PR is at L level and / AX and AX are inactive, / XDE and / RXDE are at H level, the N-MOS 24 is turned on in the level shifter 212, and the output 26 is pulled down to L level. At this time, the N-MOSs 11, 12, and 13 in the decoder 211 and the N-MOSs 91 and 92 in the redundant decoder 229 are all off at this time.
Is precharged to Vpp to turn off the P-MOS 22. Then / PR
Goes to the H level, and when / XDE and / RXDE go to the L level, the N-MOS 24 is turned off, and the decoder 211 and the redundant decoder 21 are turned off.
9 is activated.

Thereafter, when / AX, AX is activated, / AX, AX
In the decoder 211 selected based on the information of
-The MOSs 11, 12, and 13 are turned on, and the output 17 is discharged from the Vpp level to the L level. On the other hand, the redundant decoder 229
, One of the N-MOSs 91 and 92 is turned on and the output 7
9 is discharged from the Vpp level to the L level. As a result, the N-MOS 27 is turned off and the P-MOS 22
Turns on, and the output 26 transitions from the L level to the H level.

As described above, also in the modification 2 in FIG. 11, the same functions as those of the decoder, the redundant decoder and the level shifter in the embodiment in FIG. 5 can be performed, and the number of circuit components can be reduced. A smaller chip area of the storage device can be realized, and an improvement in access time can be expected.

[0040]

As described above, according to the semiconductor memory device of the present invention, the redundancy judgment operation and the address decoding operation are performed in parallel, so that high-speed access is possible.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a conventional semiconductor memory device 10.

FIG. 2 is a circuit diagram showing a configuration of a row coder 200 of FIG.

FIG. 3 is a timing chart showing an operation of the row coder 200 of FIG. 1 at the time of normal access.

FIG. 4 is a timing chart showing an operation of the row coder 200 of FIG. 1 at the time of redundant access.

FIG. 5 is a block diagram illustrating a configuration of a row degoder 290 of a semiconductor memory device according to an embodiment of the present invention.

FIG. 6 is a timing chart showing an operation of the row decoder 290 in FIG. 4 at the time of normal access.

FIG. 7 is a timing chart showing an operation of the row decoder 290 in FIG. 4 at the time of redundant access.

FIG. 8 is a circuit diagram showing a configuration of a row decoder 290 according to a first modification of the present invention.

FIG. 9 is a timing chart showing an operation at the time of a normal access in a first modification of FIG. 6;

FIG. 10 is a timing chart showing an operation at the time of a redundant access according to the first modification of FIG. 6;

FIG. 11 is a circuit diagram showing a configuration of a row decoder 290 according to a second modification of the present invention.

[Brief description of reference numerals]

 10 Semiconductor memory device 100 Column decoder 200 Conventional row decoder 201 Decoder 202 Level shifter 205 Redundancy determination circuit 207 Main word activation circuit 208 Decoder activation circuit 209 Redundancy decoder 211 Decoder of first modification 212 Level shifter of first modification 213 Drive stage 218 Decoder activation circuit of Modification 1 219 Redundancy decoder of Modification 1 229 Redundancy decoder of Modification 2 290 Row decoder 300 Memory array 310 Column switch 311 Sense amplifier 313 Bit line pair 314 Inverter

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5L106 AA01 CC04 CC17 GG03 5M024 AA40 AA50 BB07 BB08 BB35 BB36 CC22 CC50 DD62 DD80 GG02 HH01 HH10 MM12 MM15 MM20 PP01 PP02 PP03 PP07

Claims (4)

[Claims] 1. A semiconductor memory device comprising a plurality of memory cells arranged along a row and a column, wherein the row does not correspond to a plurality of rows corresponding to an externally designated address and the address does not correspond to the address. Defective address holding means for holding a defective address corresponding to a row including a defective memory cell, the defective address holding means comprising at least one of the redundant rows, and whether or not the address matches the defective row address when the address is designated Redundancy determining means for determining a row, a designated row selecting means for selecting a row corresponding to the address when the address is specified, and a redundant row selecting means for selecting a redundant row when the address is specified, Word line activating means for setting a word line for each row for controlling access of the memory cell on a row basis to a standby state or an activated state, and In response to the designation, all of the word lines are put into a standby state, and the word line corresponding to the selected row is activated after waiting for the result of the mismatch judgment by the redundancy judgment unit and the result of the row selection by the designated row selection unit. And a redundant word line activating means for controlling the access of the memory cells on a row-by-row basis and for setting a word line for each redundant row to a standby state or an active state, and the designation of the address is triggered. All of the word lines are put into a standby state, and a word line corresponding to the selected redundant row is activated after waiting for a match determination result by the redundancy determination unit and a redundant row selection result by the redundant row selection unit. And a redundant word line activating means. 2. The semiconductor memory device according to claim 1, wherein said defective address holding means includes a number of fuses corresponding to the number of bits constituting said address. 3. The system according to claim 2, further comprising: a precharge signal generation unit configured to generate a precharge signal in accordance with the designation of the address, wherein the designated row selection unit includes: a plurality of output lines corresponding to each of the rows; Means for receiving a signal and selectively relaying the precharge signal in accordance with the result of the discrepancy determination in the redundancy determination means; and precharging all of the plurality of output lines in response to the relayed precharge signal. Means for charging, and means for discharging one of the plurality of output lines corresponding to the designation of the address, wherein the redundant row selecting means comprises: an output line corresponding to the redundant row; Means for receiving a signal and selectively outputting the precharge signal in accordance with a result of the match judgment by the redundancy judgment means; 2. The semiconductor memory device according to claim 1, further comprising: means for precharging said output line in response to an image signal; and means for discharging one of said output lines. 4. The designated row selecting means includes a plurality of decoders having output lines corresponding to each of the rows, each of the plurality of decoders being a first and a second transistor, and a source thereof. Are connected to one end of a power supply, and their first and second transistors have their gates and drains connected to each other in a crossing manner. One end is connected to the drain of the first transistor;
In the case of a decoder corresponding to the address specification,
Opening / closing means for selectively relaying a signal from the drain of the first transistor to the other end; a gate connected to the other end of the opening / closing means; a source connected to the other end of the power supply; A third transistor connected to the output line; a gate connected to the drain of the first transistor; a source connected to the other end of the power supply; and a drain connected to the output line together with a drain of the third transistor. The semiconductor memory device according to claim 1, further comprising: a fourth transistor to be used.