JPH0554674A - Substrate bias voltage circuit - Google Patents

Abstract

PURPOSE:To generate plural substrate bias voltages by a control from outside a semiconductor storage device. CONSTITUTION:The circuit is constituted of N channel MOS transistors 9-12, which are connected through plural diodes with the charging pump of the substrate bias voltage circuit, and plural N channel MOS transistors 17-20 for voltage control, which are connected in parallel with 9-12. Thus, from outside the semiconductor storage device, the substrate bias voltage is easily made programmable.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a substrate bias voltage circuit for generating a substrate bias voltage in a semiconductor memory device.

[0002]

2. Description of the Related Art FIG. 2 is a circuit diagram showing a conventional substrate bias voltage circuit. In the figure, 1 to 5 are CMOS inverter circuits, and FIG. 3 shows them in more detail. Normally, a CMOS inverter circuit has a P-channel MOS transistor Tr ₃ and an N-channel M as shown in FIG.
It is composed of an OS transistor Tr ₄ , and is connected to V _CC and V _SS , respectively, and is supplied with the source potential.
Further, in FIG. 2, 6 is a capacitor, and 7 and 8 are N-channel MOS transistors. The ring oscillator 20 is configured by serially connecting five stages of inverters 1 to 5.

Next, the operation will be described. It is generally well known that a ring oscillator can be constructed by connecting the inverters 1 to 5 serially in odd stages. The output of this ring oscillator is an N-channel MOS transistor Tr whose diode is connected to the capacitor 6.
₁ 7, and a Tr ₂ 8 charge pump circuit 30
Given to. The negative voltage used as a substrate bias voltage is generated from the drain end of Tr ₁ 7.
The maximum negative voltage V _BB generated from this circuit is

V _BB = 2│V _th │-V _CC (1)

The maximum substrate current I _BB given by

I _BB = f · C · V _CC (2)

Is given by Here, V _th is Tr ₁ , T
The threshold voltage of r ₂ , V _CC is the power supply voltage supplied to the substrate bias voltage generating circuit, f is the oscillation frequency of the ring oscillator, and C is the capacitance value of the capacitor 6.

[0008]

Since the conventional substrate bias voltage generating circuit is constructed as described above, the levels of the substrate bias voltage V _BB are the power supply voltage V _CC and the threshold value of the NMOS transistor of the charge pump circuit. It is uniquely determined by the voltage V _th . There is a problem that the power supply voltage V _CC and the substrate bias voltage V _BB are arbitrarily set and the substrate bias voltage is changed from the outside to accelerate the holding characteristic test of the semiconductor memory device.

The present invention has been made in order to solve the above problems, and the substrate bias voltage can be controlled from the outside of the semiconductor memory device, so that the holding characteristic of the semiconductor memory device can be tested in a short time. The purpose is to obtain a substrate bias voltage circuit that can be implemented.

[0010]

In the substrate bias voltage generating circuit according to the present invention, a plurality of diode-junction N-channel transistors are provided, and a means for controlling the substrate bias voltage is provided by means for controlling the transistors. It is a thing.

[0011]

The substrate bias voltage generating circuit according to the present invention has a plurality of diode-junction N-channel transistors, and the substrate bias voltage can be arbitrarily set by the transistors controlling the N-channel transistors. Therefore, the retention characteristic test of the semiconductor memory device is accelerated. You can do it.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a substrate bias voltage circuit according to an embodiment of the present invention. In the figure, 9 to 12 are N channels M
In OS transistors, all N transistors are diode connected, in series to each other between the output V _BB at the output node A and the substrate bias voltage circuit of the charge pump circuit body comprising the transistors Tr ₁ 7, Tr ₂ 8 It is connected. 13 to 16 are N-channel transistors for controlling the diode-connected transistors,
There are N and N input control signals (substrate bias voltage control signals) 17 to 20 are connected. The input control signals 17 to 20 are output by the control circuit 40 such as an address key circuit which receives the external addresses A _{0 to} A _n .

Next, the operation will be described. The address key circuit receives external address inputs A _{0 to} A _n , and outputs a plurality of control signals φ ₁ to φ ₄ depending on the combination. For example, since 13 to 16 are N-channel transistors, φ ₁ is Low, φ ₂ is Low, φ ₃ is Hi,
When φ ₄ is Hi, the N-channel transistors 13 and 14 are cut off and the N-channel transistors 15 and 16 are turned on. The N-channel transistors 13 to 16 are physically small in size, and the threshold voltage is also diode-connected to the transistors 9 to 1.
It shall be less than 2. Then, Now, when the voltage of the node A and -1 V, V _BB level becomes -1-2V _th. Further, when all the input signals of φ _{1 to} φ ₄ are in the low state, all N-channel transistors 17 to
20 is cut off, and the V _BB level is -1-nV _th
Becomes In this way, the N transistors of φ ₁ to φ ₄ that receive and generate the external addresses A _{0 to An} are turned on and off.
It is possible to generate N levels of V _{BB by} combining FFs.

In the above embodiment, N diode-junctioned N channel MOS transistors are connected in parallel with N N channel MOS transistors. However, N P channel MOS transistors may be used.
Only by changing the polarities of the N control signals of _{1 to} φ ₄ , the same effect as the above embodiment can be obtained.

[0015]

As described above, according to the present invention, a plurality of diode-connected transistors are connected to a charge pump circuit of a substrate bias voltage circuit, and a plurality of voltage controlling transistors are connected in parallel with the transistor. Therefore, it is possible to easily program a plurality of substrate bias voltages from the outside.

[Brief description of drawings]

FIG. 1 is a diagram showing a substrate bias voltage circuit according to an embodiment of the present invention.

FIG. 2 is a diagram showing a conventional substrate bias voltage circuit.

FIG. 3 is a diagram showing a configuration of a CMOS inverter circuit.

[Explanation of symbols]

 1 CMOS Inverter 2 CMOS Inverter 3 CMOS Inverter 4 CMOS Inverter 5 CMOS Inverter 6 Capacitor 7 N Channel Transistor 8 N Channel Transistor 9 N Channel Transistor 10 N Channel Transistor 11 N Channel Transistor 12 N Channel Transistor 13 N Channel Transistor 14 N Channel Transistor 15 N-channel transistor 16 N-channel transistor 17 Control signal generated by external address 18 Control signal generated by external address 19 Control signal generated by external address 20 Control signal generated by external address

Claims (1)

[Claims] 1. A substrate bias voltage circuit of a semiconductor memory device having a ring oscillator and a charge pump circuit, each of which is diode-connected between an output node of the charge pump circuit body and an output of the substrate bias voltage circuit. And a plurality of transistors connected in series with each other, and a plurality of transistors for voltage control, each transistor being connected in parallel with each of the above transistors and turned on or off in response to a substrate bias voltage control signal. A substrate bias voltage circuit characterized by the above.