JPH0554646A - Memory device and its dynamic ram refresh system - Google Patents

Abstract

PURPOSE:To reduce the degradation in performance of the whole of a system by allowing normal access to banks other than the target bank of refresh even at the time of divisional refresh of a dynamic RAM. CONSTITUTION:When a refresh request signal REFREQ is active and an even bank signal EB is in the low level at this time, a RAS&CAS control part 12 refreshes even banks BANK0 and BANK2 by row address strobe signals RASO and RAS2 and column address strobe signals CASO and CAS2. When the signal EB is in the high level then, odd banks BANKI and BANK3 are refreshed by signals RAS1 and RAS3 and signals CAS1 and CAS3. When even banks BANK0 and BANK2 are refreshed, odd banks BANK1 and BANK3 can be accessed by a CPU; and when odd banks BANK1 and BANK3 are refreshed, even banks BANKO and BANK2 can be accessed by the CPU.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory device using a dynamic RAM and a refresh method for the dynamic RAM.

[0002]

2. Description of the Related Art Dynamic RAM (hereinafter "DRAM")
A memory device using
In order to retain the data in the RAM, an operation called refresh must be performed within a fixed time. As this refresh mode, ras only refresh,
There are hidden refreshes and cast-before-last refreshes.

Among them, the ras-only refresh, which requires an external circuit for generating a refresh address, is often used for refreshing a DRAM because of its short refresh time and general circuit configuration.
The hidden refresh circuit has a complicated circuit configuration, but depending on the configuration of the memory device and an external circuit (such as a CPU) that accesses it, the refresh time can be executed without degrading the overall performance. Cass Before
In the last refresh, since an address is generated inside the DRAM device, an external circuit is simplified, but one refresh time becomes long.

[0004]

Conventionally, no matter which refresh mode is used, all the DRAMs are collectively refreshed when the performance of the entire system using the memory device is taken into consideration. However, if the total memory capacity is large and there is a problem with the power supply due to inrush current during refresh, etc., there are some that adopt the method of divided refresh by dividing into multiple groups. Is faster and the overall time required for refreshing is longer. As a result, the performance of the entire system had to be sacrificed.

The present invention has been made in view of the above points, and even if the refresh is divided, normal access can be made to other than the refresh target group, and the performance of the entire system is degraded. The purpose is to be able to reduce.

[0006]

In order to achieve the above object, the present invention provides a dynamic RAM having a CAS-before-refresh mode and its dynamic RA.
A circuit for outputting a row address strobe and a column address strobe to the dynamic RAM for each constitutional unit of M, and timings of the row address and the column address of the row address strobe and the column address strobe, respectively. The present invention provides a memory device having a circuit adapted to all dynamic RAMs or its constituent units.

Then, the plurality of dynamic RAM constituent units may be divided into a plurality of groups, each group may be refreshed at different times, and a group not in a refresh cycle may be normally accessed.

[0008]

According to the present invention, the row address strobe and the column address strobe are output to the dynamic RAM for each unit of the dynamic RAM, and the row address and the column address are respectively supplied to the row address strobe. Strobe and column address
Since all dynamic RAMs or their constituent units are given in conformity with the strobe timing, the constituent units of the plural dynamic RAMs are divided into a plurality of groups, and each group is refreshed and refreshed at different times. Groups that are not in cycle can allow normal access. Therefore, the efficiency of reading and writing data from and to the dynamic RAM is improved, and the current capacity required at the time of refresh is also reduced.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of the present invention will be specifically described below with reference to the drawings. FIG. 2 is a block diagram showing a configuration example of a microcomputer which is an embodiment of the present invention.

This microcomputer comprises a central processing unit (hereinafter abbreviated as "CPU") 1, ROM2 and RAM.
3, I / O 4, and each part thereof is connected to each other by a separate line composed of an address bus 5, a data bus 6, and a control bus (not shown).

The CPU 1 includes a ROM 2, a RAM 3, and an I / O.
Various arithmetic processes are performed based on the information from 4. ROM2
Stores programs and data. RAM3 is a memory device using a dynamic RAM.

Incidentally, as the type of RAM, there is a static RAM in addition to the dynamic RAM. A static RAM, which has a simple access time and a simple circuit configuration, is used for high-speed processing, but a dynamic RAM is generally used when a large capacity memory is required and cost is taken into consideration.

However, the dynamic RAM must time-division the address to be given to it and to give the corresponding signals of row address strobe (RAS) and column address strobe (CAS). Furthermore, since the refresh operation must be performed at regular time intervals, the circuit configuration becomes complicated and the performance of the entire system may deteriorate. Therefore, the RAM 3 used in this embodiment has a function for solving the problem. The I / O 4 has a function of setting a communication interface with the outside and a port for internal control.

FIG. 1 is a circuit diagram showing a configuration example of the RAM 3 (DRAM). In this embodiment, one bank is 1 megabyte and the total number of banks is four in order to simplify the description.

In this RAM 3, the address latch 1
Reference numeral 1 designates which bank of four banks (memory cell array) BANK0-BANK3 is selected by latching the address signals A0-A21 output on the address bus 5 by the CPU 1 by the address latch enable signal ALE. Addresses A20 and A21 shown are RAS &
The address is provided to the CAS controller 12 and the addresses A0 to A19 are provided to the address multiplexer 13.

The address multiplexer 13 is a RAS &
A column address enable signal CAE from the CAS control unit 12 selects one of the lower address (row address) A0 to A9 or the upper address (column address) A10 to A19 among the address signals A0 to A19. The RAM address signals RAMADR0 to 9 are output.

The read / write control unit 14 has a RAM enable signal RAMEN output from a decoding circuit (not shown).
And read / write signal R / W output from CPU1
Output enable signal O for controlling the reading of data from each bank BANK0-BANK3.
E and a write enable signal WE for controlling writing of data to each of the banks BANK0 to BANK3 are output.

The refresh controller 15 is a dynamic R
It has a timer counter that defines the AM refresh interval, and a refresh request signal REFREQ for notifying a refresh request, and an even indicating whether the bank to be refreshed is an even bank BANK0, BANK2 or an odd bank BANK1,3. -The bank signal EB is output. Further, after the signal REFREQ is activated, the refresh enable signal R is activated when the refresh request clear signal REFLR from the RAS & CAS controller 12 becomes active.
Inactivate EFREQ.

Now, in a general 1-megabit dynamic RAM, it is specified that a refresh operation is performed within 512 msec for 512 addresses. Therefore, if you want to refresh the dynamic RAM of the entire system at once, 8 mesc ÷ 512 ≒ 16μ
It is necessary to refresh each address every sec. However, in this embodiment, since it is divided into two,
The refresh operation must be performed for each address every 8 μsec.

FIG. 3 is a circuit diagram showing a configuration example of the refresh control section 15, and FIG. 4 is a timing chart showing the operation of each circuit. The refresh control unit 15 uses a counter when the basic clock CLK is set to 8 HMz, and includes ICs 21 to 23.

Then, the IC 21 to 23 makes the refresh request signal REFREQ active (low level) every 64 clocks (8 μsec) as shown in FIG. 4, and changes the level of the even bank signal EB every 64 clocks. The signal RE depending on the level
The bank to be refreshed when FREQ becomes active is determined. After the refresh request signal REFREQ becomes active, the active state is maintained until the refresh request clear signal REFLR becomes active (low level).

FIG. 5 shows the RAS & CAS control unit 12 of FIG.
3 is a circuit diagram showing a configuration example of FIG. In the RAS & CAS control unit 12, the bank selector 31 is a simple decoder, and if the RAM enable signal RAMEN is active, it determines which bank is to be accessed by the CPU 1 shown in FIG. 2 by the addresses A21 and A20. , One of the signals BANK0EN to BANK3EN is activated. If the signal RAMEN is inactive, the signals BANK0EN to BANK3EN
Inactivate all of.

The RAS & CAS generator 32 is a PLA
(Programmable logic array). The signal SYSCLK is a clock for causing the RAS & CAS generator 32 to function as a state machine, and the signal RESET is a signal for initializing the state machine and a power-on reset signal.

This RAS & CAS generator 32 is
When both the address latch enable signal ALE and the RAM enable signal RAMEN become active,
It is judged that the RAM is accessed by the CPU 1, and the internal normal access state machine is activated so that the signal RASEN corresponding to the signal RAS and the signal CASEN corresponding to the signal CAS can be output at the timing conforming to the standard of the dynamic RAM. Let

Then, the refresh request signal R
A CAS-before-lass-refresh cycle is initiated by activating the refresh state machine when EFREQ becomes active. The signals RAS and CAS at this time correspond to the signal REFRAS and the signal REFCAS, respectively. The above operation corresponds to the case where the access and the refresh request by the CPU 1 in FIG. 2 do not overlap.

Next, the operation corresponding to the case where the access request and the refresh request by the CPU 1 overlap each other will be described. In this embodiment, when the address signal A20 is low level during access by the CPU 1, even-numbered banks BANK0, 2 are targeted, and when high-level, the odd-numbered banks BANK1, 3 are targeted. If the even bank signal EB is at the low level, the even banks BANK0 and 2 are refreshed, and if the even bank signal EB is at the high level, the odd banks BANK1 and 3 are refreshed.

Therefore, the refresh hit signal REFH output from the exclusive OR gate 34
IT is the address signal A20 and the even bank signal EB.
Goes low when the banks indicated by match.

The RAS & CAS generator 32 has two state machines, a normal access state machine and a refresh state machine, and is in an idle state when no access is requested. Each state machine is activated only when another state machine is in the idle state when the refresh hit signal REFHIT is at the low level when the activation (transition from the idle state to another state) request is made.

However, when the access request and the refresh request by the CPU 1 are simultaneously generated, the refresh operation is prioritized. This is accomplished by the normal access state machine monitoring the state of the refresh state machine and the refresh request signal REFREQ, in addition to determining the access request by the CPU 1.

When the access by the CPU 1 becomes pending due to the refresh, the RAS & CAS generator 32 activates the signal BUSY to notify the CPU 1 or a wait control circuit (not shown) of that fact. On the other hand, refresh hit signal RE
When FHIT is at a high level, the access target bank and the refresh target bank of the CPU 1 are different, so that the access cycle and the refresh cycle of the CPU 1 can be performed simultaneously.

The RAS & CAS driver 33 is also composed of PLA. Since the output timings of the signals RAS and CAS are taken into consideration by the RAS & CAS generator 32, the RAS & CAS driver 33 only selects the output destination. Signal RASEN, CASEN
Is determined by the signals BANK0EN to BANK3EN.

That is, when the signal BANK0EN is active, the signals RASEN and CASEN are output as the signals RAS0 and CAS0, respectively, and when the BANK1EN is active, the signals RASEN and CASEN are output as the signals RAS1 and CAS1, respectively. Further, when the signal BANK2EN is active, the signals RASEN and CASEN are output as the signals RAS2 and CAS2, respectively, and when the BANK3EN is active, the signal RAS is output.
EN and CASEN are signal RAS3 and CAS3, respectively.
Output as.

When the even bank signal EB is at the low level, the signal REFRAS is output as the signal RAS0,2 and the signal REFCAS is output as the signal CAS0,2. When the even bank signal EB becomes high level, the signal REFRAS is changed to the signals RAS1 and 3, and the signal REF is changed.
The CAS is output as the signals CAS1 and CAS3.

[0034]

As described above, according to the present invention, since the dynamic RAM is divided and refreshed, the simultaneous operation of strobe signals such as RAS and CAS is reduced, which causes a problem of noise and power supply capacity due to inrush current. And the groups not in the refresh cycle can be accessed normally, so that the delay of the CPU access time due to the refresh operation is reduced.
The decrease in performance of the entire memory system using the dynamic RAM is reduced.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration example of a RAM 3 (dynamic RAM) of FIG.

FIG. 2 is a block diagram showing a configuration example of a microcomputer which is an embodiment of the present invention.

3 is a block circuit diagram showing a configuration example of a refresh control unit 12 in FIG.

FIG. 4 is a timing chart showing the operation of each circuit in FIG.

5 is a block circuit diagram showing a configuration example of a RAS & CAS control unit 12 in FIG.

[Explanation of symbols]

1 Central Processing Unit (CPU) 2 ROM 3 RAM 4 I / O 11 Address Latch 12 RAS & CA
S control unit 13 address multiplexer 14 read / write control unit 15 refresh control unit 21 to 23 IC 31 bank selector 32 RAS & CA
S generator 33 RAS & CAS driver BANK0-3 banks

Claims (2)

[Claims] 1. A dynamic RAM having a CAS-before-refresh mode and its dynamic RA.
A circuit for outputting a row address strobe and a column address strobe to the dynamic RAM for each unit of M, and a row address and a column address of the row address strobe and the column address strobe, respectively. A memory device having a circuit adapted to all timings for each dynamic RAM or its constituent units. 2. The memory device according to claim 1, wherein the plurality of dynamic RAM constituent units are divided into a plurality of groups, and each group is refreshed at different times.
Dynamic RAM refresh method characterized by enabling normal access to groups not in the refresh cycle.