JPH0554286B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a signal detection circuit, and particularly to a signal detection circuit that detects a signal by installing a comparator in a signal input section and comparing a reference level and an input signal. Regarding prevention of false positive detection.

FIG. 1 shows this type of signal detection circuit.
The input terminal 4A formed at the non-inverting input terminal (+) of the comparator 2 is given the signal to be detected, while the input terminal 4B formed at the inverting input terminal (-) is supplied with the voltage source 6. A comparison reference level V _REF is set. The output of the comparator 2 is applied to a waveform generating circuit 8 that generates a sawtooth wave, and the waveform generating circuit 8 is composed of a transistor 10, a resistor 12, and a capacitor 14, and its output is applied to a switching circuit 16. This switching circuit 16 has a transistor 22 installed via a resistor 20 between a power supply terminal 17 to which a drive voltage Vcc is applied and a reference potential point terminal 18.
The output of the waveform generating circuit 8 is given to the base of the , and the output is sent to the output terminal 2 formed at the collector.
It is taken out from 4.

According to such a signal detection circuit, a pulse having a pulse width given in a range where the signal amplitude level exceeds the reference level V _REF is output from the comparator 2,
During the period of that pulse width, the transistor 10
is conductive and is non-conductive during other periods, and in response to this switching operation, the capacitor 14 is repeatedly charged and discharged, and the transistor 2
A sawtooth voltage is formed at the base of 2. To the extent that this sawtooth voltage exceeds the threshold level of the transistor 22, an output voltage is generated at the collector, and the voltage output can be taken out from the output terminal 24.

Figure 2 shows the operating waveforms from turning on the power switch to steady state operation, and Figure 2A shows the power supply voltage.
The rising waveform of Vcc, Figure 2B shows the input signal waveform to the input terminal 4A of the comparator 2, and in B, S indicates a transient sound signal (pop sound signal) other than the signal to be detected that occurs when the power is turned on. ing.
When such a signal S arrives and its signal level exceeds the reference level, comparator 2 produces an output, as shown in FIG. 2C. This output is detected by the waveform generation circuit 8, and as shown in FIG. 2D,
A corresponding sawtooth voltage is generated, and the voltage shown in FIG. 2E is generated at the output terminal 24. In this case, among the outputs shown in E, the voltage output in section T indicates a malfunction portion due to a transient sound signal.

If such a malfunction occurs, the control system or signal system on the output side will malfunction.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a signal detection circuit that prevents malfunctions in signal detection caused by transient signals caused by a transient state when power is turned on.

That is, the signal detection circuit of the present invention includes a comparator 2 that compares an input signal with a reference level and generates an output depending on the magnitude relationship between the two, and a first resistor 12 between the power supply and the reference potential point. and a capacitor 14 connected in series, and a capacitor connected in parallel between the collector and emitter of the first transistor 10 to which the output of the comparator is applied to the base via a second resistor 26 for switching. a waveform generating circuit 8 that generates a waveform by controlling the capacitor to be charged or discharged by switching the first transistor according to the output of the comparator; and the capacitor of this waveform generating circuit. A signal detection circuit comprising: a second transistor 22 that receives and switches a charging voltage based on a charging voltage; and a first switching circuit 16 that generates an output in accordance with the switching of the second transistor. a frequency divider circuit 28 which divides the frequency of the output generated by the comparator; the output of this frequency divider circuit is input to a set input; a reset pulse upon power-on is received to a reset input for switching;
A flip-flop circuit 36 that generates an output, and a collector of a third transistor 40 that receives the output of the flip-flop circuit at its base and becomes conductive, are connected to the base of the first transistor, and the emitter of the third transistor is connected to the base of the third transistor 40. The emitters of the first transistors are connected in common, and the bases of the first transistors are forcibly shifted to a non-conducting level by making the second transistor conductive in accordance with the output of the flip-flop circuit, thereby forming the waveform. The present invention is characterized in that it includes a second switching circuit 38 for canceling the output of the generating circuit.

Hereinafter, the present invention will be described in detail with reference to embodiments shown in the drawings.

FIG. 3 shows an embodiment of the signal detection circuit of the present invention, and the same parts as those of the signal detection circuit shown in FIG. 1 are given the same reference numerals. In the figure, a capacitor 14 connected to a power supply via a first resistor 12 is installed in the waveform generating circuit 8.
A first transistor 10 is connected in parallel between the terminals of the transistors 4 and 4. The output of comparator 2 is connected to second resistor 2
6 to the base of transistor 10. A capacitor 14 connected between the collector and emitter of the transistor 10 is charged through the first resistor 12 when the transistor 10 is non-conducting, and when the transistor 10 is connected to the comparator 2.
When conductive by the output of transistor 10
is discharged through. A sawtooth voltage is formed in the capacitor 14 by charging and discharging the capacitor 14 by switching the transistor 10. The sawtooth voltage generated in the capacitor 14 is applied to the base of the transistor 22 of the first switching circuit 16.

Further, the output of the comparator 2 is given to a frequency dividing circuit 28 as a counting circuit. The frequency dividing circuit 28 is T
It is composed of flip-flop circuits 30 and 32, and each T flip-flop circuit 30 and 32 constitutes a frequency dividing circuit that divides the frequency of an input pulse by two.
The output of the comparator 2 is applied to the trigger input T of the T flip-flop circuit 30, and the inverted output of the T flip-flop circuit 30 serves as the trigger input T of the T flip-flop circuit 32. As a result, the frequency divider circuit 28 becomes 1/ It is configured to generate a frequency divided by 4 output. A common reset terminal 34 is formed at the reset terminal R of each T flip-flop circuit 30, 32, and a reset pulse is applied at the same time as the power is turned on.

An SR flip-flop circuit 36 is installed on the output side of the frequency divider circuit 28, and a set input S of the SR flip-flop circuit 36 is supplied with the non-inverting output Q of the T flip-flop circuit 32.
A reset pulse is applied to the reset input R from the reset terminal 34.

Further, between the base of the transistor 10 of the waveform generation circuit 8 and the reference potential line, there is a second switching circuit 38 that controls the operation of the waveform generation circuit 8 in response to the output of the SR flip-flop circuit 36.
is installed. This switching circuit 38 is composed of a third transistor 40, and the inverted output of the SR flip-flop circuit 36 is applied to the base of this transistor 40.

The operation of the above configuration will be explained in detail with reference to FIG. In FIG. 4, H indicates a high level section and L indicates a low level section.

4A shows the power-on state, and FIG. 4B shows the input signal applied to the input terminal 4A, where V _REF is the reference voltage level applied to the input terminal 4B by the voltage source 6, and S is the reference voltage level applied to the input terminal 4B. This is a transient sound signal, that is, a pop sound signal, which is generated in a transient state when the power is turned on and is given before signal input.

FIG. 4C shows the output pulse of comparator 2, the output pulse has a pulse width in the section where the amplitude level of the input signal exceeds the reference voltage level, and
A corresponding pulse is also generated.

T flip-flop circuit 30 of frequency divider circuit 28,
32 and the SR flip-flop circuit 36 are supplied with a reset input from the reset terminal 34 in response to the power being turned on, and are shifted to the reset state at the same time as the power is turned on. In this state, the output pulses of the comparator 2 are sequentially applied to the T flip-flop circuit 30 of the frequency divider circuit 28, and FIG. 4D shows the inverted output of this flip-flop circuit 30.
This is the frequency-divided output of the comparator 2, and this output is applied to the T flip-flop circuit 32. FIG. 4E shows the non-inverted output Q of the T-flip-flop circuit 32, which constitutes the frequency-divided output of the T-flip-flop circuit 30.

This output Q is given to the SR flip-flop circuit 36, and the SR flip-flop circuit 36 shifts to the set state, but since it is placed in the reset state at the same time as the power is turned on, its inverted output is applied to the T flip-flop circuit 32 from the time the power is turned on. During a predetermined period of time until the inverted output is generated, it becomes high level and generates the output shown in FIG. 4F.

Therefore, during a certain period of time after the power is turned on, that is, until the time when the frequency divider circuit 28 starts counting the second pulse, the transistor 4
0 is in a conductive state, the operation of the waveform generating circuit 8 is stopped, and the detection of the output pulse of the comparator 2 is cut off.

Then, at the same time as the above-mentioned time ends, the switching circuit 38 becomes non-conductive, and the transistor 10 becomes non-conductive.
A pulse shown in FIG. 4G corresponding to the pulse shown in FIG. 4C is input to the base of transistor 1.
0 repeats the switching operation in response to the input pulse of the comparator 2, and a sawtooth voltage shown in FIG. 4H is generated at the base of the transistor 22. During the period in which this sawtooth voltage does not exceed the threshold level V _SH of the switching circuit 16, the collector voltage of the transistor 22 maintains a constant high level, and this voltage output becomes as shown in FIG. 4I.
This can be taken out from the output terminal 24 as a signal detection output.

In this way, since the operation of the waveform generation circuit 8 is stopped for a certain period of time after the power is turned on, it is possible to avoid detection of pop sound signals in the transient state when the power is turned on, and highly reliable signal detection can be performed. ,
Malfunctions caused by pop sound signals can be prevented.

FIG. 5 shows another embodiment of the signal detection circuit of the present invention, in which the same parts as in the previous embodiment are given the same reference numerals. In the embodiment described above, a single comparator 2 was used, and the comparison level V _REF was set for the positive amplitude of the input signal, but in this embodiment, a pair of comparators 2A and 2B are installed, and one A common input terminal 4A is formed between the non-inverting input terminal (+) of the comparator 2A and the inverting input terminal (-) of the other comparator 2B, and an input signal is applied to the inverting input terminal (-) of the comparator 2A. The formed input terminal 4B has a comparison level V _REF1 from the voltage source 6A, and a non-inverting input terminal (+) of the comparator 2B.
It is assumed that a comparison level V _REF2 (<V _REF1 ) is individually set from the voltage source 6A to the input terminal 4C formed at . In particular, if this reference level V _REF2 is set on the negative side of the input signal amplitude, it becomes possible to detect both waves.

Then, the outputs of the comparators 2A and 2B are outputted via the OR circuit 42, and supplied to the same circuit as in the previous embodiment.

If this is done, the operating waveform will be as shown in FIG. Figure 6 A and B are Figure 4 A and B
Correspondingly, in the waveform shown in FIG. 6B, the voltage levels V _REF1 and V _REF2 indicate comparison levels. FIG. 6C shows the output of the OR circuit 42 obtained by combining the outputs of the comparators 2A and 2B. Also,
6D to I correspond to FIG. 4D to I.

In this case, since the positive and negative amplitude levels of the input signal are detected, the density of the total number of output pulses of the comparators 2A and 2B becomes higher, and the pulse interval from power-on becomes narrower. When a transient signal does not occur, there are advantages in that the response speed for detecting the input signal waveform becomes faster and the possibility of failure to detect the input signal waveform decreases.

Although the waveform generation circuit 8 and the switching circuit 16 in the embodiment have been described as being common to the circuit shown in FIG. Effects can be expected, and the circuit is not limited to the circuit of the embodiment.

As explained above, according to the present invention, since the detection of the input signal in the arrival section of the transient signal generated in the transient state when the power is turned on is prevented, only the regular input signal that should be detected can be selectively detected. , it is possible to prevent malfunctions in signal detection due to transient signals and improve the reliability of signal detection.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a conventional signal detection circuit, FIG. 2 is an explanatory diagram showing its operating waveforms, FIG. 3 is a circuit diagram showing an embodiment of the signal detection circuit of the present invention, and FIG.
FIG. 5 is a circuit diagram showing another embodiment of the signal detection circuit of the present invention, and FIG. 6 is an explanatory diagram showing its operating waveforms. 2, 2A, 2B... comparator, 8... waveform generation circuit, 10... first transistor, 12... first
resistor, 14... capacitor, 16... first switching circuit, 22... second transistor,
26... Second resistor, 28... Frequency divider circuit, 36...
. . . flip-flop circuit, 38 . . . second switching circuit, 40 . . . third transistor.

Claims (1)

[Claims] 1. A comparator that compares an input signal with a reference level and generates an output depending on the magnitude relationship between the two, and a series circuit of a first resistor and a capacitor between the power supply and the reference potential point. and the capacitor is connected in parallel between the collector and emitter of a first transistor whose output is applied to the base of the comparator through a second resistor for switching. A waveform generation circuit that generates a waveform by switching the first transistor according to the output and controlling the capacitor to a charging or discharging state; and a first switching circuit that generates an output according to switching of the second transistor, the signal detection circuit divides the output generated by the comparator. A frequency divider circuit, a flip-flop circuit that receives the output of this frequency divider circuit as a set input, receives a reset pulse when the power is turned on as a reset input, and switches to generate an output; and a flip-flop circuit that receives the output of this flip-flop circuit as a base and conducts the A collector of a third transistor is connected to a base of the first transistor, and an emitter of the third transistor is commonly connected to an emitter of the first transistor. a second switching circuit that forcibly shifts the base of the first transistor to a non-conducting level by making a third transistor conductive, thereby canceling the output of the waveform generating circuit; signal detection circuit. 2. The comparator includes a first comparator that has a first reference level set, and a second comparator that has a second reference level that is different from the first reference level. A second comparator compares the input signal with the first and second reference levels, and outputs obtained from the first and second comparators are input to the frequency dividing circuit through an OR circuit. The signal detection circuit according to claim 1, characterized in that: