JPH0553909A - Cache memory control system for image data processing - Google Patents

Abstract

PURPOSE:To constitute one block of a cache memory while containing the longitudinal picture elements of an image memory. CONSTITUTION:This system is equipped with a cache memory 10 to copy one part of the picture elements in an image memory 1 with the plural picture elements longitudinally and laterally continued in the image memory 1 as the data of one block and a tag table 9 to store data as the index of a block 2 stored in the cache memory 10 while using the address of the image memory 1. The cache memory 10 is composed of data blocks corresponding to the respective tags of the tag table 9 and defines a byte select address in the block of the cache memory 10 by combining the value of one digit or plural digits containing the least significant digits of digits 7 and 8 expressing the horizontal address of the image memory 1 outputted from a processor with the value of one or plural digits containing the least significant digits of digits 4, 5 and 6 expressing the longitudinal position of the image memory 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cache memory control system in image data processing provided with a cache memory.

In an image data processing system, a part of the image data in the image memory is copied to a high speed cache memory, and the copied data is accessed in the cache memory so that an image is created or changed. We are trying to speed up the process.

[0003]

2. Description of the Related Art FIG. 4 shows an image data processing system having a conventional cache memory. In the figure, 100 is a processor, 101 is an image memory, 102 is a part of image data, and 103 is a cache memory for copying a part 102 of the image data. 104 is an image memory,
The block is a unit of copying data to the cache memory 103, and is composed of a plurality of continuous pixels. 1
04 'represents a copy of block 104.

The operation of the configuration shown in the figure is as follows. The image processor 100 performs a calculation for generating an image such as a straight line and a circle, and writes the calculation result in the image memory 101. Also,
When changing the image drawn in the image memory 101, the processor 100 reads the image data from the image memory 101, performs an operation, and writes the operation result in the image memory 101.

In the above processing, when the processor 100 reads the image data, the processor 100 accesses the cache memory 103, and if there is image data at the read address, the data is read, the operation is performed, and the data is written back to the cache memory. At the same time, the data on the same image memory is rewritten. If there is no data at the address to be read in the cache memory 103, the data is read from the image memory 101 and the calculation result is written back to the same address in the image memory. Then, a plurality of consecutive pixels including the pixel of the address of the calculation result are regarded as one block and the cache memory 1
Replace with the data of 1 block of 03.

According to the above configuration, since the access time of the cache memory 103 is shorter than the access time of the image memory 101, if the ratio (hit rate) that can be processed by the access of the cache memory 103 is high, the processing will be executed. It will be faster.

FIG. 5 shows the relationship between the address array of the conventional image memory and the block of the cache memory. In the figure, 105 is an image memory, which represents an array corresponding to an image image of 2048 bits (256 bytes) in the horizontal direction and 1024 bits in the vertical direction. Reference numeral 105 'denotes one horizontal line, which represents the horizontal direction when the image memory is represented by a vertical and horizontal array. Then, the horizontal 8 dots x vertical 1 bit of the image memory is set as 1 byte, and the addresses are sequentially set in the horizontal direction (the arrow directions of the first horizontal line and the second horizontal line in the figure) from the upper left of the image memory array. Then, when it reaches the right end, it continues to the right end following the left end one line down. 106 represents the pixel at address m. 107 is a pixel vertically above the pixel 106 at the address m (m-256), and 108 is a pixel vertically below the pixel 106 at the address m (m + 256).
address). Reference numeral 109 represents one block of pixels stored in the cache memory.

Conventionally, when copying to the cache memory, pixels that are continuous in the horizontal direction on the image memory are copied as one block. For example, as shown in the drawing, data of 16 × 8 pixels (16 bytes) continuous from the address m in the horizontal direction is copied as one block of data.

FIG. 6 shows a conventional cache control method.
In the figure, 110 is a CPU address (32 bits), which is the address of the image memory output from the processor. When accessing the cache memory 112, the addresses are configured as shown in the figure. A tag table 111 serves as an index table for data stored in the cache memory.
Reference numeral 112 represents a cache memory, and 113 represents one block (16 bytes) of data stored in the cache memory. Reference numeral 114 is a tag portion (upper 20
(Bit), which is a search index when written in the cache memory and is data that is written in the tag table. An index portion (8 bits) 115 gives an index (address) of the position where the tag portion is written to the tag table 111. Reference numeral 116 denotes a byte selection address portion (4 bits) in the block, which gives a byte selection address in the block. 117 is a comparator,
The index table 115 of the CPU address 110 refers to the tag table 111 to determine whether the tag parts 114 match.

The operation of the configuration shown in the figure will be described. When reading data, the index part 1 of the CPU address 110
If the tag table 114 is referred to in step 15 and the tag table 114 is matched, the byte selection address part 116 of the CPU address 110 reads the data of the matched block.

When writing to the cache memory 112, the index section 11 of the CPU address 110 is used.
5 to refer to the tag table 111 (for example, if the 8-bit index part represents a decimal number 4 and then refer to the fourth part of the tag table), if the tag part 114 matches, Data is stored at the obtained address by the byte selection address 116.

[0012]

In the conventional cache control method, since one block of data is continuous in the horizontal direction on the image, the probability of hitting is low when drawing in the vertical direction. For example, in FIG. 5, when the data at the address m is processed and the pixels consecutive from the address m in the horizontal direction are stored in the cache memory, next, m + 25
When processing the data at address 6, the data does not exist in the block copied to the cache memory immediately before.
Therefore, the processor had to access the image memory and read the data at the address m + 256 unless a cache hit was made to another block.

Further, in the case of including one pixel in the vertical direction on the image memory into one block, the address array in the image memory has to be changed. This point in the problem to be solved by the invention will be described with reference to FIG.

(A) shows the structure of a conventional block. In the figure, 120 is a CPU address (representing the address of the image memory output from the CPU. The same applies hereinafter),
The figure shows the byte selection address in the block at address m (lower 4
It shows the case where the bit) 121 is “0000”.

Reference numeral 122 represents data of 16 × 8 pixels (16 bytes) continuous from the address m. CPU as shown
Selected address in address block (lower 4 bits)
Was used to access one block of the cache memory.

FIG. 1B illustrates an arrangement of a conventional image memory, which is a block including vertical data.
In the figure, reference numeral 130 indicates a case where horizontal 8 × 8 pixels and vertical 2 pixels form one block. Lower 4 of CPU address at address m
If the bit is the byte selection address in the block, m
The lower 3 bits of the address and the address m + 256 have the same address. Similarly, the m + 1 address and the m + 257 address are the lower 3
The bits have the same address, and the lower 4 bits of the CPU address cannot be used as a byte selection address in the block of the cache memory.

It is an object of the present invention to provide a cache control system which makes it possible to configure one block of a cache memory so as to include a vertical pixel on an image memory by using a CPU address.

[0018]

According to the present invention, by changing the correspondence between the CPU address and the address of the cache memory, the vertical pixel on the image memory can be displayed without changing the address array of the standard image memory. It became possible to make the included cache memory one block of data.

FIG. 1 shows the basic configuration of the present invention. In the figure, reference numeral 1 is an image memory, and as an example, a case of horizontal 8 bytes x vertical 4 bits is shown. Also, as an example, one block written in the cache memory is composed of horizontal 2 × 8 pixels × vertical 2 pixels. Reference numeral 2 represents one block written in the cache memory. The address of the upper left pixel of the image memory is "... 00000", and the lower 5 digits of each pixel address are shown. For example, image unit A
(1 byte pixel) is "... 00010" or the like.
Reference numerals 3 and 3'represent CPU addresses, which represent a byte selection address in a block of the cache memory by a set of a numerical value of a least significant digit and a digit representing a horizontal address. The portions 5 and 7 of the lower digits of the CPU address 3'excluding the byte selection addresses 8 and 6 in the block from the lower digits are used as the index portion and used as the index of the tag table 9. C
The high-order plural digits of the PU address 3'are the tag section 4. Reference numeral 9 is a tag table, 10 is a cache memory, and 11 is data of the tag unit 4 written in the tag table, and the writing position is specified by the values of the index units 5 and 7. Reference numeral 12 is a block written in the cache memory, which is a copy of the block 2 of the image memory 1. Reference numeral 14 is a comparator for comparing the tag unit 4 with the data 11 in the tag table 9, and 15 is a cache memory 10.
Is a data output control unit that outputs the data.

[0020]

The operation of copying the data of the illustrated block 2 to the cache memory 10 will be described as an example.

Since the lower 5 digits of the address of the image unit A of the block 2 is "00010", the byte selection address (,) in the block is (0,0). Therefore, the byte selection address in the block of A is (0,0). Similarly, the image units B, C, and D are represented by a set of selected addresses (,) in the block, respectively (0, 1),
It becomes (1,0) and (1,1). Index part 5, 7
Is "001" when it has three digits. Therefore, the value of the tag portion is written in the position of the index "001" of the tag table, and the data of the image units A, B, C, D are written in the corresponding blocks of the cache memory.

When reading the data of the cache memory 10, first, the comparator 14 compares the tag data of the CPU address 3 with the tag data 11 in the tag table 9. If there is a match, the CPU address data exists in the cache memory 10. Therefore, the block of the cache memory 10 corresponding to the tag table 9 is selected, and it is needed by the byte selection address in the CPU address block. The data is output from the data output control unit 15.

[0023]

FIG. 2 shows an embodiment of an image memory to which the present invention is applied. In the figure, reference numeral 20 denotes an image memory, which has a width of 2
This represents an array corresponding to a 048-bit (256-byte) vertical 1024-bit image. 20 'is one horizontal line and represents the horizontal direction of the image memory. Then, the addresses are sequentially specified in the horizontal direction from the upper left of the array of the image memory in the horizontal direction. Reference numeral 21 represents one block, which is composed of 128 pixels (16 bytes) of 32 pixels horizontally by 4 pixels vertically. A represents the pixel at the address m. D, E, I, M, P are each m
+3, m + 256, m + 512, m + 76
It represents the pixel at address 8 and m + 771.

In the present invention, one block is composed of pixels including, for example, pixels E, I, M which are continuous in the vertical direction. FIG. 3 shows the configuration of an embodiment of the present invention.

In the figure, 30 is a CPU address, which is composed of 32 bits (digits), and the lower 8 bits (00
Digits to 07 digits) specify an address in the horizontal direction. Reference numeral 31 is a tag table, which has 256 entries (256 addresses) and is used to write 20-bit (digit) data in the tag section 35. Reference numeral 32 denotes a cache memory which has vertical 256 addresses corresponding to the index of the tag table and stores pixels of one block at 16 addresses. Reference numeral 33 is a comparator for comparing the tag section 35 of the CPU address 30 with the data of the tag table. Reference numeral 34 represents one block of data in the cache memory 32 (A, D,
E, I, M and P correspond to each of FIG. 2).

Reference numeral 35 denotes a tag portion in the CPU address 30, which is the upper 20 bits (12 digits to 12 digits) of the CPU address.
(31 digits). 36 and 37 are index parts, which are 8 bits (02 digits to 07 digits and 08 digits to 09 digits)
It is composed of. 38 and 39 are selected addresses in the block of the cache memory 32, and are 08 digits to 09 digits () and 00 digits to 01 digits () of the CPU address.
The address in the block is specified by the data set of. The selected address within the block is an address that gives the position in the vertical direction within the block of FIG.

The operation of the configuration shown in the figure will be described. Refer to FIG. 2 as needed. A case where the block 21 in FIG. 2 is copied will be described. When writing, first, from the 8-bit data of the index parts 36 and 37, the tag table 3
The address of 1 is designated and the data of the tag section 35 is written in the tag table 31. Furthermore, the selected address in the block is set to 00 in the corresponding cache memory 32.
Data A of () 00 () is set to the head, and each data B
Write ~ P. At this time, the address of each data is skipped every 4 bytes, but since the selected address in the block of the cache memory is specified by the digit of (,) of the CPU address 30, A, B, C, D, E In the order of to P, the selected addresses in the block are continuous addresses from (0000) to (1111).

When reading, 20 bits of the tag portion 35 (12 digits to 31 digits) of the CPU address 30 are compared with the data written in the tag table 31 by the comparator 33. Then, if there is a match, the corresponding data is output as the selected address in the block of the cache memory 32 according to the CPU address.

According to the present invention, since one block of the cache memory includes pixels in the vertical direction in the image memory, the hit rate in drawing in the vertical direction is high.
For example, when there is no hit at the address m, the pixel data of the block 21 starting from the address m is written in the cache memory (copied from the image memory to the cache memory). When rewriting the data at the address m + 256, since the pixel E at the address m + 256 is written in the cache memory, the processor performs read access to the cache memory, retrieves the data, performs arithmetic processing, and then again in the cache memory and the image memory. Just write it back.

[0030]

According to the present invention, with the standard address arrangement of the image memory, it is possible to include consecutive pixels in the vertical direction in the block to be copied in the cache memory. Therefore, the hit rate in the image processing in the vertical direction is improved, and the image processing can be speeded up.

[Brief description of drawings]

FIG. 1 is a diagram showing a basic configuration of the present invention.

FIG. 2 is a diagram showing a relationship between an address array of an image memory and blocks of a cache memory according to the present invention.

FIG. 3 is a diagram showing a configuration of an embodiment of the present invention.

FIG. 4 is a diagram showing an image data processing system including a conventional cache memory.

FIG. 5 is a diagram showing a relationship between an address array of a conventional image memory and a block of a cache memory.

FIG. 6 is a diagram showing a conventional cache control method.

FIG. 7 is an explanatory diagram of a problem to be solved by the invention.

[Explanation of symbols]

 1: Image memory 2: Block 3, 3 ': CPU address 4: Tag part 5: Index part 6: Byte selection address in block 7: Index part 8: Byte selection address in block 9: Tag table 10: Cache memory 11: Data of tag part 12: Copy data 14: Comparator 15: Data output control part

Claims (2)

[Claims] 1. A cache memory control method for image data processing, wherein a part of the pixels of the image memory (1) is copied with a plurality of pixels continuous in the vertical and horizontal directions of the image memory (1) as one block of data. Cache memory
(10) and a tag table (9) that stores data as an index of the block stored in the cache memory using the address of the image memory (1), and the cache memory (10)
Is the lowest digit of the digit representing the horizontal direction of the address of the image memory (1) output from the processor, in which the blocks are arranged in the vertical direction of the matrix and the pixels of block (2) are arranged in the horizontal direction of the matrix. One or more digits including
The image memory (1) output from the processor is used as the byte selection address in the block of the cache memory with a set of one digit or multiple digits including the least significant digit of the vertical position of the image memory (1). ) The tag part of the address is compared with the index of the tag table (9), and if they match, the data of the block corresponding to the index is read or written at the byte selection address (6, 8). Cache memory control method for image data processing. 2. The image memory (1) according to claim 1, comprising one or more digits including a least significant digit of an address of the image memory (1) and an upper digit next to a most significant digit representing a horizontal address.
A cache memory (1
Byte selection address (6,
8), and a part of the upper digits is used as the index of the block as the tag part (4), and part of the part excluding the byte selection address part (6,8) and the tag part (4) in the above block. Alternatively, the cache memory control method in image data processing is characterized in that an index indicating the position of writing the whole in the index of the tag table is used.