WO2004017640A1

WO2004017640A1 - Signal processor and system

Info

Publication number: WO2004017640A1
Application number: PCT/JP2002/008236
Authority: WO
Inventors: Yukifumi Kobayashi; Hiroshi Hatae; Hiromi Watanabe
Original assignee: Renesas Technology Corp.
Priority date: 2002-08-13
Filing date: 2002-08-13
Publication date: 2004-02-26
Also published as: JPWO2004017640A1

Abstract

A signal processor capable of increasing the cache hit ratio while preventing entry conflict between a coded image and a reference image, performing optimum cache control to each image by the capacity, the entry determining method, etc., and increasing the cache hit ratio in the longitudinal direction while preventing entry conflict with a rectangular block in the vicinity of the longitudinal direction. A system using the signal processor is also disclosed. A cache system comprises a cache memory (111) for coded image and a cache control unit (110) thereof, a cache memory (113) for reference image, and a cache control unit (112) thereof. A control unit selection circuit (114) determines whether the image is a coded image or a reference image according to the accessed address. If the access is made to the coded image, cache control for the coded image is performed. If the access is made to the reference image, cache control for the reference image is performed. Thus, the data cached to be is stored in each independent entry.

Description

Specification

Signal processing equipment and systems

The present invention relates to a signal processing device, and more particularly to a technology that is effective when applied to a control method of an image cache memory. Background art

According to the studies made by the present inventors, the following techniques can be considered for an image signal processing device.

Currently, LSIs that realize compression and decompression processing of moving images such as MPEG-4 are being developed. When performing this compression / expansion processing, a large amount of data access occurs between the image memory and the image processing processor. In general, image memory has a large capacity, so large-capacity but slow-speed memory such as DRAM is often used. Therefore, a cache memory may be provided between the processor and the memory to improve speed.

As a technique relating to a cache system having such a cache memory, for example, a technique described in Japanese Patent Application Laid-Open No. 5-52909 is cited. This gazette discloses a system having a cache memory for storing data in units of blocks in an MPEG / hardware accelerator. However, this technique has only one side of cache memory.

By the way, when a cache system having a cache memory as described above is applied to image processing, the first problem is that the same cache control is performed in both the processing of an encoded image and the processing of a reference image. Normally, in image processing, the coded image and the reference image are accessed frequently, but the address of the pixel data of the coded image and the address of the pixel data of the reference image are far apart at that time. .

Therefore, in the case of the cache system described above, the entry is determined Since it is determined by the lower bits of the address, entry conflicts are more likely to occur when frequent access to distant locations in memory occurs. Therefore, if the access to the coded image and the access to the reference image are performed alternately, frequent access to a distant location in the memory may occur, causing frequent contention for the entry. is there. If an entry conflict occurs, the entry is replaced with newer data, and the cache hit rate decreases.

Also, the coded image and the reference image have different access characteristics. For example, in motion vector detection in MPEG, encoding is performed for a coded image. Power that is frequently accessed for a block of 16 × 16 pixels s, and for a reference image, a block of a search range is searched. (For example, 48 x 48 pixels, assuming ± 16 pixels in both X and Y directions). If the same control method is used for different access characteristics, there is a problem that the capacity is increased.

The second problem is that the cache memory uses an address to determine the data entry that stores data in units of blocks in order to increase the cache hit ratio of pixels in the vertical direction. The size of the direction is limited to a power of two. If the horizontal size of the image is other than a power of two, entry conflicts will occur, and the vertical pixel cache hit rate will decrease.

Therefore, a first object of the present invention is to solve the first problem and increase the cache hit rate by preventing entry conflicts between an encoded image and a reference image. Another object of the present invention is to provide a signal processing device capable of performing optimal cache control for each image in terms of capacity, entry determination method, and the like, and a system using the same.

Further, a second object of the present invention is to solve the second problem and increase the vertical hit ratio by preventing a rectangular block in the vertical direction from causing contention of an entry. Provide a signal processing device capable of freely selecting an image size and a system using the same Is to do.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings. Disclosure of the invention

The following is a brief description of the outline of typical inventions disclosed in the present application.

In order to achieve the first object, the present invention has a cache memory for an encoded image and its cache control unit, a cache memory for a reference image and its cache control unit, and is accessed by a selection circuit. It determines whether the image is a coded image or a reference image based on the address, and performs cache control for the coded image if access to the coded image, and cache control for the reference image if access to the reference image. The data to be cached is stored in each independent entry. This control prevents entry conflicts between the encoded image and the reference image, and increases the cache hit rate. In addition, since cache control is performed independently, it is possible to perform optimal cache control for each image using the capacity and entry determination method.

Further, according to the present invention, in order to achieve the second object, in each cache control method, one entry stores image data that is a rectangular block on an image, and specifies the pixel data to be accessed. Specifies the horizontal and vertical positions of the rectangular block, the horizontal and vertical pixel positions of the rectangular block 矩形, and determines the entry based on the horizontal and vertical positions of the rectangular block. It is. As a result, since the cached unit is a rectangular block, neighboring pixels exist in the horizontal and vertical directions in one entry, and the cache hit ratio in the vertical direction can be increased. . In addition, the entry of pixel data to be accessed is determined using the horizontal position and the vertical position of the rectangular block. Thus, the rectangular block in the vertical direction does not cause entry competition, so that the cache hit ratio in the vertical direction can be increased, and the size of the image can be freely selected.

Therefore, according to the present invention, the cache hit rate for image data can be improved. Therefore, the bus occupation ratio due to the transfer of image data can be reduced in an image processing apparatus employing the unified memory architecture. As a result, it is possible to realize high-speed processing and low power consumption. BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a block diagram illustrating a cache system according to a first embodiment to which the signal processing device according to the present invention is applied, FIG. 2 is a flowchart illustrating an operation in the cache system according to the first embodiment, and FIG. FIG. 4 is an explanatory diagram showing an access range upon detection of a motion vector, FIG. 4 is a block diagram showing a cache system according to a second embodiment to which the signal processing device according to the present invention is applied, and FIG. 5 is a signal processing device according to the present invention. FIG. 6 is a block diagram showing a cache system according to a third embodiment to which the present invention is applied, FIG. 6 is an explanatory diagram showing an address designation method in the third embodiment, FIG. 7 is an explanatory diagram showing an entry determination method, and FIG. FIG. 9 is a block diagram showing a cache system according to a fourth embodiment to which the signal processing device according to the present invention is applied, and FIG. 10 is a signal processing device according to the present invention. It is a block diagram showing a mobile phone system of the fifth embodiment according to the. BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In all the drawings for describing the embodiments, members having the same functions are denoted by the same reference numerals, and repeated description thereof will be omitted.

(Embodiment 1)

FIG. 1 shows a key according to the first embodiment to which the signal processing device according to the present invention is applied. An example of the configuration of the cache system will be described. FIG. 1 shows a block diagram of a cache system according to the present embodiment.

The cache system according to the present embodiment is, for example, a system that realizes image compression / decompression processing, and includes a cache control unit 100 for controlling a cache operation of image data, and an image processing for processing image data. It comprises a device 101 and an image memory 102 for storing image data. In particular, a feature of the present embodiment is that a cache control unit 100 functioning as a signal processing device is provided with a cache memory for an encoded image and a reference image and a cache control unit therefor, independently of each other. You.

The cache control unit 100 0 is a part that functions as a signal processing device, and includes a coded image cache control unit 110, a coded image cache memory 111, and a reference image cache control unit 112. It consists of image cache memory 113, control section selection circuit 114, signal line selection circuit 115, etc., and is connected to image processing apparatus 101 through a path from the image processing apparatus interface, and image memory Is connected to the image memory 102 through the bus from the user interface. In particular, in the cache control unit 100, the encoded image cache control unit 110 and the reference image cache control unit 112 are independently provided.

In the cache system configured as described above, the image processing device 101 includes an encoded image cache control unit 110 in the cache control unit 100, a reference image cache control unit 112, and a control unit. The selection circuit 114 is connected to the signal line selection circuit 115 through the address path 120, and is connected to the signal line selection circuit 115 through the data bus 122. The image memory 102 is connected to the signal line selection circuit 115 in the cache control unit 100 through address and data paths.

In the cache control unit 100, the encoded image cache control unit 110, the reference image cache control unit 112, and the control unit selection circuit 114 are connected through a control line 122, and the control unit Selection circuit 1 1 4, Signal line selection The selection circuit 1 15 is connected through another control line 1 2 3. Also, between the coded image cache control unit 110 and the signal line selection circuit 115, between the reference image cache control unit 112 and the signal line selection circuit 115, and furthermore, the coded image cache Between the control unit 110 and the coded image cache memory 111, and between the reference image cache control unit 112 and the reference image cache memory 113 through address and data signal lines, respectively. It is connected.

Next, an example of the operation in the cache system of the present embodiment will be described with reference to FIG. FIG. 2 shows a flow chart of the operation in the cache system of the present embodiment.

In the cache system according to the present embodiment, encoding associated with image compression processing is performed between the image processing device 101, the cache memory for encoded image 111, and the cache memory for reference image 113. This is performed, and the data in the image memory 102 is used as needed. The decoding accompanying the image decompression process is performed between the image processing device 101 and the image memory 102. Here, a description will be given of an encoding operation associated with image compression processing which is an object of the present invention.

First, when the image processing apparatus 101 accesses the cache control section 100, the control section selection circuit 114 in the cache control section 100 has an address path 120. Since the connection is established, an address to be accessed through this address path 120 is input (step S 1). In the cache control unit 100, the control unit selection circuit 114 has information on the start address of the encoded image, the image size of the encoded image, the start address of the reference image, and the image size of the reference image. From this information, it is determined whether the input address is an access to an encoded image, an access to a reference image, or an access to any other (steps S2 and S3). .

Based on the result of this determination, if the access is to an encoded image, control is performed so that the encoded image cache control unit 110 performs a cache control operation. Controlled by line 122. When performing the encoded image caching operation, data to be cached in the encoded image cache memory 111 is stored. In addition, the signal line selection circuit 115 selects the coded image cache control unit 110 that has been accessed, and connects it to the image memory 102 and the image processing device 101 by controlling the signal line. Control is performed by 1 2 3 (Step S 4). Also, if the result of the determination is that the reference image is to be accessed, the reference image cache control unit 112 is controlled by the control line 12′2 so as to perform the cache control operation. When the reference image is cached, data to be cached is stored in the reference image cache memory 113. In addition, the signal line selection circuit 115 selects the accessed reference image cache control unit 112 so that the control line is connected to the image memory 102 and the image processing device 101. Control is performed by 1 2 3 (step S 5).

Also, if the result of the determination indicates that the accessed address is neither a coded image nor a reference image, caching is not performed, and the address path 120 and the data path 122 are connected to the image memory 102. Next, the signal line selection circuit 1 15 is controlled (step S6).

As described above, since the dedicated cache memories 1 1 1 and 1 1 3 and the cache controllers 1 1 0 and 1 1 2 are provided for the encoded image and the reference image, respectively, the encoded image and the reference image are Always stored in separate memory, no entry conflicts. In the case of an access that is neither a coded image nor a reference image, the cache operation is not performed, so that the coded image and the reference image are not evicted from the cache memories 111 and 113. As a result, each cache hit rate is improved.

Next, an example of an access range when a motion vector is detected will be described with reference to FIG. Figure 3 shows an explanatory diagram of the access range when a motion vector is detected.

Since the coded image cache control unit 110 and the reference image cache control unit 112 operate independently of each other, their control methods may not be the same. For example, as shown in Fig. 3, the motion vector detection is 16 x 1 When searching for a 6-pixel coded image block in a range of 16 pixels in both the X and Y directions, the coding block requires 16 X 16 pixels, and the reference image requires 48 X 48 pixels. In this case, if the cache capacity of the encoded image is 16 × 16 pixels and the cache capacity of the reference image is 48 × 48 pixels, the efficiency in terms of capacity is improved.

As described above, according to the cache system of the present embodiment, the coded image cache control unit 110 and the reference image cache control unit 112 are operated independently of each other, so that the coded image and the reference image are controlled. There is no entry conflict between the image and other data, and the cache hit rate is improved. Also, since independent control methods can be used for the coded image and the reference image, the capacity, the control method, and the like can be optimized according to the characteristics of the image.

(Embodiment 2)

Referring to FIG. 4, an example of the configuration of a cache system according to Embodiment 2 to which the signal processing device according to the present invention is applied will be described. FIG. 4 shows a block diagram of the cache system of the present embodiment.

The cache system according to the present embodiment is, for example, a system that realizes image compression / decompression processing. As in the first embodiment, a cache control unit 100 a, an image processing device 101, A difference from the first embodiment is that a cache memory for a reference image and its cache control unit are further referred to in forward prediction as an extended example of the first embodiment. In that it is divided into an image and a backward prediction reference image.

■ Puru

That is, in the cache system according to the present embodiment, the cache control unit 100a functioning as a signal processing device includes: a coded image cache control unit 110; a coded image cache memory 111; Reference image cache control unit 210, forward reference image cache memory 211, backward reference image cache control unit 212, backward reference image cache memory 211, control unit selection circuit 114, Signal line selection circuit In particular, a forward reference image cache control unit 210 and a backward reference image cache control unit 212 are independently provided as reference image cache control units.

In the cache control unit 100a, the cache control unit 110 for encoded images, the cache control unit 210 for forward reference images, the cache control unit 212 for backward reference images, and the control unit selection The circuit 1 1 4 is connected through a control line 1 2 2, and the control section selection circuit 1 1 4 and the signal line selection circuit 1 1 5 are connected through another control line 1 2 3. Other connections between the devices are the same as in the first embodiment.

Therefore, according to the cache system of the present embodiment, when the motion vector is predicted from both the forward prediction reference image and the backward prediction reference image, the coded image cache control unit 110 and the forward Each of the reference image cache control unit 210 and the backward reference image cache control unit 212 has its own cache memory 111, 211, 213, and operates independently. There is no entry conflict between the two, and the cache hit rate is improved. In addition, the capacity and control method can be optimized according to the characteristics of each image.

(Embodiment 3)

Referring to FIG. 5, an example of the configuration of a cache system according to Embodiment 3 to which the signal processing device according to the present invention is applied will be described. FIG. 5 shows a block diagram of the cache system of the present embodiment.

The feature of this embodiment is that the unit of data stored in one entry is a rectangular block that is continuous in the horizontal and vertical directions on the image, and the method of specifying pixel data depends on the block position and the position in the block. It is to be done. Here, the cache control of the reference image will be described as an example, but it goes without saying that the present invention can be similarly applied to the cache control of the encoded image.

That is, the cache system according to the present embodiment is a system that realizes, for example, image compression / decompression processing. It comprises an image processing device 101, a cache control unit 112 for reference images and a cache memory 113, a control unit selection circuit 114, a main memory 300, and the like. The main memory 300 corresponds to the image memory 102 of the first embodiment.

The reference image cache control unit 112 includes an entry determination circuit 310, a cache hit determination circuit 3111, a tag memory 3112, a memory controller 3113, and the like. The entry determination circuit 310 has information on the starting address of the reference image and the image size in the X direction, and the address of the accessed pixel in the main memory 300 is determined by the block position and the position in the block. It can be calculated.

Next, an example of an access method in the cache system of the present embodiment will be described.

Since the address bus 120 is connected to the control section selection circuit 114, the upper 16 bits of the address specify whether the access is for the reference image or for an access other than the reference image. For example, assuming that the identification code of the reference image is H ': FF 00, if the upper 16 bits of the input address are H, FF 00, the access is to the reference image, otherwise, It is usually used as a non-cached access specified by 32 bits. For this reason, the address used for the identification code is a prohibited area in normal access.

Since the address path 120 and the data path 121 are connected to the entry determination circuit 310, the register setting is performed from the image processing apparatus 101 through this. The pixel to be accessed is specified by the block position of the pixel and the position in the block. Here, the size of the block is 16 X I 6 pixels. The block position is specified by the register set of the entry decision circuit 310, and the position of the pixel in the block is specified by the lower 16 bits of the address.

When the reference image control selection signal is output from the control unit selection circuit 114, the lower 16 bits of the address indicate the pixel position in the block. The cache memory address is calculated by specifying the position, and the cache access is performed. The position within the block is specified by the position in the X and Y directions. Of the lower 16 bits of the address used to specify the position in the block, the lower 8 bits are specified as the X direction position in the block, and the upper 8 bits are specified as the Y direction position in the block.

Next, an example of a method of designating a position and an address of a plane image will be described with reference to FIG. FIG. 6 shows an explanatory diagram of the address designation method.

As shown in Fig. 6, when accessing the pixel whose block position is (1, 2) and the position in the block is (2, 1), the internal register of the entry decision circuit 310 stores 1 as the X-direction block position. Set 2 as the Y direction block position. After that, in the address, the identification code H 'FFOO of the reference image is assigned to the upper 16 bits, the pixel position H'01 in the Y direction in the block, and the pixel position H, 02 in the X direction are assigned to the lower 16 bits. Then, access with address = H, FF00001102.

Next, an example of an entry determination method will be described with reference to FIG. FIG. 7 shows an explanatory diagram of the entry determination method.

The entry is determined by the following formula, assuming that the horizontal position of the rectangular block is X, the vertical position is y, and the number of entries is mXn.

Entry number = {Remainder of (Xm)} + {Remainder of (y / n)} Xm (1) According to Fig. 7, when the entry number is determined according to equation (1), the block on the image It will be described whether it is stored. Here, the case where the number of entries is 3 X 3 (numbers 0 to 8) is shown, where the block position (6, 3) is entry number 0, and the block position (5, 5) is entry number 8 And is stored in each entry number position. As shown in Fig. 7, the entry number increases by one in the horizontal direction, and returns to the original state at the third. In the vertical direction, the entry number increases by three, and returns to the original state at the third.

Therefore, blocks in less than three locations in both the horizontal and vertical directions do not cause entry conflicts. That is, up to m in the horizontal direction and n in the vertical direction Blocks within this position do not cause entry conflicts. Therefore, the cache hit ratio of the neighboring pixels in both the horizontal and vertical directions is improved.

The tag at this time is represented by the following equation.

Tag = {quotient of (x / m)} + {quotient of (y / n)} X m (2) At the position in the tag memory 312 corresponding to the entry determined by the formula (1), the formula ( 2) is stored.

Next, an example of the operation of the cache system according to the present embodiment will be described.

The X-direction block position and the Y-direction block position of the reference image to be accessed by the image processing apparatus 101 are set in the internal register of the entry determination circuit 310. When an address is input from the address bus 120, the control unit selection circuit 114 checks the upper 16 bits to determine whether the access is to the reference image or to an access other than the reference image. If the access is to the reference image, the reference image control selection signal is output to the entry decision circuit 310.

When the reference image control selection signal is input, the entry determination circuit 310 determines the entry and tag according to the expressions (1) and (2) according to the value set in the internal register, and the cache hit determination circuit 310 1 Output to 1. Also, it calculates the address for the main memory at the time of a miss from the reference image start address, the X-direction image size, the block position, and the cache memory address from the position in the block, and outputs them to the memory controller 313.

The cache hit determination circuit 311 compares the value of the tag memory 312 corresponding to the input entry with the input tag. As a result of the comparison, a hit signal is output to the memory controller 3 13 if they match, and a mismatch signal is output if they do not match. In the case of a miss, the tag memory 3 1 2 is rewritten with the input tag.

The memory controller 3 1 3, when the hit determination, accessing Kiya' Shumemori 1 1 3 in accordance with key Yasshu memory for real Adoresu inputted from the entry determination circuits 3 1 0, and outputs the data to the data path 1 2 1 _c In the case of a mishit determination, replace all 16 x 16 pixels of the corresponding entry, and then output the data.

Next, an example of the operation at the time of mishit will be described with reference to FIG. Fig. 8 is an explanatory diagram of the operation during a miss.

Here, a case where a miss occurs when accessing the pixel of the (1, 1) block is shown. If the reference image storage start address is H'0 00 0 and the image X-direction size is 176 pixels, the start address of (1, 1) is H'0B10, and the Y-direction increment value. (The sum of the next address in the Y direction) is H, BO. These values are passed from the entry determination circuit 310. Block position (1, 1) is stored in entry number 4 from equation (1) above.

The memory controller 3 13 accesses the main memory 3 0 0, and first transfers one line (16 bytes) of H 'OB 1 0, which is the first address, to the entry number 4 of the cache memory 1 13 from above. Store in order. The Y-direction increment value (Η'BO) is added to the address of main memory 300, and the next address (Η'0BC0) is accessed, and the entry number of cache memory 113 is added. Store in order in 4. This is repeated for 16 lines. One block (16 x 16 pixels) is replaced. Then, it accesses the cache memory 113 according to the actual address for the cache memory, outputs data to the data bus 121, and completes the operation.

As described above, according to the cache system of the present embodiment, a rectangular block is stored in one entry, and the pixel is specified at the block position and the position in the block. As a result, the cache hit ratio of nearby pixels is improved. Also, the size of the image can be freely selected.

(Embodiment 4)

Referring to FIG. 9, an example of the configuration of a cache system according to Embodiment 4 to which the signal processing device according to the present invention is applied will be described. FIG. 9 shows a block diagram of the cache system of the present embodiment. A feature of the present embodiment is that a cache control unit for an image and a cache control unit for a normal arithmetic processing device are separately provided, and are connected to a main memory via a path.

That is, the cache system according to the present embodiment includes an image processing device 101 for processing image data, an image cache control unit 400 for controlling the image data caching operation, and a cache operation image. An image cache memory 401 for storing data, a main memory 402 for storing image data and an instruction code and other data for an arithmetic processing device, and an other for an arithmetic processing device. An arithmetic processing unit 403 for performing arithmetic processing on the data of the same, a cache control unit for arithmetic processing unit 404 for controlling a cache operation of other data, and a cache control unit 404 for storing other data of the cache operation. It is composed of a cache memory for arithmetic processing device 405 and the like.

The image processing apparatus 101 performs processing relating to image data. The image processing device 101 requests the image cache controller 400 to access the image data. If the image data is a cache hit, the cache control unit 400 accesses the image cache memory 401 and outputs the data to the image processing device 101. If it is a miss, the main memory 402 is accessed via the bus 420, the data is replaced with the data of the image cache memory 401, and the data is output to the image processing apparatus 101. The control method of the cache adopts the method described in the first embodiment, and is suitable for an image.

Next, an example of the operation of the arithmetic processing unit 403 will be described.

The arithmetic processing unit 403 mainly handles data other than image data. The arithmetic processing unit 403 issues a data access request to the arithmetic processing unit cache control unit 404. In the cache control unit 404, if the data is a cache hit, it is stored in the cache memory 405 for the arithmetic processing unit. And outputs data to the arithmetic processing unit 403. If it is a miss, the main memory 402 is accessed through the path 420, the data is replaced with the data in the cache memory for the processing unit 405, and the data is output to the processing unit 403. The arithmetic processing unit 403 mainly handles data other than images, such as instruction codes, so that a conventional cache control suitable for such control is performed.

As described above, according to the cache system of the present embodiment, the image processing device 101 has the image cache control unit 400, and the arithmetic processing device 400 has the arithmetic processing device cache control unit 400. By independently providing cache control, a cache control method suitable for each process can be applied. As a result, the cache hit rate increases in each process.

(Embodiment 5)

An example of the configuration of a mobile phone system according to a fifth embodiment to which the signal processing device according to the present invention is applied will be described with reference to FIG. FIG. 10 shows a block diagram of the mobile phone system of the present embodiment.

The feature of this embodiment is that it is applied to a mobile phone system as a specific product.

That is, the mobile phone system according to the present embodiment includes a mobile phone main unit 500 on which the main part of the mobile phone system is mounted, a microphone 501 for inputting voice, and a speaker for uttering voice. It is composed of a device 502, a camera 503 for capturing an image of an object, an LCD 504 for displaying an image, and the like.

The mobile phone main body 500 has an RF circuit 510 that has the function of modulating and demodulating transmitted and received signals, a baseband processor 511 that has a function of controlling transmission and reception, and stores data such as voice and images Main memory 511, Camera DSP 513 for digitally processing image signals captured by camera 503, Application processor 515 including cache memory 514 for executing various application processes, LCD 505 It is composed of an LCD interface 516 that controls the interface with the ing. The main memory 512 is connected to the baseband processor 511 and the cache memory 514 via a path 520, and stores audio data, image data, and the like.

The basic operation during reception is as follows. In the RF circuit 510, a radio wave received by an antenna is converted into an intermediate frequency signal via a filter, an amplifier, a mixer, and the like. Then, in the baseband processor 511, the intermediate frequency signal is demodulated into a baseband signal, which is then decomposed by a channel codec, and the necessary channel audio signal is converted into an analog audio signal by an audio codec. It is uttered from 02. At this time, the baseband processor 511 stores data in the main memory 512 at any time, reads out necessary data and executes each processing. The basic operation at the time of transmission is as follows. In step 1, a signal input from microphone 501 and digitized by a voice codec is converted by a channel codec, and shaped into a waveform suitable for transmission by a waveform shaping circuit. At this time, the baseband processor 511 stores data in the main memory 512 as needed, reads out necessary data, and executes each process. Thereafter, in the RF circuit 510, the signal is modulated at an intermediate frequency, further converted to a radio frequency via a mixer or the like, amplified by an amplifier, and then transmitted from an antenna via a filter.

The operations related to the image capturing function of the camera 503 and the display function on the LCD 504 are performed by digitally processing the image signal captured by the camera 503 by the camera DSP 513, and further by the application processor 515. It performs data processing for display on the LCD 504 and data processing for transmission on radio waves together with voice. At this time, the application processor 515 stores data in the main memory 512 as needed, and stores necessary data in the cache memory 514 by a cache operation to execute each process.

Then, the signal processed for display on the LCD 504 is displayed as an image on the LCD 504. Also, put it on the radio wave with the sound The signal processed for transmission is transmitted from the antenna together with the voice, and displayed as an image on the other party's LCD.

As described above, according to the mobile phone system of the present embodiment, by applying the cache system to the mobile phone system, the same effects as those of the first to fourth embodiments can be obtained.

As described above, the invention made by the inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and can be variously modified without departing from the gist of the invention. Needless to say. Industrial applicability

As described above, the signal processing device according to the present invention is particularly applicable to a control system for an image cache memory, and further to a control system cache system in which an image cache memory and a normal operation device cache memory are separately provided. It is useful when applied, and can be widely applied to mobile terminal systems such as mobile phones.

Claims

The scope of the claims

1. Encoded image cache memory for image data,

An encoded image cache control unit that controls a cache operation for the encoded image cache memory;

A reference image cache memory for the image data,

A reference image cache control unit that controls a cache operation for the reference image cache memory;

The cache control by the coded image cache control unit and the cache control by the reference image cache control unit are performed independently, and the independent entries of the coded image cache memory and the reference image cache memory are performed. And a selection circuit for storing image data to be cached.

2. The signal processing device according to claim 1,

The reference image cache memory has a forward prediction reference image cache memory and a backward prediction reference image cache memory,

The reference image cache control unit includes a forward prediction reference image cache control unit and a backward prediction reference image cache control unit,

The selection circuit independently performs cache control by the forward prediction reference image cache control unit and cache control by the backward prediction reference image cache control unit. A signal processing device for storing data to be cached in an entry of a backward prediction reference image cache memory.

3. The signal processing device according to claim 1,

The signal processing device, wherein the encoded image cache memory and the reference image cache memory have a rectangular block on an image as a unit of image data stored in one entry.

4. The signal processing device according to claim 3,

The cache control unit for the encoded image and the cache control unit for the reference image, when designating pixel data to be accessed, The horizontal position and vertical position of the rectangular block and the horizontal pixel position and vertical pixel position in the rectangular block are specified, and the entry is determined by the horizontal position and vertical position of the rectangular block. Signal processing device characterized by the above-mentioned.

5. The signal processing device according to claim 2,

The coded image cache memory, the forward prediction reference image cache memory and the backward prediction reference image cache memory may be configured such that a unit of image data stored in one entry is a rectangular block on an image. Characteristic signal processing device.

6. The signal processing device according to claim 5,

The cache control unit for the coded image, the cache control unit for the forward prediction reference image, and the cache control unit for the backward prediction reference image, when designating pixel data to be accessed, the horizontal direction of the rectangular block. The position is specified by a position, a vertical position, a horizontal pixel position and a vertical pixel position in the rectangular block, and an entry is determined by the horizontal position and the vertical position of the rectangular block. Signal processing device.

7. The signal processing device according to claim 1, 2, 3, 4, 5, or 6, wherein an image memory interface for connecting an image memory for storing the image data,

An image processing device interface for connecting an image processing device that processes the image data,

The signal processing device is connected to the image memory through a path from the image memory interface, and is connected to the image processing device through a bus from the image processing device interface. apparatus.

8. The signal processing device according to claim 1, 2, 3, 4, 5, or 6, wherein a memory interface for connecting a memory that stores the image data and other data in a shared manner;

Image processing for connecting an image processing device for processing the image data A device interface;

An arithmetic processing device interface for connecting the arithmetic processing device that processes the other data,

The signal processing device is connected to the memory through a bus from the memory interface, is connected to the image processing device through a bus from the image processing device interface, and is connected to the image processing device through a bus from the arithmetic processing device interface. A signal processing device connected to a processing device.

9. Encoded image cache memory for image data, Encoded image cache control unit for controlling a cache operation on the encoded image cache memory, Reference image cache memory for the image data, The reference image A cache control by the reference image cache control unit and a cache control by the coded image cache control unit, and a cache control by the reference image cache control unit. A signal processing device including: the encoded image cache memory; and a selection circuit that stores image data to be cached in an entry of the reference image cache memory.

An image memory that is connected to the signal processing device through a path and stores the image data;

An image processing device connected to the signal processing device through a path and configured to process the image data.

10. Encoded image cache memory for image data, Encoded image cache control unit that controls a cache operation for the encoded image cache memory, Reference image cache memory for the image data, and Reference image A cache control unit for controlling the cache operation for the cache memory for the reference image, a cache control by the cache control unit for the coded image, and a cache control by the cache control unit for the reference image. Cache the entries in the coded image cache memory and the reference image cache memory. A signal processing device having a selection circuit for storing image data to be processed, a memory connected to the signal processing device via a bus, and sharing and storing the image data and other data;

An image processing device that is connected to the signal processing device through a path and processes the image data;

A system connected to the memory via a bus and configured to process the other data.